1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/bl_common.h> 10 #include <common/debug.h> 11 #include <drivers/console.h> 12 #include <drivers/generic_delay_timer.h> 13 #include <lib/mmio.h> 14 #include <plat/common/common_def.h> 15 #include <plat/common/platform.h> 16 17 #include <mcucfg.h> 18 #include <mtcmos.h> 19 #include <mtk_plat_common.h> 20 #include <plat_arm.h> 21 #include <plat_private.h> 22 #include <spm.h> 23 24 static entry_point_info_t bl32_ep_info; 25 static entry_point_info_t bl33_ep_info; 26 27 static void platform_setup_cpu(void) 28 { 29 /* turn off all the little core's power except cpu 0 */ 30 mtcmos_little_cpu_off(); 31 32 /* setup big cores */ 33 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, 34 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | 35 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | 36 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | 37 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | 38 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); 39 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); 40 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, 41 MP1_SW_CG_GEN); 42 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, 43 MP1_L2RSTDISABLE); 44 45 /* set big cores arm64 boot mode */ 46 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, 47 MP1_CPUCFG_64BIT); 48 49 /* set LITTLE cores arm64 boot mode */ 50 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, 51 MP0_CPUCFG_64BIT); 52 53 /* enable dcm control */ 54 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, 55 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN | 56 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN | 57 INFRACLK_PSYS_DYNAMIC_CG_EN); 58 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, 59 L2C_SRAM_DCM_EN); 60 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, 61 MCU_BUS_DCM_EN); 62 } 63 64 static void platform_setup_sram(void) 65 { 66 /* protect BL31 memory from non-secure read/write access */ 67 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); 68 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); 69 } 70 71 /******************************************************************************* 72 * Return a pointer to the 'entry_point_info' structure of the next image for 73 * the security state specified. BL33 corresponds to the non-secure image type 74 * while BL32 corresponds to the secure image type. A NULL pointer is returned 75 * if the image does not exist. 76 ******************************************************************************/ 77 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 78 { 79 entry_point_info_t *next_image_info; 80 81 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 82 83 /* None of the images on this platform can have 0x0 as the entrypoint */ 84 if (next_image_info->pc) 85 return next_image_info; 86 else 87 return NULL; 88 } 89 90 /******************************************************************************* 91 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 92 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 93 * are lost (potentially). This needs to be done before the MMU is initialized 94 * so that the memory layout can be used while creating page tables. 95 * BL2 has flushed this information to memory, so we are guaranteed to pick up 96 * good data. 97 ******************************************************************************/ 98 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 99 u_register_t arg2, u_register_t arg3) 100 { 101 struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0; 102 103 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); 104 105 VERBOSE("bl31_setup\n"); 106 107 assert(arg_from_bl2 != NULL); 108 assert(arg_from_bl2->h.type == PARAM_BL31); 109 assert(arg_from_bl2->h.version >= VERSION_1); 110 111 bl32_ep_info = *arg_from_bl2->bl32_ep_info; 112 bl33_ep_info = *arg_from_bl2->bl33_ep_info; 113 } 114 115 /******************************************************************************* 116 * Perform any BL3-1 platform setup code 117 ******************************************************************************/ 118 void bl31_platform_setup(void) 119 { 120 platform_setup_cpu(); 121 platform_setup_sram(); 122 123 generic_delay_timer_init(); 124 125 /* Initialize the gic cpu and distributor interfaces */ 126 plat_arm_gic_driver_init(); 127 plat_arm_gic_init(); 128 129 /* Initialize spm at boot time */ 130 spm_boot_init(); 131 } 132 133 /******************************************************************************* 134 * Perform the very early platform specific architectural setup here. At the 135 * moment this is only intializes the mmu in a quick and dirty way. 136 ******************************************************************************/ 137 void bl31_plat_arch_setup(void) 138 { 139 plat_cci_init(); 140 plat_cci_enable(); 141 142 plat_configure_mmu_el3(BL_CODE_BASE, 143 BL_COHERENT_RAM_END - BL_CODE_BASE, 144 BL_CODE_BASE, 145 BL_CODE_END, 146 BL_COHERENT_RAM_BASE, 147 BL_COHERENT_RAM_END); 148 } 149 150