1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <arm_gic.h> 31 #include <assert.h> 32 #include <bl_common.h> 33 #include <console.h> 34 #include <debug.h> 35 #include <mcucfg.h> 36 #include <mmio.h> 37 #include <mtcmos.h> 38 #include <plat_private.h> 39 #include <platform.h> 40 #include <spm.h> 41 42 /******************************************************************************* 43 * Declarations of linker defined symbols which will help us find the layout 44 * of trusted SRAM 45 ******************************************************************************/ 46 unsigned long __RO_START__; 47 unsigned long __RO_END__; 48 49 unsigned long __COHERENT_RAM_START__; 50 unsigned long __COHERENT_RAM_END__; 51 52 /* 53 * The next 3 constants identify the extents of the code, RO data region and the 54 * limit of the BL31 image. These addresses are used by the MMU setup code and 55 * therefore they must be page-aligned. It is the responsibility of the linker 56 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 57 * refer to page-aligned addresses. 58 */ 59 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 60 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 61 #define BL31_END (unsigned long)(&__BL31_END__) 62 63 /* 64 * The next 2 constants identify the extents of the coherent memory region. 65 * These addresses are used by the MMU setup code and therefore they must be 66 * page-aligned. It is the responsibility of the linker script to ensure that 67 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 68 * refer to page-aligned addresses. 69 */ 70 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 71 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 72 73 static entry_point_info_t bl32_ep_info; 74 static entry_point_info_t bl33_ep_info; 75 76 static void platform_setup_cpu(void) 77 { 78 /* turn off all the little core's power except cpu 0 */ 79 mtcmos_little_cpu_off(); 80 81 /* setup big cores */ 82 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, 83 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | 84 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | 85 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | 86 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | 87 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); 88 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); 89 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, 90 MP1_SW_CG_GEN); 91 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, 92 MP1_L2RSTDISABLE); 93 94 /* set big cores arm64 boot mode */ 95 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, 96 MP1_CPUCFG_64BIT); 97 98 /* set LITTLE cores arm64 boot mode */ 99 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, 100 MP0_CPUCFG_64BIT); 101 102 /* enable dcm control */ 103 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, 104 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN | 105 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN | 106 INFRACLK_PSYS_DYNAMIC_CG_EN); 107 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, 108 L2C_SRAM_DCM_EN); 109 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, 110 MCU_BUS_DCM_EN); 111 } 112 113 static void platform_setup_sram(void) 114 { 115 /* protect BL31 memory from non-secure read/write access */ 116 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); 117 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); 118 } 119 120 /******************************************************************************* 121 * Return a pointer to the 'entry_point_info' structure of the next image for 122 * the security state specified. BL33 corresponds to the non-secure image type 123 * while BL32 corresponds to the secure image type. A NULL pointer is returned 124 * if the image does not exist. 125 ******************************************************************************/ 126 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 127 { 128 entry_point_info_t *next_image_info; 129 130 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 131 132 /* None of the images on this platform can have 0x0 as the entrypoint */ 133 if (next_image_info->pc) 134 return next_image_info; 135 else 136 return NULL; 137 } 138 139 /******************************************************************************* 140 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 141 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 142 * are lost (potentially). This needs to be done before the MMU is initialized 143 * so that the memory layout can be used while creating page tables. 144 * BL2 has flushed this information to memory, so we are guaranteed to pick up 145 * good data. 146 ******************************************************************************/ 147 void bl31_early_platform_setup(bl31_params_t *from_bl2, 148 void *plat_params_from_bl2) 149 { 150 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); 151 152 VERBOSE("bl31_setup\n"); 153 154 assert(from_bl2 != NULL); 155 assert(from_bl2->h.type == PARAM_BL31); 156 assert(from_bl2->h.version >= VERSION_1); 157 158 bl32_ep_info = *from_bl2->bl32_ep_info; 159 bl33_ep_info = *from_bl2->bl33_ep_info; 160 } 161 162 /******************************************************************************* 163 * Perform any BL3-1 platform setup code 164 ******************************************************************************/ 165 void bl31_platform_setup(void) 166 { 167 platform_setup_cpu(); 168 platform_setup_sram(); 169 170 plat_delay_timer_init(); 171 172 /* Initialize the gic cpu and distributor interfaces */ 173 plat_mt_gic_init(); 174 arm_gic_setup(); 175 176 /* Topologies are best known to the platform. */ 177 mt_setup_topology(); 178 179 /* Initialize spm at boot time */ 180 spm_boot_init(); 181 } 182 183 /******************************************************************************* 184 * Perform the very early platform specific architectural setup here. At the 185 * moment this is only intializes the mmu in a quick and dirty way. 186 ******************************************************************************/ 187 void bl31_plat_arch_setup(void) 188 { 189 plat_cci_init(); 190 plat_cci_enable(); 191 192 plat_configure_mmu_el3(BL31_RO_BASE, 193 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), 194 BL31_RO_BASE, 195 BL31_RO_LIMIT, 196 BL31_COHERENT_RAM_BASE, 197 BL31_COHERENT_RAM_LIMIT); 198 } 199 200