1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <arm_gic.h> 31 #include <assert.h> 32 #include <bl_common.h> 33 #include <console.h> 34 #include <debug.h> 35 #include <mcucfg.h> 36 #include <mmio.h> 37 #include <mtcmos.h> 38 #include <plat_private.h> 39 #include <platform.h> 40 #include <spm.h> 41 42 /******************************************************************************* 43 * Declarations of linker defined symbols which will help us find the layout 44 * of trusted SRAM 45 ******************************************************************************/ 46 unsigned long __RO_START__; 47 unsigned long __RO_END__; 48 49 unsigned long __COHERENT_RAM_START__; 50 unsigned long __COHERENT_RAM_END__; 51 52 /* 53 * The next 2 constants identify the extents of the code & RO data region. 54 * These addresses are used by the MMU setup code and therefore they must be 55 * page-aligned. It is the responsibility of the linker script to ensure that 56 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 57 */ 58 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 59 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 60 61 /* 62 * The next 2 constants identify the extents of the coherent memory region. 63 * These addresses are used by the MMU setup code and therefore they must be 64 * page-aligned. It is the responsibility of the linker script to ensure that 65 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 66 * refer to page-aligned addresses. 67 */ 68 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 69 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 70 71 static entry_point_info_t bl32_ep_info; 72 static entry_point_info_t bl33_ep_info; 73 74 static void platform_setup_cpu(void) 75 { 76 /* turn off all the little core's power except cpu 0 */ 77 mtcmos_little_cpu_off(); 78 79 /* setup big cores */ 80 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, 81 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | 82 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | 83 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | 84 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | 85 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); 86 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); 87 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, 88 MP1_SW_CG_GEN); 89 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, 90 MP1_L2RSTDISABLE); 91 92 /* set big cores arm64 boot mode */ 93 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, 94 MP1_CPUCFG_64BIT); 95 96 /* set LITTLE cores arm64 boot mode */ 97 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, 98 MP0_CPUCFG_64BIT); 99 } 100 101 /******************************************************************************* 102 * Return a pointer to the 'entry_point_info' structure of the next image for 103 * the security state specified. BL33 corresponds to the non-secure image type 104 * while BL32 corresponds to the secure image type. A NULL pointer is returned 105 * if the image does not exist. 106 ******************************************************************************/ 107 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 108 { 109 entry_point_info_t *next_image_info; 110 111 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 112 113 /* None of the images on this platform can have 0x0 as the entrypoint */ 114 if (next_image_info->pc) 115 return next_image_info; 116 else 117 return NULL; 118 } 119 120 /******************************************************************************* 121 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 122 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 123 * are lost (potentially). This needs to be done before the MMU is initialized 124 * so that the memory layout can be used while creating page tables. 125 * BL2 has flushed this information to memory, so we are guaranteed to pick up 126 * good data. 127 ******************************************************************************/ 128 void bl31_early_platform_setup(bl31_params_t *from_bl2, 129 void *plat_params_from_bl2) 130 { 131 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); 132 133 VERBOSE("bl31_setup\n"); 134 135 assert(from_bl2 != NULL); 136 assert(from_bl2->h.type == PARAM_BL31); 137 assert(from_bl2->h.version >= VERSION_1); 138 139 assert(((unsigned long)plat_params_from_bl2) == MT_BL31_PLAT_PARAM_VAL); 140 141 bl32_ep_info = *from_bl2->bl32_ep_info; 142 bl33_ep_info = *from_bl2->bl33_ep_info; 143 } 144 145 /******************************************************************************* 146 * Perform any BL3-1 platform setup code 147 ******************************************************************************/ 148 void bl31_platform_setup(void) 149 { 150 platform_setup_cpu(); 151 152 plat_delay_timer_init(); 153 154 /* Initialize the gic cpu and distributor interfaces */ 155 plat_mt_gic_init(); 156 arm_gic_setup(); 157 158 /* Topologies are best known to the platform. */ 159 mt_setup_topology(); 160 161 /* Initialize spm at boot time */ 162 spm_boot_init(); 163 } 164 165 /******************************************************************************* 166 * Perform the very early platform specific architectural setup here. At the 167 * moment this is only intializes the mmu in a quick and dirty way. 168 ******************************************************************************/ 169 void bl31_plat_arch_setup(void) 170 { 171 plat_cci_init(); 172 plat_cci_enable(); 173 174 plat_configure_mmu_el3(BL31_RO_BASE, 175 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), 176 BL31_RO_BASE, 177 BL31_RO_LIMIT, 178 BL31_COHERENT_RAM_BASE, 179 BL31_COHERENT_RAM_LIMIT); 180 } 181 182