1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <arm_gic.h> 31 #include <assert.h> 32 #include <bl_common.h> 33 #include <console.h> 34 #include <debug.h> 35 #include <generic_delay_timer.h> 36 #include <mcucfg.h> 37 #include <mmio.h> 38 #include <mtcmos.h> 39 #include <plat_private.h> 40 #include <platform.h> 41 #include <spm.h> 42 43 /******************************************************************************* 44 * Declarations of linker defined symbols which will help us find the layout 45 * of trusted SRAM 46 ******************************************************************************/ 47 unsigned long __RO_START__; 48 unsigned long __RO_END__; 49 50 unsigned long __COHERENT_RAM_START__; 51 unsigned long __COHERENT_RAM_END__; 52 53 /* 54 * The next 3 constants identify the extents of the code, RO data region and the 55 * limit of the BL31 image. These addresses are used by the MMU setup code and 56 * therefore they must be page-aligned. It is the responsibility of the linker 57 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 58 * refer to page-aligned addresses. 59 */ 60 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 61 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 62 #define BL31_END (unsigned long)(&__BL31_END__) 63 64 /* 65 * The next 2 constants identify the extents of the coherent memory region. 66 * These addresses are used by the MMU setup code and therefore they must be 67 * page-aligned. It is the responsibility of the linker script to ensure that 68 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 69 * refer to page-aligned addresses. 70 */ 71 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 72 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 73 74 static entry_point_info_t bl32_ep_info; 75 static entry_point_info_t bl33_ep_info; 76 77 static void platform_setup_cpu(void) 78 { 79 /* turn off all the little core's power except cpu 0 */ 80 mtcmos_little_cpu_off(); 81 82 /* setup big cores */ 83 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, 84 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | 85 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | 86 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | 87 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | 88 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); 89 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); 90 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, 91 MP1_SW_CG_GEN); 92 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, 93 MP1_L2RSTDISABLE); 94 95 /* set big cores arm64 boot mode */ 96 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, 97 MP1_CPUCFG_64BIT); 98 99 /* set LITTLE cores arm64 boot mode */ 100 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, 101 MP0_CPUCFG_64BIT); 102 103 /* enable dcm control */ 104 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, 105 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN | 106 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN | 107 INFRACLK_PSYS_DYNAMIC_CG_EN); 108 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, 109 L2C_SRAM_DCM_EN); 110 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, 111 MCU_BUS_DCM_EN); 112 } 113 114 static void platform_setup_sram(void) 115 { 116 /* protect BL31 memory from non-secure read/write access */ 117 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); 118 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); 119 } 120 121 /******************************************************************************* 122 * Return a pointer to the 'entry_point_info' structure of the next image for 123 * the security state specified. BL33 corresponds to the non-secure image type 124 * while BL32 corresponds to the secure image type. A NULL pointer is returned 125 * if the image does not exist. 126 ******************************************************************************/ 127 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 128 { 129 entry_point_info_t *next_image_info; 130 131 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 132 133 /* None of the images on this platform can have 0x0 as the entrypoint */ 134 if (next_image_info->pc) 135 return next_image_info; 136 else 137 return NULL; 138 } 139 140 /******************************************************************************* 141 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 142 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 143 * are lost (potentially). This needs to be done before the MMU is initialized 144 * so that the memory layout can be used while creating page tables. 145 * BL2 has flushed this information to memory, so we are guaranteed to pick up 146 * good data. 147 ******************************************************************************/ 148 void bl31_early_platform_setup(bl31_params_t *from_bl2, 149 void *plat_params_from_bl2) 150 { 151 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); 152 153 VERBOSE("bl31_setup\n"); 154 155 assert(from_bl2 != NULL); 156 assert(from_bl2->h.type == PARAM_BL31); 157 assert(from_bl2->h.version >= VERSION_1); 158 159 bl32_ep_info = *from_bl2->bl32_ep_info; 160 bl33_ep_info = *from_bl2->bl33_ep_info; 161 } 162 163 /******************************************************************************* 164 * Perform any BL3-1 platform setup code 165 ******************************************************************************/ 166 void bl31_platform_setup(void) 167 { 168 platform_setup_cpu(); 169 platform_setup_sram(); 170 171 generic_delay_timer_init(); 172 173 /* Initialize the gic cpu and distributor interfaces */ 174 plat_mt_gic_init(); 175 arm_gic_setup(); 176 177 /* Topologies are best known to the platform. */ 178 mt_setup_topology(); 179 180 /* Initialize spm at boot time */ 181 spm_boot_init(); 182 } 183 184 /******************************************************************************* 185 * Perform the very early platform specific architectural setup here. At the 186 * moment this is only intializes the mmu in a quick and dirty way. 187 ******************************************************************************/ 188 void bl31_plat_arch_setup(void) 189 { 190 plat_cci_init(); 191 plat_cci_enable(); 192 193 plat_configure_mmu_el3(BL31_RO_BASE, 194 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), 195 BL31_RO_BASE, 196 BL31_RO_LIMIT, 197 BL31_COHERENT_RAM_BASE, 198 BL31_COHERENT_RAM_LIMIT); 199 } 200 201