1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <assert.h> 31 #include <bl_common.h> 32 #include <common_def.h> 33 #include <console.h> 34 #include <debug.h> 35 #include <generic_delay_timer.h> 36 #include <mcucfg.h> 37 #include <mmio.h> 38 #include <mtcmos.h> 39 #include <plat_arm.h> 40 #include <plat_private.h> 41 #include <platform.h> 42 #include <spm.h> 43 44 /******************************************************************************* 45 * Declarations of linker defined symbols which will help us find the layout 46 * of trusted SRAM 47 ******************************************************************************/ 48 unsigned long __RO_START__; 49 unsigned long __RO_END__; 50 51 /* 52 * The next 3 constants identify the extents of the code, RO data region and the 53 * limit of the BL31 image. These addresses are used by the MMU setup code and 54 * therefore they must be page-aligned. It is the responsibility of the linker 55 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 56 * refer to page-aligned addresses. 57 */ 58 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 59 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 60 #define BL31_END (unsigned long)(&__BL31_END__) 61 62 static entry_point_info_t bl32_ep_info; 63 static entry_point_info_t bl33_ep_info; 64 65 static void platform_setup_cpu(void) 66 { 67 /* turn off all the little core's power except cpu 0 */ 68 mtcmos_little_cpu_off(); 69 70 /* setup big cores */ 71 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, 72 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | 73 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | 74 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | 75 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | 76 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); 77 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); 78 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, 79 MP1_SW_CG_GEN); 80 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, 81 MP1_L2RSTDISABLE); 82 83 /* set big cores arm64 boot mode */ 84 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, 85 MP1_CPUCFG_64BIT); 86 87 /* set LITTLE cores arm64 boot mode */ 88 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, 89 MP0_CPUCFG_64BIT); 90 91 /* enable dcm control */ 92 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, 93 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN | 94 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN | 95 INFRACLK_PSYS_DYNAMIC_CG_EN); 96 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, 97 L2C_SRAM_DCM_EN); 98 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, 99 MCU_BUS_DCM_EN); 100 } 101 102 static void platform_setup_sram(void) 103 { 104 /* protect BL31 memory from non-secure read/write access */ 105 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); 106 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); 107 } 108 109 /******************************************************************************* 110 * Return a pointer to the 'entry_point_info' structure of the next image for 111 * the security state specified. BL33 corresponds to the non-secure image type 112 * while BL32 corresponds to the secure image type. A NULL pointer is returned 113 * if the image does not exist. 114 ******************************************************************************/ 115 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 116 { 117 entry_point_info_t *next_image_info; 118 119 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 120 121 /* None of the images on this platform can have 0x0 as the entrypoint */ 122 if (next_image_info->pc) 123 return next_image_info; 124 else 125 return NULL; 126 } 127 128 /******************************************************************************* 129 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 130 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 131 * are lost (potentially). This needs to be done before the MMU is initialized 132 * so that the memory layout can be used while creating page tables. 133 * BL2 has flushed this information to memory, so we are guaranteed to pick up 134 * good data. 135 ******************************************************************************/ 136 void bl31_early_platform_setup(bl31_params_t *from_bl2, 137 void *plat_params_from_bl2) 138 { 139 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); 140 141 VERBOSE("bl31_setup\n"); 142 143 assert(from_bl2 != NULL); 144 assert(from_bl2->h.type == PARAM_BL31); 145 assert(from_bl2->h.version >= VERSION_1); 146 147 bl32_ep_info = *from_bl2->bl32_ep_info; 148 bl33_ep_info = *from_bl2->bl33_ep_info; 149 } 150 151 /******************************************************************************* 152 * Perform any BL3-1 platform setup code 153 ******************************************************************************/ 154 void bl31_platform_setup(void) 155 { 156 platform_setup_cpu(); 157 platform_setup_sram(); 158 159 generic_delay_timer_init(); 160 161 /* Initialize the gic cpu and distributor interfaces */ 162 plat_arm_gic_driver_init(); 163 plat_arm_gic_init(); 164 165 #if ENABLE_PLAT_COMPAT 166 /* Topologies are best known to the platform. */ 167 mt_setup_topology(); 168 #endif 169 170 /* Initialize spm at boot time */ 171 spm_boot_init(); 172 } 173 174 /******************************************************************************* 175 * Perform the very early platform specific architectural setup here. At the 176 * moment this is only intializes the mmu in a quick and dirty way. 177 ******************************************************************************/ 178 void bl31_plat_arch_setup(void) 179 { 180 plat_cci_init(); 181 plat_cci_enable(); 182 183 plat_configure_mmu_el3(BL31_RO_BASE, 184 BL_COHERENT_RAM_END - BL31_RO_BASE, 185 BL31_RO_BASE, 186 BL31_RO_LIMIT, 187 BL_COHERENT_RAM_BASE, 188 BL_COHERENT_RAM_END); 189 } 190 191