xref: /rk3399_ARM-atf/plat/mediatek/mt8173/aarch64/platform_common.c (revision fd6007de64fd7e16f6d96972643434c04a77f1c6)
1 /*
2  * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * Redistributions of source code must retain the above copyright notice, this
8  * list of conditions and the following disclaimer.
9  *
10  * Redistributions in binary form must reproduce the above copyright notice,
11  * this list of conditions and the following disclaimer in the documentation
12  * and/or other materials provided with the distribution.
13  *
14  * Neither the name of ARM nor the names of its contributors may be used
15  * to endorse or promote products derived from this software without specific
16  * prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 #include <arch_helpers.h>
31 #include <arm_gic.h>
32 #include <bl_common.h>
33 #include <cci.h>
34 #include <debug.h>
35 #include <mt8173_def.h>
36 #include <platform_def.h>
37 #include <xlat_tables.h>
38 
39 static const int cci_map[] = {
40 	PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX,
41 	PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX
42 };
43 
44 /* Table of regions to map using the MMU.  */
45 const mmap_region_t plat_mmap[] = {
46 	/* for TF text, RO, RW */
47 	MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE + TZRAM2_SIZE,
48 			MT_MEMORY | MT_RW | MT_SECURE),
49 	MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
50 			MT_DEVICE | MT_RW | MT_SECURE),
51 	MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
52 			MT_DEVICE | MT_RW | MT_SECURE),
53 	{ 0 }
54 
55 };
56 
57 /*******************************************************************************
58  * Macro generating the code for the function setting up the pagetables as per
59  * the platform memory map & initialize the mmu, for the given exception level
60  ******************************************************************************/
61 #define DEFINE_CONFIGURE_MMU_EL(_el)					\
62 	void plat_configure_mmu_el ## _el(unsigned long total_base,	\
63 					  unsigned long total_size,	\
64 					  unsigned long ro_start,	\
65 					  unsigned long ro_limit,	\
66 					  unsigned long coh_start,	\
67 					  unsigned long coh_limit)	\
68 	{								\
69 		mmap_add_region(total_base, total_base,			\
70 				total_size,				\
71 				MT_MEMORY | MT_RW | MT_SECURE);		\
72 		mmap_add_region(ro_start, ro_start,			\
73 				ro_limit - ro_start,			\
74 				MT_MEMORY | MT_RO | MT_SECURE);		\
75 		mmap_add_region(coh_start, coh_start,			\
76 				coh_limit - coh_start,			\
77 				MT_DEVICE | MT_RW | MT_SECURE);		\
78 		mmap_add(plat_mmap);					\
79 		init_xlat_tables();					\
80 									\
81 		enable_mmu_el ## _el(0);				\
82 	}
83 
84 /* Define EL3 variants of the function initialising the MMU */
85 DEFINE_CONFIGURE_MMU_EL(3)
86 
87 uint64_t plat_get_syscnt_freq(void)
88 {
89 	return SYS_COUNTER_FREQ_IN_TICKS;
90 }
91 
92 void plat_cci_init(void)
93 {
94 	/* Initialize CCI driver */
95 	cci_init(PLAT_MT_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
96 }
97 
98 void plat_cci_enable(void)
99 {
100 	/*
101 	 * Enable CCI coherency for this cluster.
102 	 * No need for locks as no other cpu is active at the moment.
103 	 */
104 	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
105 }
106 
107 void plat_cci_disable(void)
108 {
109 	cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
110 }
111