1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <drivers/arm/cci.h> 13 #include <lib/utils.h> 14 #include <lib/xlat_tables/xlat_tables.h> 15 16 #include <mt8173_def.h> 17 18 static const int cci_map[] = { 19 PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX, 20 PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 21 }; 22 23 /* Table of regions to map using the MMU. */ 24 const mmap_region_t plat_mmap[] = { 25 /* for TF text, RO, RW */ 26 MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE, 27 MT_MEMORY | MT_RW | MT_SECURE), 28 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, 29 MT_DEVICE | MT_RW | MT_SECURE), 30 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, 31 MT_DEVICE | MT_RW | MT_SECURE), 32 { 0 } 33 34 }; 35 36 /******************************************************************************* 37 * Macro generating the code for the function setting up the pagetables as per 38 * the platform memory map & initialize the mmu, for the given exception level 39 ******************************************************************************/ 40 #define DEFINE_CONFIGURE_MMU_EL(_el) \ 41 void plat_configure_mmu_el ## _el(unsigned long total_base, \ 42 unsigned long total_size, \ 43 unsigned long ro_start, \ 44 unsigned long ro_limit, \ 45 unsigned long coh_start, \ 46 unsigned long coh_limit) \ 47 { \ 48 mmap_add_region(total_base, total_base, \ 49 total_size, \ 50 MT_MEMORY | MT_RW | MT_SECURE); \ 51 mmap_add_region(ro_start, ro_start, \ 52 ro_limit - ro_start, \ 53 MT_MEMORY | MT_RO | MT_SECURE); \ 54 mmap_add_region(coh_start, coh_start, \ 55 coh_limit - coh_start, \ 56 MT_DEVICE | MT_RW | MT_SECURE); \ 57 mmap_add(plat_mmap); \ 58 init_xlat_tables(); \ 59 \ 60 enable_mmu_el ## _el(0); \ 61 } 62 63 /* Define EL3 variants of the function initialising the MMU */ 64 DEFINE_CONFIGURE_MMU_EL(3) 65 66 unsigned int plat_get_syscnt_freq2(void) 67 { 68 return SYS_COUNTER_FREQ_IN_TICKS; 69 } 70 71 void plat_cci_init(void) 72 { 73 /* Initialize CCI driver */ 74 cci_init(PLAT_MT_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 75 } 76 77 void plat_cci_enable(void) 78 { 79 /* 80 * Enable CCI coherency for this cluster. 81 * No need for locks as no other cpu is active at the moment. 82 */ 83 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 84 } 85 86 void plat_cci_disable(void) 87 { 88 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 89 } 90