17d116dccSCC Ma/* 27d116dccSCC Ma * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 37d116dccSCC Ma * 47d116dccSCC Ma * Redistribution and use in source and binary forms, with or without 57d116dccSCC Ma * modification, are permitted provided that the following conditions are met: 67d116dccSCC Ma * 77d116dccSCC Ma * Redistributions of source code must retain the above copyright notice, this 87d116dccSCC Ma * list of conditions and the following disclaimer. 97d116dccSCC Ma * 107d116dccSCC Ma * Redistributions in binary form must reproduce the above copyright notice, 117d116dccSCC Ma * this list of conditions and the following disclaimer in the documentation 127d116dccSCC Ma * and/or other materials provided with the distribution. 137d116dccSCC Ma * 147d116dccSCC Ma * Neither the name of ARM nor the names of its contributors may be used 157d116dccSCC Ma * to endorse or promote products derived from this software without specific 167d116dccSCC Ma * prior written permission. 177d116dccSCC Ma * 187d116dccSCC Ma * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 197d116dccSCC Ma * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 207d116dccSCC Ma * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 217d116dccSCC Ma * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 227d116dccSCC Ma * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 237d116dccSCC Ma * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 247d116dccSCC Ma * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 257d116dccSCC Ma * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 267d116dccSCC Ma * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 277d116dccSCC Ma * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 287d116dccSCC Ma * POSSIBILITY OF SUCH DAMAGE. 297d116dccSCC Ma */ 307d116dccSCC Ma#include <arch.h> 317d116dccSCC Ma#include <asm_macros.S> 327d116dccSCC Ma#include <mt8173_def.h> 337d116dccSCC Ma 347d116dccSCC Ma .globl plat_secondary_cold_boot_setup 357d116dccSCC Ma .globl plat_report_exception 367d116dccSCC Ma .globl platform_is_primary_cpu 37*3fc26aa0SKoan-Sin Tan .globl plat_my_core_pos 387d116dccSCC Ma .globl plat_crash_console_init 397d116dccSCC Ma .globl plat_crash_console_putc 407d116dccSCC Ma 417d116dccSCC Ma /* ----------------------------------------------------- 427d116dccSCC Ma * void plat_secondary_cold_boot_setup (void); 437d116dccSCC Ma * 447d116dccSCC Ma * This function performs any platform specific actions 457d116dccSCC Ma * needed for a secondary cpu after a cold reset e.g 467d116dccSCC Ma * mark the cpu's presence, mechanism to place it in a 477d116dccSCC Ma * holding pen etc. 487d116dccSCC Ma * ----------------------------------------------------- 497d116dccSCC Ma */ 507d116dccSCC Mafunc plat_secondary_cold_boot_setup 517d116dccSCC Ma /* MT8173 Oak does not do cold boot for secondary CPU */ 527d116dccSCC Macb_panic: 537d116dccSCC Ma b cb_panic 547d116dccSCC Maendfunc plat_secondary_cold_boot_setup 557d116dccSCC Ma 567d116dccSCC Mafunc platform_is_primary_cpu 577d116dccSCC Ma and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 587d116dccSCC Ma cmp x0, #MT8173_PRIMARY_CPU 597d116dccSCC Ma cset x0, eq 607d116dccSCC Ma ret 617d116dccSCC Maendfunc platform_is_primary_cpu 627d116dccSCC Ma 63*3fc26aa0SKoan-Sin Tan#if !ENABLE_PLAT_COMPAT 64*3fc26aa0SKoan-Sin Tan /* ----------------------------------------------------- 65*3fc26aa0SKoan-Sin Tan * unsigned int plat_my_core_pos(void); 66*3fc26aa0SKoan-Sin Tan * 67*3fc26aa0SKoan-Sin Tan * result: CorePos = CoreId + (ClusterId << 2) 68*3fc26aa0SKoan-Sin Tan * ----------------------------------------------------- 69*3fc26aa0SKoan-Sin Tan */ 70*3fc26aa0SKoan-Sin Tanfunc plat_my_core_pos 71*3fc26aa0SKoan-Sin Tan mrs x0, mpidr_el1 72*3fc26aa0SKoan-Sin Tan and x1, x0, #MPIDR_CPU_MASK 73*3fc26aa0SKoan-Sin Tan and x0, x0, #MPIDR_CLUSTER_MASK 74*3fc26aa0SKoan-Sin Tan add x0, x1, x0, LSR #6 75*3fc26aa0SKoan-Sin Tan ret 76*3fc26aa0SKoan-Sin Tanendfunc plat_my_core_pos 77*3fc26aa0SKoan-Sin Tan#endif 78*3fc26aa0SKoan-Sin Tan 797d116dccSCC Ma /* --------------------------------------------- 807d116dccSCC Ma * int plat_crash_console_init(void) 817d116dccSCC Ma * Function to initialize the crash console 827d116dccSCC Ma * without a C Runtime to print crash report. 839400b40eSJuan Castillo * Clobber list : x0 - x4 847d116dccSCC Ma * --------------------------------------------- 857d116dccSCC Ma */ 867d116dccSCC Mafunc plat_crash_console_init 877d116dccSCC Ma mov_imm x0, MT8173_UART0_BASE 887d116dccSCC Ma mov_imm x1, MT8173_UART_CLOCK 897d116dccSCC Ma mov_imm x2, MT8173_BAUDRATE 907d116dccSCC Ma b console_core_init 917d116dccSCC Maendfunc plat_crash_console_init 927d116dccSCC Ma 937d116dccSCC Ma /* --------------------------------------------- 947d116dccSCC Ma * int plat_crash_console_putc(void) 957d116dccSCC Ma * Function to print a character on the crash 967d116dccSCC Ma * console without a C Runtime. 977d116dccSCC Ma * Clobber list : x1, x2 987d116dccSCC Ma * --------------------------------------------- 997d116dccSCC Ma */ 1007d116dccSCC Mafunc plat_crash_console_putc 1017d116dccSCC Ma mov_imm x1, MT8173_UART0_BASE 1027d116dccSCC Ma b console_core_putc 1037d116dccSCC Maendfunc plat_crash_console_putc 104