17d116dccSCC Ma/* 2*2cc97771SAmbroise Vincent * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 37d116dccSCC Ma * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 57d116dccSCC Ma */ 67d116dccSCC Ma#include <arch.h> 77d116dccSCC Ma#include <asm_macros.S> 87d116dccSCC Ma#include <mt8173_def.h> 97d116dccSCC Ma 107d116dccSCC Ma .globl plat_secondary_cold_boot_setup 117d116dccSCC Ma .globl plat_report_exception 127d116dccSCC Ma .globl platform_is_primary_cpu 133fc26aa0SKoan-Sin Tan .globl plat_my_core_pos 147d116dccSCC Ma 157d116dccSCC Ma /* ----------------------------------------------------- 167d116dccSCC Ma * void plat_secondary_cold_boot_setup (void); 177d116dccSCC Ma * 187d116dccSCC Ma * This function performs any platform specific actions 197d116dccSCC Ma * needed for a secondary cpu after a cold reset e.g 207d116dccSCC Ma * mark the cpu's presence, mechanism to place it in a 217d116dccSCC Ma * holding pen etc. 227d116dccSCC Ma * ----------------------------------------------------- 237d116dccSCC Ma */ 247d116dccSCC Mafunc plat_secondary_cold_boot_setup 257d116dccSCC Ma /* MT8173 Oak does not do cold boot for secondary CPU */ 267d116dccSCC Macb_panic: 277d116dccSCC Ma b cb_panic 287d116dccSCC Maendfunc plat_secondary_cold_boot_setup 297d116dccSCC Ma 307d116dccSCC Mafunc platform_is_primary_cpu 317d116dccSCC Ma and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 327d116dccSCC Ma cmp x0, #MT8173_PRIMARY_CPU 337d116dccSCC Ma cset x0, eq 347d116dccSCC Ma ret 357d116dccSCC Maendfunc platform_is_primary_cpu 367d116dccSCC Ma 373fc26aa0SKoan-Sin Tan /* ----------------------------------------------------- 383fc26aa0SKoan-Sin Tan * unsigned int plat_my_core_pos(void); 393fc26aa0SKoan-Sin Tan * 403fc26aa0SKoan-Sin Tan * result: CorePos = CoreId + (ClusterId << 2) 413fc26aa0SKoan-Sin Tan * ----------------------------------------------------- 423fc26aa0SKoan-Sin Tan */ 433fc26aa0SKoan-Sin Tanfunc plat_my_core_pos 443fc26aa0SKoan-Sin Tan mrs x0, mpidr_el1 453fc26aa0SKoan-Sin Tan and x1, x0, #MPIDR_CPU_MASK 463fc26aa0SKoan-Sin Tan and x0, x0, #MPIDR_CLUSTER_MASK 473fc26aa0SKoan-Sin Tan add x0, x1, x0, LSR #6 483fc26aa0SKoan-Sin Tan ret 493fc26aa0SKoan-Sin Tanendfunc plat_my_core_pos 50