1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT6363_LOWPOWER_REG_H 8 #define MT6363_LOWPOWER_REG_H 9 10 #define MT6363_RG_BUCK_VS2_VOSEL_SLEEP_ADDR 0x1487 11 #define MT6363_RG_BUCK_VS2_ONLV_EN_ADDR 0x1488 12 #define MT6363_RG_BUCK_VS2_ONLV_EN_SHIFT 4 13 #define MT6363_RG_BUCK_VS2_RC0_OP_EN_ADDR 0x148D 14 #define MT6363_RG_BUCK_VS2_RC1_OP_EN_ADDR 0x148D 15 #define MT6363_RG_BUCK_VS2_RC2_OP_EN_ADDR 0x148D 16 #define MT6363_RG_BUCK_VS2_RC3_OP_EN_ADDR 0x148D 17 #define MT6363_RG_BUCK_VS2_RC4_OP_EN_ADDR 0x148D 18 #define MT6363_RG_BUCK_VS2_RC5_OP_EN_ADDR 0x148D 19 #define MT6363_RG_BUCK_VS2_RC6_OP_EN_ADDR 0x148D 20 #define MT6363_RG_BUCK_VS2_RC7_OP_EN_ADDR 0x148D 21 #define MT6363_RG_BUCK_VS2_RC8_OP_EN_ADDR 0x148E 22 #define MT6363_RG_BUCK_VS2_RC9_OP_EN_ADDR 0x148E 23 #define MT6363_RG_BUCK_VS2_RC10_OP_EN_ADDR 0x148E 24 #define MT6363_RG_BUCK_VS2_RC11_OP_EN_ADDR 0x148E 25 #define MT6363_RG_BUCK_VS2_RC12_OP_EN_ADDR 0x148E 26 #define MT6363_RG_BUCK_VS2_RC13_OP_EN_ADDR 0x148E 27 #define MT6363_RG_BUCK_VS2_HW0_OP_EN_ADDR 0x148F 28 #define MT6363_RG_BUCK_VS2_HW1_OP_EN_ADDR 0x148F 29 #define MT6363_RG_BUCK_VS2_HW2_OP_EN_ADDR 0x148F 30 #define MT6363_RG_BUCK_VS2_HW3_OP_EN_ADDR 0x148F 31 #define MT6363_RG_BUCK_VS2_HW4_OP_EN_ADDR 0x148F 32 #define MT6363_RG_BUCK_VS2_SW_OP_EN_ADDR 0x148F 33 #define MT6363_RG_BUCK_VS2_RC0_OP_CFG_ADDR 0x1490 34 #define MT6363_RG_BUCK_VS2_RC1_OP_CFG_ADDR 0x1490 35 #define MT6363_RG_BUCK_VS2_RC2_OP_CFG_ADDR 0x1490 36 #define MT6363_RG_BUCK_VS2_RC3_OP_CFG_ADDR 0x1490 37 #define MT6363_RG_BUCK_VS2_RC4_OP_CFG_ADDR 0x1490 38 #define MT6363_RG_BUCK_VS2_RC5_OP_CFG_ADDR 0x1490 39 #define MT6363_RG_BUCK_VS2_RC6_OP_CFG_ADDR 0x1490 40 #define MT6363_RG_BUCK_VS2_RC7_OP_CFG_ADDR 0x1490 41 #define MT6363_RG_BUCK_VS2_RC8_OP_CFG_ADDR 0x1491 42 #define MT6363_RG_BUCK_VS2_RC9_OP_CFG_ADDR 0x1491 43 #define MT6363_RG_BUCK_VS2_RC10_OP_CFG_ADDR 0x1491 44 #define MT6363_RG_BUCK_VS2_RC11_OP_CFG_ADDR 0x1491 45 #define MT6363_RG_BUCK_VS2_RC12_OP_CFG_ADDR 0x1491 46 #define MT6363_RG_BUCK_VS2_RC13_OP_CFG_ADDR 0x1491 47 #define MT6363_RG_BUCK_VS2_HW0_OP_CFG_ADDR 0x1492 48 #define MT6363_RG_BUCK_VS2_HW1_OP_CFG_ADDR 0x1492 49 #define MT6363_RG_BUCK_VS2_HW2_OP_CFG_ADDR 0x1492 50 #define MT6363_RG_BUCK_VS2_HW3_OP_CFG_ADDR 0x1492 51 #define MT6363_RG_BUCK_VS2_HW4_OP_CFG_ADDR 0x1492 52 #define MT6363_RG_BUCK_VS2_RC0_OP_MODE_ADDR 0x1493 53 #define MT6363_RG_BUCK_VS2_RC1_OP_MODE_ADDR 0x1493 54 #define MT6363_RG_BUCK_VS2_RC2_OP_MODE_ADDR 0x1493 55 #define MT6363_RG_BUCK_VS2_RC3_OP_MODE_ADDR 0x1493 56 #define MT6363_RG_BUCK_VS2_RC4_OP_MODE_ADDR 0x1493 57 #define MT6363_RG_BUCK_VS2_RC5_OP_MODE_ADDR 0x1493 58 #define MT6363_RG_BUCK_VS2_RC6_OP_MODE_ADDR 0x1493 59 #define MT6363_RG_BUCK_VS2_RC7_OP_MODE_ADDR 0x1493 60 #define MT6363_RG_BUCK_VS2_RC8_OP_MODE_ADDR 0x1494 61 #define MT6363_RG_BUCK_VS2_RC9_OP_MODE_ADDR 0x1494 62 #define MT6363_RG_BUCK_VS2_RC10_OP_MODE_ADDR 0x1494 63 #define MT6363_RG_BUCK_VS2_RC11_OP_MODE_ADDR 0x1494 64 #define MT6363_RG_BUCK_VS2_RC12_OP_MODE_ADDR 0x1494 65 #define MT6363_RG_BUCK_VS2_RC13_OP_MODE_ADDR 0x1494 66 #define MT6363_RG_BUCK_VS2_HW0_OP_MODE_ADDR 0x1495 67 #define MT6363_RG_BUCK_VS2_HW1_OP_MODE_ADDR 0x1495 68 #define MT6363_RG_BUCK_VS2_HW2_OP_MODE_ADDR 0x1495 69 #define MT6363_RG_BUCK_VS2_HW3_OP_MODE_ADDR 0x1495 70 #define MT6363_RG_BUCK_VS2_HW4_OP_MODE_ADDR 0x1495 71 #define MT6363_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR 0x1507 72 #define MT6363_RG_BUCK_VBUCK1_ONLV_EN_ADDR 0x1508 73 #define MT6363_RG_BUCK_VBUCK1_ONLV_EN_SHIFT 4 74 #define MT6363_RG_BUCK_VBUCK1_RC0_OP_EN_ADDR 0x150D 75 #define MT6363_RG_BUCK_VBUCK1_RC1_OP_EN_ADDR 0x150D 76 #define MT6363_RG_BUCK_VBUCK1_RC2_OP_EN_ADDR 0x150D 77 #define MT6363_RG_BUCK_VBUCK1_RC3_OP_EN_ADDR 0x150D 78 #define MT6363_RG_BUCK_VBUCK1_RC4_OP_EN_ADDR 0x150D 79 #define MT6363_RG_BUCK_VBUCK1_RC5_OP_EN_ADDR 0x150D 80 #define MT6363_RG_BUCK_VBUCK1_RC6_OP_EN_ADDR 0x150D 81 #define MT6363_RG_BUCK_VBUCK1_RC7_OP_EN_ADDR 0x150D 82 #define MT6363_RG_BUCK_VBUCK1_RC8_OP_EN_ADDR 0x150E 83 #define MT6363_RG_BUCK_VBUCK1_RC9_OP_EN_ADDR 0x150E 84 #define MT6363_RG_BUCK_VBUCK1_RC10_OP_EN_ADDR 0x150E 85 #define MT6363_RG_BUCK_VBUCK1_RC11_OP_EN_ADDR 0x150E 86 #define MT6363_RG_BUCK_VBUCK1_RC12_OP_EN_ADDR 0x150E 87 #define MT6363_RG_BUCK_VBUCK1_RC13_OP_EN_ADDR 0x150E 88 #define MT6363_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x150F 89 #define MT6363_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x150F 90 #define MT6363_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x150F 91 #define MT6363_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x150F 92 #define MT6363_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x150F 93 #define MT6363_RG_BUCK_VBUCK1_RC0_OP_CFG_ADDR 0x1510 94 #define MT6363_RG_BUCK_VBUCK1_RC1_OP_CFG_ADDR 0x1510 95 #define MT6363_RG_BUCK_VBUCK1_RC2_OP_CFG_ADDR 0x1510 96 #define MT6363_RG_BUCK_VBUCK1_RC3_OP_CFG_ADDR 0x1510 97 #define MT6363_RG_BUCK_VBUCK1_RC4_OP_CFG_ADDR 0x1510 98 #define MT6363_RG_BUCK_VBUCK1_RC5_OP_CFG_ADDR 0x1510 99 #define MT6363_RG_BUCK_VBUCK1_RC6_OP_CFG_ADDR 0x1510 100 #define MT6363_RG_BUCK_VBUCK1_RC7_OP_CFG_ADDR 0x1510 101 #define MT6363_RG_BUCK_VBUCK1_RC8_OP_CFG_ADDR 0x1511 102 #define MT6363_RG_BUCK_VBUCK1_RC9_OP_CFG_ADDR 0x1511 103 #define MT6363_RG_BUCK_VBUCK1_RC10_OP_CFG_ADDR 0x1511 104 #define MT6363_RG_BUCK_VBUCK1_RC11_OP_CFG_ADDR 0x1511 105 #define MT6363_RG_BUCK_VBUCK1_RC12_OP_CFG_ADDR 0x1511 106 #define MT6363_RG_BUCK_VBUCK1_RC13_OP_CFG_ADDR 0x1511 107 #define MT6363_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x1512 108 #define MT6363_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x1512 109 #define MT6363_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x1512 110 #define MT6363_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x1512 111 #define MT6363_RG_BUCK_VBUCK1_HW4_OP_CFG_ADDR 0x1512 112 #define MT6363_RG_BUCK_VBUCK1_RC0_OP_MODE_ADDR 0x1513 113 #define MT6363_RG_BUCK_VBUCK1_RC1_OP_MODE_ADDR 0x1513 114 #define MT6363_RG_BUCK_VBUCK1_RC2_OP_MODE_ADDR 0x1513 115 #define MT6363_RG_BUCK_VBUCK1_RC3_OP_MODE_ADDR 0x1513 116 #define MT6363_RG_BUCK_VBUCK1_RC4_OP_MODE_ADDR 0x1513 117 #define MT6363_RG_BUCK_VBUCK1_RC5_OP_MODE_ADDR 0x1513 118 #define MT6363_RG_BUCK_VBUCK1_RC6_OP_MODE_ADDR 0x1513 119 #define MT6363_RG_BUCK_VBUCK1_RC7_OP_MODE_ADDR 0x1513 120 #define MT6363_RG_BUCK_VBUCK1_RC8_OP_MODE_ADDR 0x1514 121 #define MT6363_RG_BUCK_VBUCK1_RC9_OP_MODE_ADDR 0x1514 122 #define MT6363_RG_BUCK_VBUCK1_RC10_OP_MODE_ADDR 0x1514 123 #define MT6363_RG_BUCK_VBUCK1_RC11_OP_MODE_ADDR 0x1514 124 #define MT6363_RG_BUCK_VBUCK1_RC12_OP_MODE_ADDR 0x1514 125 #define MT6363_RG_BUCK_VBUCK1_RC13_OP_MODE_ADDR 0x1514 126 #define MT6363_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x1515 127 #define MT6363_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x1515 128 #define MT6363_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x1515 129 #define MT6363_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x1515 130 #define MT6363_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR 0x1587 131 #define MT6363_RG_BUCK_VBUCK2_ONLV_EN_ADDR 0x1588 132 #define MT6363_RG_BUCK_VBUCK2_ONLV_EN_SHIFT 4 133 #define MT6363_RG_BUCK_VBUCK2_RC0_OP_EN_ADDR 0x158D 134 #define MT6363_RG_BUCK_VBUCK2_RC1_OP_EN_ADDR 0x158D 135 #define MT6363_RG_BUCK_VBUCK2_RC2_OP_EN_ADDR 0x158D 136 #define MT6363_RG_BUCK_VBUCK2_RC3_OP_EN_ADDR 0x158D 137 #define MT6363_RG_BUCK_VBUCK2_RC4_OP_EN_ADDR 0x158D 138 #define MT6363_RG_BUCK_VBUCK2_RC5_OP_EN_ADDR 0x158D 139 #define MT6363_RG_BUCK_VBUCK2_RC6_OP_EN_ADDR 0x158D 140 #define MT6363_RG_BUCK_VBUCK2_RC7_OP_EN_ADDR 0x158D 141 #define MT6363_RG_BUCK_VBUCK2_RC8_OP_EN_ADDR 0x158E 142 #define MT6363_RG_BUCK_VBUCK2_RC9_OP_EN_ADDR 0x158E 143 #define MT6363_RG_BUCK_VBUCK2_RC10_OP_EN_ADDR 0x158E 144 #define MT6363_RG_BUCK_VBUCK2_RC11_OP_EN_ADDR 0x158E 145 #define MT6363_RG_BUCK_VBUCK2_RC12_OP_EN_ADDR 0x158E 146 #define MT6363_RG_BUCK_VBUCK2_RC13_OP_EN_ADDR 0x158E 147 #define MT6363_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x158F 148 #define MT6363_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x158F 149 #define MT6363_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x158F 150 #define MT6363_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x158F 151 #define MT6363_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x158F 152 #define MT6363_RG_BUCK_VBUCK2_RC0_OP_CFG_ADDR 0x1590 153 #define MT6363_RG_BUCK_VBUCK2_RC1_OP_CFG_ADDR 0x1590 154 #define MT6363_RG_BUCK_VBUCK2_RC2_OP_CFG_ADDR 0x1590 155 #define MT6363_RG_BUCK_VBUCK2_RC3_OP_CFG_ADDR 0x1590 156 #define MT6363_RG_BUCK_VBUCK2_RC4_OP_CFG_ADDR 0x1590 157 #define MT6363_RG_BUCK_VBUCK2_RC5_OP_CFG_ADDR 0x1590 158 #define MT6363_RG_BUCK_VBUCK2_RC6_OP_CFG_ADDR 0x1590 159 #define MT6363_RG_BUCK_VBUCK2_RC7_OP_CFG_ADDR 0x1590 160 #define MT6363_RG_BUCK_VBUCK2_RC8_OP_CFG_ADDR 0x1591 161 #define MT6363_RG_BUCK_VBUCK2_RC9_OP_CFG_ADDR 0x1591 162 #define MT6363_RG_BUCK_VBUCK2_RC10_OP_CFG_ADDR 0x1591 163 #define MT6363_RG_BUCK_VBUCK2_RC11_OP_CFG_ADDR 0x1591 164 #define MT6363_RG_BUCK_VBUCK2_RC12_OP_CFG_ADDR 0x1591 165 #define MT6363_RG_BUCK_VBUCK2_RC13_OP_CFG_ADDR 0x1591 166 #define MT6363_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x1592 167 #define MT6363_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x1592 168 #define MT6363_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x1592 169 #define MT6363_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x1592 170 #define MT6363_RG_BUCK_VBUCK2_RC0_OP_MODE_ADDR 0x1593 171 #define MT6363_RG_BUCK_VBUCK2_RC1_OP_MODE_ADDR 0x1593 172 #define MT6363_RG_BUCK_VBUCK2_RC2_OP_MODE_ADDR 0x1593 173 #define MT6363_RG_BUCK_VBUCK2_RC3_OP_MODE_ADDR 0x1593 174 #define MT6363_RG_BUCK_VBUCK2_RC4_OP_MODE_ADDR 0x1593 175 #define MT6363_RG_BUCK_VBUCK2_RC5_OP_MODE_ADDR 0x1593 176 #define MT6363_RG_BUCK_VBUCK2_RC6_OP_MODE_ADDR 0x1593 177 #define MT6363_RG_BUCK_VBUCK2_RC7_OP_MODE_ADDR 0x1593 178 #define MT6363_RG_BUCK_VBUCK2_RC8_OP_MODE_ADDR 0x1594 179 #define MT6363_RG_BUCK_VBUCK2_RC9_OP_MODE_ADDR 0x1594 180 #define MT6363_RG_BUCK_VBUCK2_RC10_OP_MODE_ADDR 0x1594 181 #define MT6363_RG_BUCK_VBUCK2_RC11_OP_MODE_ADDR 0x1594 182 #define MT6363_RG_BUCK_VBUCK2_RC12_OP_MODE_ADDR 0x1594 183 #define MT6363_RG_BUCK_VBUCK2_RC13_OP_MODE_ADDR 0x1594 184 #define MT6363_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x1595 185 #define MT6363_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x1595 186 #define MT6363_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x1595 187 #define MT6363_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x1595 188 #define MT6363_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR 0x1607 189 #define MT6363_RG_BUCK_VBUCK3_ONLV_EN_ADDR 0x1608 190 #define MT6363_RG_BUCK_VBUCK3_ONLV_EN_SHIFT 4 191 #define MT6363_RG_BUCK_VBUCK3_RC0_OP_EN_ADDR 0x160D 192 #define MT6363_RG_BUCK_VBUCK3_RC1_OP_EN_ADDR 0x160D 193 #define MT6363_RG_BUCK_VBUCK3_RC2_OP_EN_ADDR 0x160D 194 #define MT6363_RG_BUCK_VBUCK3_RC3_OP_EN_ADDR 0x160D 195 #define MT6363_RG_BUCK_VBUCK3_RC4_OP_EN_ADDR 0x160D 196 #define MT6363_RG_BUCK_VBUCK3_RC5_OP_EN_ADDR 0x160D 197 #define MT6363_RG_BUCK_VBUCK3_RC6_OP_EN_ADDR 0x160D 198 #define MT6363_RG_BUCK_VBUCK3_RC7_OP_EN_ADDR 0x160D 199 #define MT6363_RG_BUCK_VBUCK3_RC8_OP_EN_ADDR 0x160E 200 #define MT6363_RG_BUCK_VBUCK3_RC9_OP_EN_ADDR 0x160E 201 #define MT6363_RG_BUCK_VBUCK3_RC10_OP_EN_ADDR 0x160E 202 #define MT6363_RG_BUCK_VBUCK3_RC11_OP_EN_ADDR 0x160E 203 #define MT6363_RG_BUCK_VBUCK3_RC12_OP_EN_ADDR 0x160E 204 #define MT6363_RG_BUCK_VBUCK3_RC13_OP_EN_ADDR 0x160E 205 #define MT6363_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x160F 206 #define MT6363_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x160F 207 #define MT6363_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x160F 208 #define MT6363_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x160F 209 #define MT6363_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x160F 210 #define MT6363_RG_BUCK_VBUCK3_RC0_OP_CFG_ADDR 0x1610 211 #define MT6363_RG_BUCK_VBUCK3_RC1_OP_CFG_ADDR 0x1610 212 #define MT6363_RG_BUCK_VBUCK3_RC2_OP_CFG_ADDR 0x1610 213 #define MT6363_RG_BUCK_VBUCK3_RC3_OP_CFG_ADDR 0x1610 214 #define MT6363_RG_BUCK_VBUCK3_RC4_OP_CFG_ADDR 0x1610 215 #define MT6363_RG_BUCK_VBUCK3_RC5_OP_CFG_ADDR 0x1610 216 #define MT6363_RG_BUCK_VBUCK3_RC6_OP_CFG_ADDR 0x1610 217 #define MT6363_RG_BUCK_VBUCK3_RC7_OP_CFG_ADDR 0x1610 218 #define MT6363_RG_BUCK_VBUCK3_RC8_OP_CFG_ADDR 0x1611 219 #define MT6363_RG_BUCK_VBUCK3_RC9_OP_CFG_ADDR 0x1611 220 #define MT6363_RG_BUCK_VBUCK3_RC10_OP_CFG_ADDR 0x1611 221 #define MT6363_RG_BUCK_VBUCK3_RC11_OP_CFG_ADDR 0x1611 222 #define MT6363_RG_BUCK_VBUCK3_RC12_OP_CFG_ADDR 0x1611 223 #define MT6363_RG_BUCK_VBUCK3_RC13_OP_CFG_ADDR 0x1611 224 #define MT6363_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x1612 225 #define MT6363_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x1612 226 #define MT6363_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x1612 227 #define MT6363_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x1612 228 #define MT6363_RG_BUCK_VBUCK3_RC0_OP_MODE_ADDR 0x1613 229 #define MT6363_RG_BUCK_VBUCK3_RC1_OP_MODE_ADDR 0x1613 230 #define MT6363_RG_BUCK_VBUCK3_RC2_OP_MODE_ADDR 0x1613 231 #define MT6363_RG_BUCK_VBUCK3_RC3_OP_MODE_ADDR 0x1613 232 #define MT6363_RG_BUCK_VBUCK3_RC4_OP_MODE_ADDR 0x1613 233 #define MT6363_RG_BUCK_VBUCK3_RC5_OP_MODE_ADDR 0x1613 234 #define MT6363_RG_BUCK_VBUCK3_RC6_OP_MODE_ADDR 0x1613 235 #define MT6363_RG_BUCK_VBUCK3_RC7_OP_MODE_ADDR 0x1613 236 #define MT6363_RG_BUCK_VBUCK3_RC8_OP_MODE_ADDR 0x1614 237 #define MT6363_RG_BUCK_VBUCK3_RC9_OP_MODE_ADDR 0x1614 238 #define MT6363_RG_BUCK_VBUCK3_RC10_OP_MODE_ADDR 0x1614 239 #define MT6363_RG_BUCK_VBUCK3_RC11_OP_MODE_ADDR 0x1614 240 #define MT6363_RG_BUCK_VBUCK3_RC12_OP_MODE_ADDR 0x1614 241 #define MT6363_RG_BUCK_VBUCK3_RC13_OP_MODE_ADDR 0x1614 242 #define MT6363_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x1615 243 #define MT6363_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x1615 244 #define MT6363_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x1615 245 #define MT6363_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x1615 246 #define MT6363_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR 0x1687 247 #define MT6363_RG_BUCK_VBUCK4_ONLV_EN_ADDR 0x1688 248 #define MT6363_RG_BUCK_VBUCK4_ONLV_EN_SHIFT 4 249 #define MT6363_RG_BUCK_VBUCK4_RC0_OP_EN_ADDR 0x168D 250 #define MT6363_RG_BUCK_VBUCK4_RC1_OP_EN_ADDR 0x168D 251 #define MT6363_RG_BUCK_VBUCK4_RC2_OP_EN_ADDR 0x168D 252 #define MT6363_RG_BUCK_VBUCK4_RC3_OP_EN_ADDR 0x168D 253 #define MT6363_RG_BUCK_VBUCK4_RC4_OP_EN_ADDR 0x168D 254 #define MT6363_RG_BUCK_VBUCK4_RC5_OP_EN_ADDR 0x168D 255 #define MT6363_RG_BUCK_VBUCK4_RC6_OP_EN_ADDR 0x168D 256 #define MT6363_RG_BUCK_VBUCK4_RC7_OP_EN_ADDR 0x168D 257 #define MT6363_RG_BUCK_VBUCK4_RC8_OP_EN_ADDR 0x168E 258 #define MT6363_RG_BUCK_VBUCK4_RC9_OP_EN_ADDR 0x168E 259 #define MT6363_RG_BUCK_VBUCK4_RC10_OP_EN_ADDR 0x168E 260 #define MT6363_RG_BUCK_VBUCK4_RC11_OP_EN_ADDR 0x168E 261 #define MT6363_RG_BUCK_VBUCK4_RC12_OP_EN_ADDR 0x168E 262 #define MT6363_RG_BUCK_VBUCK4_RC13_OP_EN_ADDR 0x168E 263 #define MT6363_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x168F 264 #define MT6363_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x168F 265 #define MT6363_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x168F 266 #define MT6363_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x168F 267 #define MT6363_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x168F 268 #define MT6363_RG_BUCK_VBUCK4_RC0_OP_CFG_ADDR 0x1690 269 #define MT6363_RG_BUCK_VBUCK4_RC1_OP_CFG_ADDR 0x1690 270 #define MT6363_RG_BUCK_VBUCK4_RC2_OP_CFG_ADDR 0x1690 271 #define MT6363_RG_BUCK_VBUCK4_RC3_OP_CFG_ADDR 0x1690 272 #define MT6363_RG_BUCK_VBUCK4_RC4_OP_CFG_ADDR 0x1690 273 #define MT6363_RG_BUCK_VBUCK4_RC5_OP_CFG_ADDR 0x1690 274 #define MT6363_RG_BUCK_VBUCK4_RC6_OP_CFG_ADDR 0x1690 275 #define MT6363_RG_BUCK_VBUCK4_RC7_OP_CFG_ADDR 0x1690 276 #define MT6363_RG_BUCK_VBUCK4_RC8_OP_CFG_ADDR 0x1691 277 #define MT6363_RG_BUCK_VBUCK4_RC9_OP_CFG_ADDR 0x1691 278 #define MT6363_RG_BUCK_VBUCK4_RC10_OP_CFG_ADDR 0x1691 279 #define MT6363_RG_BUCK_VBUCK4_RC11_OP_CFG_ADDR 0x1691 280 #define MT6363_RG_BUCK_VBUCK4_RC12_OP_CFG_ADDR 0x1691 281 #define MT6363_RG_BUCK_VBUCK4_RC13_OP_CFG_ADDR 0x1691 282 #define MT6363_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x1692 283 #define MT6363_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x1692 284 #define MT6363_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x1692 285 #define MT6363_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x1692 286 #define MT6363_RG_BUCK_VBUCK4_RC0_OP_MODE_ADDR 0x1693 287 #define MT6363_RG_BUCK_VBUCK4_RC1_OP_MODE_ADDR 0x1693 288 #define MT6363_RG_BUCK_VBUCK4_RC2_OP_MODE_ADDR 0x1693 289 #define MT6363_RG_BUCK_VBUCK4_RC3_OP_MODE_ADDR 0x1693 290 #define MT6363_RG_BUCK_VBUCK4_RC4_OP_MODE_ADDR 0x1693 291 #define MT6363_RG_BUCK_VBUCK4_RC5_OP_MODE_ADDR 0x1693 292 #define MT6363_RG_BUCK_VBUCK4_RC6_OP_MODE_ADDR 0x1693 293 #define MT6363_RG_BUCK_VBUCK4_RC7_OP_MODE_ADDR 0x1693 294 #define MT6363_RG_BUCK_VBUCK4_RC8_OP_MODE_ADDR 0x1694 295 #define MT6363_RG_BUCK_VBUCK4_RC9_OP_MODE_ADDR 0x1694 296 #define MT6363_RG_BUCK_VBUCK4_RC10_OP_MODE_ADDR 0x1694 297 #define MT6363_RG_BUCK_VBUCK4_RC11_OP_MODE_ADDR 0x1694 298 #define MT6363_RG_BUCK_VBUCK4_RC12_OP_MODE_ADDR 0x1694 299 #define MT6363_RG_BUCK_VBUCK4_RC13_OP_MODE_ADDR 0x1694 300 #define MT6363_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x1695 301 #define MT6363_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x1695 302 #define MT6363_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x1695 303 #define MT6363_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x1695 304 #define MT6363_RG_BUCK_VBUCK5_VOSEL_SLEEP_ADDR 0x1707 305 #define MT6363_RG_BUCK_VBUCK5_ONLV_EN_ADDR 0x1708 306 #define MT6363_RG_BUCK_VBUCK5_ONLV_EN_SHIFT 4 307 #define MT6363_RG_BUCK_VBUCK5_RC0_OP_EN_ADDR 0x170D 308 #define MT6363_RG_BUCK_VBUCK5_RC1_OP_EN_ADDR 0x170D 309 #define MT6363_RG_BUCK_VBUCK5_RC2_OP_EN_ADDR 0x170D 310 #define MT6363_RG_BUCK_VBUCK5_RC3_OP_EN_ADDR 0x170D 311 #define MT6363_RG_BUCK_VBUCK5_RC4_OP_EN_ADDR 0x170D 312 #define MT6363_RG_BUCK_VBUCK5_RC5_OP_EN_ADDR 0x170D 313 #define MT6363_RG_BUCK_VBUCK5_RC6_OP_EN_ADDR 0x170D 314 #define MT6363_RG_BUCK_VBUCK5_RC7_OP_EN_ADDR 0x170D 315 #define MT6363_RG_BUCK_VBUCK5_RC8_OP_EN_ADDR 0x170E 316 #define MT6363_RG_BUCK_VBUCK5_RC9_OP_EN_ADDR 0x170E 317 #define MT6363_RG_BUCK_VBUCK5_RC10_OP_EN_ADDR 0x170E 318 #define MT6363_RG_BUCK_VBUCK5_RC11_OP_EN_ADDR 0x170E 319 #define MT6363_RG_BUCK_VBUCK5_RC12_OP_EN_ADDR 0x170E 320 #define MT6363_RG_BUCK_VBUCK5_RC13_OP_EN_ADDR 0x170E 321 #define MT6363_RG_BUCK_VBUCK5_HW0_OP_EN_ADDR 0x170F 322 #define MT6363_RG_BUCK_VBUCK5_HW1_OP_EN_ADDR 0x170F 323 #define MT6363_RG_BUCK_VBUCK5_HW2_OP_EN_ADDR 0x170F 324 #define MT6363_RG_BUCK_VBUCK5_HW3_OP_EN_ADDR 0x170F 325 #define MT6363_RG_BUCK_VBUCK5_SW_OP_EN_ADDR 0x170F 326 #define MT6363_RG_BUCK_VBUCK5_RC0_OP_CFG_ADDR 0x1710 327 #define MT6363_RG_BUCK_VBUCK5_RC1_OP_CFG_ADDR 0x1710 328 #define MT6363_RG_BUCK_VBUCK5_RC2_OP_CFG_ADDR 0x1710 329 #define MT6363_RG_BUCK_VBUCK5_RC3_OP_CFG_ADDR 0x1710 330 #define MT6363_RG_BUCK_VBUCK5_RC4_OP_CFG_ADDR 0x1710 331 #define MT6363_RG_BUCK_VBUCK5_RC5_OP_CFG_ADDR 0x1710 332 #define MT6363_RG_BUCK_VBUCK5_RC6_OP_CFG_ADDR 0x1710 333 #define MT6363_RG_BUCK_VBUCK5_RC7_OP_CFG_ADDR 0x1710 334 #define MT6363_RG_BUCK_VBUCK5_RC8_OP_CFG_ADDR 0x1711 335 #define MT6363_RG_BUCK_VBUCK5_RC9_OP_CFG_ADDR 0x1711 336 #define MT6363_RG_BUCK_VBUCK5_RC10_OP_CFG_ADDR 0x1711 337 #define MT6363_RG_BUCK_VBUCK5_RC11_OP_CFG_ADDR 0x1711 338 #define MT6363_RG_BUCK_VBUCK5_RC12_OP_CFG_ADDR 0x1711 339 #define MT6363_RG_BUCK_VBUCK5_RC13_OP_CFG_ADDR 0x1711 340 #define MT6363_RG_BUCK_VBUCK5_HW0_OP_CFG_ADDR 0x1712 341 #define MT6363_RG_BUCK_VBUCK5_HW1_OP_CFG_ADDR 0x1712 342 #define MT6363_RG_BUCK_VBUCK5_HW2_OP_CFG_ADDR 0x1712 343 #define MT6363_RG_BUCK_VBUCK5_HW3_OP_CFG_ADDR 0x1712 344 #define MT6363_RG_BUCK_VBUCK5_RC0_OP_MODE_ADDR 0x1713 345 #define MT6363_RG_BUCK_VBUCK5_RC1_OP_MODE_ADDR 0x1713 346 #define MT6363_RG_BUCK_VBUCK5_RC2_OP_MODE_ADDR 0x1713 347 #define MT6363_RG_BUCK_VBUCK5_RC3_OP_MODE_ADDR 0x1713 348 #define MT6363_RG_BUCK_VBUCK5_RC4_OP_MODE_ADDR 0x1713 349 #define MT6363_RG_BUCK_VBUCK5_RC5_OP_MODE_ADDR 0x1713 350 #define MT6363_RG_BUCK_VBUCK5_RC6_OP_MODE_ADDR 0x1713 351 #define MT6363_RG_BUCK_VBUCK5_RC7_OP_MODE_ADDR 0x1713 352 #define MT6363_RG_BUCK_VBUCK5_RC8_OP_MODE_ADDR 0x1714 353 #define MT6363_RG_BUCK_VBUCK5_RC9_OP_MODE_ADDR 0x1714 354 #define MT6363_RG_BUCK_VBUCK5_RC10_OP_MODE_ADDR 0x1714 355 #define MT6363_RG_BUCK_VBUCK5_RC11_OP_MODE_ADDR 0x1714 356 #define MT6363_RG_BUCK_VBUCK5_RC12_OP_MODE_ADDR 0x1714 357 #define MT6363_RG_BUCK_VBUCK5_RC13_OP_MODE_ADDR 0x1714 358 #define MT6363_RG_BUCK_VBUCK5_HW0_OP_MODE_ADDR 0x1715 359 #define MT6363_RG_BUCK_VBUCK5_HW1_OP_MODE_ADDR 0x1715 360 #define MT6363_RG_BUCK_VBUCK5_HW2_OP_MODE_ADDR 0x1715 361 #define MT6363_RG_BUCK_VBUCK5_HW3_OP_MODE_ADDR 0x1715 362 #define MT6363_RG_BUCK_VBUCK6_VOSEL_SLEEP_ADDR 0x1787 363 #define MT6363_RG_BUCK_VBUCK6_ONLV_EN_ADDR 0x1788 364 #define MT6363_RG_BUCK_VBUCK6_ONLV_EN_SHIFT 4 365 #define MT6363_RG_BUCK_VBUCK6_RC0_OP_EN_ADDR 0x178D 366 #define MT6363_RG_BUCK_VBUCK6_RC1_OP_EN_ADDR 0x178D 367 #define MT6363_RG_BUCK_VBUCK6_RC2_OP_EN_ADDR 0x178D 368 #define MT6363_RG_BUCK_VBUCK6_RC3_OP_EN_ADDR 0x178D 369 #define MT6363_RG_BUCK_VBUCK6_RC4_OP_EN_ADDR 0x178D 370 #define MT6363_RG_BUCK_VBUCK6_RC5_OP_EN_ADDR 0x178D 371 #define MT6363_RG_BUCK_VBUCK6_RC6_OP_EN_ADDR 0x178D 372 #define MT6363_RG_BUCK_VBUCK6_RC7_OP_EN_ADDR 0x178D 373 #define MT6363_RG_BUCK_VBUCK6_RC8_OP_EN_ADDR 0x178E 374 #define MT6363_RG_BUCK_VBUCK6_RC9_OP_EN_ADDR 0x178E 375 #define MT6363_RG_BUCK_VBUCK6_RC10_OP_EN_ADDR 0x178E 376 #define MT6363_RG_BUCK_VBUCK6_RC11_OP_EN_ADDR 0x178E 377 #define MT6363_RG_BUCK_VBUCK6_RC12_OP_EN_ADDR 0x178E 378 #define MT6363_RG_BUCK_VBUCK6_RC13_OP_EN_ADDR 0x178E 379 #define MT6363_RG_BUCK_VBUCK6_HW0_OP_EN_ADDR 0x178F 380 #define MT6363_RG_BUCK_VBUCK6_HW1_OP_EN_ADDR 0x178F 381 #define MT6363_RG_BUCK_VBUCK6_HW2_OP_EN_ADDR 0x178F 382 #define MT6363_RG_BUCK_VBUCK6_HW3_OP_EN_ADDR 0x178F 383 #define MT6363_RG_BUCK_VBUCK6_SW_OP_EN_ADDR 0x178F 384 #define MT6363_RG_BUCK_VBUCK6_RC0_OP_CFG_ADDR 0x1790 385 #define MT6363_RG_BUCK_VBUCK6_RC1_OP_CFG_ADDR 0x1790 386 #define MT6363_RG_BUCK_VBUCK6_RC2_OP_CFG_ADDR 0x1790 387 #define MT6363_RG_BUCK_VBUCK6_RC3_OP_CFG_ADDR 0x1790 388 #define MT6363_RG_BUCK_VBUCK6_RC4_OP_CFG_ADDR 0x1790 389 #define MT6363_RG_BUCK_VBUCK6_RC5_OP_CFG_ADDR 0x1790 390 #define MT6363_RG_BUCK_VBUCK6_RC6_OP_CFG_ADDR 0x1790 391 #define MT6363_RG_BUCK_VBUCK6_RC7_OP_CFG_ADDR 0x1790 392 #define MT6363_RG_BUCK_VBUCK6_RC8_OP_CFG_ADDR 0x1791 393 #define MT6363_RG_BUCK_VBUCK6_RC9_OP_CFG_ADDR 0x1791 394 #define MT6363_RG_BUCK_VBUCK6_RC10_OP_CFG_ADDR 0x1791 395 #define MT6363_RG_BUCK_VBUCK6_RC11_OP_CFG_ADDR 0x1791 396 #define MT6363_RG_BUCK_VBUCK6_RC12_OP_CFG_ADDR 0x1791 397 #define MT6363_RG_BUCK_VBUCK6_RC13_OP_CFG_ADDR 0x1791 398 #define MT6363_RG_BUCK_VBUCK6_HW0_OP_CFG_ADDR 0x1792 399 #define MT6363_RG_BUCK_VBUCK6_HW1_OP_CFG_ADDR 0x1792 400 #define MT6363_RG_BUCK_VBUCK6_HW2_OP_CFG_ADDR 0x1792 401 #define MT6363_RG_BUCK_VBUCK6_HW3_OP_CFG_ADDR 0x1792 402 #define MT6363_RG_BUCK_VBUCK6_RC0_OP_MODE_ADDR 0x1793 403 #define MT6363_RG_BUCK_VBUCK6_RC1_OP_MODE_ADDR 0x1793 404 #define MT6363_RG_BUCK_VBUCK6_RC2_OP_MODE_ADDR 0x1793 405 #define MT6363_RG_BUCK_VBUCK6_RC3_OP_MODE_ADDR 0x1793 406 #define MT6363_RG_BUCK_VBUCK6_RC4_OP_MODE_ADDR 0x1793 407 #define MT6363_RG_BUCK_VBUCK6_RC5_OP_MODE_ADDR 0x1793 408 #define MT6363_RG_BUCK_VBUCK6_RC6_OP_MODE_ADDR 0x1793 409 #define MT6363_RG_BUCK_VBUCK6_RC7_OP_MODE_ADDR 0x1793 410 #define MT6363_RG_BUCK_VBUCK6_RC8_OP_MODE_ADDR 0x1794 411 #define MT6363_RG_BUCK_VBUCK6_RC9_OP_MODE_ADDR 0x1794 412 #define MT6363_RG_BUCK_VBUCK6_RC10_OP_MODE_ADDR 0x1794 413 #define MT6363_RG_BUCK_VBUCK6_RC11_OP_MODE_ADDR 0x1794 414 #define MT6363_RG_BUCK_VBUCK6_RC12_OP_MODE_ADDR 0x1794 415 #define MT6363_RG_BUCK_VBUCK6_RC13_OP_MODE_ADDR 0x1794 416 #define MT6363_RG_BUCK_VBUCK6_HW0_OP_MODE_ADDR 0x1795 417 #define MT6363_RG_BUCK_VBUCK6_HW1_OP_MODE_ADDR 0x1795 418 #define MT6363_RG_BUCK_VBUCK6_HW2_OP_MODE_ADDR 0x1795 419 #define MT6363_RG_BUCK_VBUCK6_HW3_OP_MODE_ADDR 0x1795 420 #define MT6363_RG_BUCK_VBUCK7_VOSEL_SLEEP_ADDR 0x1807 421 #define MT6363_RG_BUCK_VBUCK7_ONLV_EN_ADDR 0x1808 422 #define MT6363_RG_BUCK_VBUCK7_ONLV_EN_SHIFT 4 423 #define MT6363_RG_BUCK_VBUCK7_RC0_OP_EN_ADDR 0x180D 424 #define MT6363_RG_BUCK_VBUCK7_RC1_OP_EN_ADDR 0x180D 425 #define MT6363_RG_BUCK_VBUCK7_RC2_OP_EN_ADDR 0x180D 426 #define MT6363_RG_BUCK_VBUCK7_RC3_OP_EN_ADDR 0x180D 427 #define MT6363_RG_BUCK_VBUCK7_RC4_OP_EN_ADDR 0x180D 428 #define MT6363_RG_BUCK_VBUCK7_RC5_OP_EN_ADDR 0x180D 429 #define MT6363_RG_BUCK_VBUCK7_RC6_OP_EN_ADDR 0x180D 430 #define MT6363_RG_BUCK_VBUCK7_RC7_OP_EN_ADDR 0x180D 431 #define MT6363_RG_BUCK_VBUCK7_RC8_OP_EN_ADDR 0x180E 432 #define MT6363_RG_BUCK_VBUCK7_RC9_OP_EN_ADDR 0x180E 433 #define MT6363_RG_BUCK_VBUCK7_RC10_OP_EN_ADDR 0x180E 434 #define MT6363_RG_BUCK_VBUCK7_RC11_OP_EN_ADDR 0x180E 435 #define MT6363_RG_BUCK_VBUCK7_RC12_OP_EN_ADDR 0x180E 436 #define MT6363_RG_BUCK_VBUCK7_RC13_OP_EN_ADDR 0x180E 437 #define MT6363_RG_BUCK_VBUCK7_HW0_OP_EN_ADDR 0x180F 438 #define MT6363_RG_BUCK_VBUCK7_HW1_OP_EN_ADDR 0x180F 439 #define MT6363_RG_BUCK_VBUCK7_HW2_OP_EN_ADDR 0x180F 440 #define MT6363_RG_BUCK_VBUCK7_HW3_OP_EN_ADDR 0x180F 441 #define MT6363_RG_BUCK_VBUCK7_SW_OP_EN_ADDR 0x180F 442 #define MT6363_RG_BUCK_VBUCK7_RC0_OP_CFG_ADDR 0x1810 443 #define MT6363_RG_BUCK_VBUCK7_RC1_OP_CFG_ADDR 0x1810 444 #define MT6363_RG_BUCK_VBUCK7_RC2_OP_CFG_ADDR 0x1810 445 #define MT6363_RG_BUCK_VBUCK7_RC3_OP_CFG_ADDR 0x1810 446 #define MT6363_RG_BUCK_VBUCK7_RC4_OP_CFG_ADDR 0x1810 447 #define MT6363_RG_BUCK_VBUCK7_RC5_OP_CFG_ADDR 0x1810 448 #define MT6363_RG_BUCK_VBUCK7_RC6_OP_CFG_ADDR 0x1810 449 #define MT6363_RG_BUCK_VBUCK7_RC7_OP_CFG_ADDR 0x1810 450 #define MT6363_RG_BUCK_VBUCK7_RC8_OP_CFG_ADDR 0x1811 451 #define MT6363_RG_BUCK_VBUCK7_RC9_OP_CFG_ADDR 0x1811 452 #define MT6363_RG_BUCK_VBUCK7_RC10_OP_CFG_ADDR 0x1811 453 #define MT6363_RG_BUCK_VBUCK7_RC11_OP_CFG_ADDR 0x1811 454 #define MT6363_RG_BUCK_VBUCK7_RC12_OP_CFG_ADDR 0x1811 455 #define MT6363_RG_BUCK_VBUCK7_RC13_OP_CFG_ADDR 0x1811 456 #define MT6363_RG_BUCK_VBUCK7_HW0_OP_CFG_ADDR 0x1812 457 #define MT6363_RG_BUCK_VBUCK7_HW1_OP_CFG_ADDR 0x1812 458 #define MT6363_RG_BUCK_VBUCK7_HW2_OP_CFG_ADDR 0x1812 459 #define MT6363_RG_BUCK_VBUCK7_HW3_OP_CFG_ADDR 0x1812 460 #define MT6363_RG_BUCK_VBUCK7_RC0_OP_MODE_ADDR 0x1813 461 #define MT6363_RG_BUCK_VBUCK7_RC1_OP_MODE_ADDR 0x1813 462 #define MT6363_RG_BUCK_VBUCK7_RC2_OP_MODE_ADDR 0x1813 463 #define MT6363_RG_BUCK_VBUCK7_RC3_OP_MODE_ADDR 0x1813 464 #define MT6363_RG_BUCK_VBUCK7_RC4_OP_MODE_ADDR 0x1813 465 #define MT6363_RG_BUCK_VBUCK7_RC5_OP_MODE_ADDR 0x1813 466 #define MT6363_RG_BUCK_VBUCK7_RC6_OP_MODE_ADDR 0x1813 467 #define MT6363_RG_BUCK_VBUCK7_RC7_OP_MODE_ADDR 0x1813 468 #define MT6363_RG_BUCK_VBUCK7_RC8_OP_MODE_ADDR 0x1814 469 #define MT6363_RG_BUCK_VBUCK7_RC9_OP_MODE_ADDR 0x1814 470 #define MT6363_RG_BUCK_VBUCK7_RC10_OP_MODE_ADDR 0x1814 471 #define MT6363_RG_BUCK_VBUCK7_RC11_OP_MODE_ADDR 0x1814 472 #define MT6363_RG_BUCK_VBUCK7_RC12_OP_MODE_ADDR 0x1814 473 #define MT6363_RG_BUCK_VBUCK7_RC13_OP_MODE_ADDR 0x1814 474 #define MT6363_RG_BUCK_VBUCK7_HW0_OP_MODE_ADDR 0x1815 475 #define MT6363_RG_BUCK_VBUCK7_HW1_OP_MODE_ADDR 0x1815 476 #define MT6363_RG_BUCK_VBUCK7_HW2_OP_MODE_ADDR 0x1815 477 #define MT6363_RG_BUCK_VBUCK7_HW3_OP_MODE_ADDR 0x1815 478 #define MT6363_RG_BUCK_VS1_VOSEL_SLEEP_ADDR 0x1887 479 #define MT6363_RG_BUCK_VS1_ONLV_EN_ADDR 0x1888 480 #define MT6363_RG_BUCK_VS1_ONLV_EN_SHIFT 4 481 #define MT6363_RG_BUCK_VS1_RC0_OP_EN_ADDR 0x188D 482 #define MT6363_RG_BUCK_VS1_RC1_OP_EN_ADDR 0x188D 483 #define MT6363_RG_BUCK_VS1_RC2_OP_EN_ADDR 0x188D 484 #define MT6363_RG_BUCK_VS1_RC3_OP_EN_ADDR 0x188D 485 #define MT6363_RG_BUCK_VS1_RC4_OP_EN_ADDR 0x188D 486 #define MT6363_RG_BUCK_VS1_RC5_OP_EN_ADDR 0x188D 487 #define MT6363_RG_BUCK_VS1_RC6_OP_EN_ADDR 0x188D 488 #define MT6363_RG_BUCK_VS1_RC7_OP_EN_ADDR 0x188D 489 #define MT6363_RG_BUCK_VS1_RC8_OP_EN_ADDR 0x188E 490 #define MT6363_RG_BUCK_VS1_RC9_OP_EN_ADDR 0x188E 491 #define MT6363_RG_BUCK_VS1_RC10_OP_EN_ADDR 0x188E 492 #define MT6363_RG_BUCK_VS1_RC11_OP_EN_ADDR 0x188E 493 #define MT6363_RG_BUCK_VS1_RC12_OP_EN_ADDR 0x188E 494 #define MT6363_RG_BUCK_VS1_RC13_OP_EN_ADDR 0x188E 495 #define MT6363_RG_BUCK_VS1_HW0_OP_EN_ADDR 0x188F 496 #define MT6363_RG_BUCK_VS1_HW1_OP_EN_ADDR 0x188F 497 #define MT6363_RG_BUCK_VS1_HW2_OP_EN_ADDR 0x188F 498 #define MT6363_RG_BUCK_VS1_HW3_OP_EN_ADDR 0x188F 499 #define MT6363_RG_BUCK_VS1_HW4_OP_EN_ADDR 0x188F 500 #define MT6363_RG_BUCK_VS1_SW_OP_EN_ADDR 0x188F 501 #define MT6363_RG_BUCK_VS1_RC0_OP_CFG_ADDR 0x1890 502 #define MT6363_RG_BUCK_VS1_RC1_OP_CFG_ADDR 0x1890 503 #define MT6363_RG_BUCK_VS1_RC2_OP_CFG_ADDR 0x1890 504 #define MT6363_RG_BUCK_VS1_RC3_OP_CFG_ADDR 0x1890 505 #define MT6363_RG_BUCK_VS1_RC4_OP_CFG_ADDR 0x1890 506 #define MT6363_RG_BUCK_VS1_RC5_OP_CFG_ADDR 0x1890 507 #define MT6363_RG_BUCK_VS1_RC6_OP_CFG_ADDR 0x1890 508 #define MT6363_RG_BUCK_VS1_RC7_OP_CFG_ADDR 0x1890 509 #define MT6363_RG_BUCK_VS1_RC8_OP_CFG_ADDR 0x1891 510 #define MT6363_RG_BUCK_VS1_RC9_OP_CFG_ADDR 0x1891 511 #define MT6363_RG_BUCK_VS1_RC10_OP_CFG_ADDR 0x1891 512 #define MT6363_RG_BUCK_VS1_RC11_OP_CFG_ADDR 0x1891 513 #define MT6363_RG_BUCK_VS1_RC12_OP_CFG_ADDR 0x1891 514 #define MT6363_RG_BUCK_VS1_RC13_OP_CFG_ADDR 0x1891 515 #define MT6363_RG_BUCK_VS1_HW0_OP_CFG_ADDR 0x1892 516 #define MT6363_RG_BUCK_VS1_HW1_OP_CFG_ADDR 0x1892 517 #define MT6363_RG_BUCK_VS1_HW2_OP_CFG_ADDR 0x1892 518 #define MT6363_RG_BUCK_VS1_HW3_OP_CFG_ADDR 0x1892 519 #define MT6363_RG_BUCK_VS1_HW4_OP_CFG_ADDR 0x1892 520 #define MT6363_RG_BUCK_VS1_RC0_OP_MODE_ADDR 0x1893 521 #define MT6363_RG_BUCK_VS1_RC1_OP_MODE_ADDR 0x1893 522 #define MT6363_RG_BUCK_VS1_RC2_OP_MODE_ADDR 0x1893 523 #define MT6363_RG_BUCK_VS1_RC3_OP_MODE_ADDR 0x1893 524 #define MT6363_RG_BUCK_VS1_RC4_OP_MODE_ADDR 0x1893 525 #define MT6363_RG_BUCK_VS1_RC5_OP_MODE_ADDR 0x1893 526 #define MT6363_RG_BUCK_VS1_RC6_OP_MODE_ADDR 0x1893 527 #define MT6363_RG_BUCK_VS1_RC7_OP_MODE_ADDR 0x1893 528 #define MT6363_RG_BUCK_VS1_RC8_OP_MODE_ADDR 0x1894 529 #define MT6363_RG_BUCK_VS1_RC9_OP_MODE_ADDR 0x1894 530 #define MT6363_RG_BUCK_VS1_RC10_OP_MODE_ADDR 0x1894 531 #define MT6363_RG_BUCK_VS1_RC11_OP_MODE_ADDR 0x1894 532 #define MT6363_RG_BUCK_VS1_RC12_OP_MODE_ADDR 0x1894 533 #define MT6363_RG_BUCK_VS1_RC13_OP_MODE_ADDR 0x1894 534 #define MT6363_RG_BUCK_VS1_HW0_OP_MODE_ADDR 0x1895 535 #define MT6363_RG_BUCK_VS1_HW1_OP_MODE_ADDR 0x1895 536 #define MT6363_RG_BUCK_VS1_HW2_OP_MODE_ADDR 0x1895 537 #define MT6363_RG_BUCK_VS1_HW3_OP_MODE_ADDR 0x1895 538 #define MT6363_RG_BUCK_VS1_HW4_OP_MODE_ADDR 0x1895 539 #define MT6363_RG_BUCK_VS3_VOSEL_SLEEP_ADDR 0x1907 540 #define MT6363_RG_BUCK_VS3_ONLV_EN_ADDR 0x1908 541 #define MT6363_RG_BUCK_VS3_ONLV_EN_SHIFT 4 542 #define MT6363_RG_BUCK_VS3_RC0_OP_EN_ADDR 0x190D 543 #define MT6363_RG_BUCK_VS3_RC1_OP_EN_ADDR 0x190D 544 #define MT6363_RG_BUCK_VS3_RC2_OP_EN_ADDR 0x190D 545 #define MT6363_RG_BUCK_VS3_RC3_OP_EN_ADDR 0x190D 546 #define MT6363_RG_BUCK_VS3_RC4_OP_EN_ADDR 0x190D 547 #define MT6363_RG_BUCK_VS3_RC5_OP_EN_ADDR 0x190D 548 #define MT6363_RG_BUCK_VS3_RC6_OP_EN_ADDR 0x190D 549 #define MT6363_RG_BUCK_VS3_RC7_OP_EN_ADDR 0x190D 550 #define MT6363_RG_BUCK_VS3_RC8_OP_EN_ADDR 0x190E 551 #define MT6363_RG_BUCK_VS3_RC9_OP_EN_ADDR 0x190E 552 #define MT6363_RG_BUCK_VS3_RC10_OP_EN_ADDR 0x190E 553 #define MT6363_RG_BUCK_VS3_RC11_OP_EN_ADDR 0x190E 554 #define MT6363_RG_BUCK_VS3_RC12_OP_EN_ADDR 0x190E 555 #define MT6363_RG_BUCK_VS3_RC13_OP_EN_ADDR 0x190E 556 #define MT6363_RG_BUCK_VS3_HW0_OP_EN_ADDR 0x190F 557 #define MT6363_RG_BUCK_VS3_HW1_OP_EN_ADDR 0x190F 558 #define MT6363_RG_BUCK_VS3_HW2_OP_EN_ADDR 0x190F 559 #define MT6363_RG_BUCK_VS3_HW3_OP_EN_ADDR 0x190F 560 #define MT6363_RG_BUCK_VS3_HW4_OP_EN_ADDR 0x190F 561 #define MT6363_RG_BUCK_VS3_SW_OP_EN_ADDR 0x190F 562 #define MT6363_RG_BUCK_VS3_RC0_OP_CFG_ADDR 0x1910 563 #define MT6363_RG_BUCK_VS3_RC1_OP_CFG_ADDR 0x1910 564 #define MT6363_RG_BUCK_VS3_RC2_OP_CFG_ADDR 0x1910 565 #define MT6363_RG_BUCK_VS3_RC3_OP_CFG_ADDR 0x1910 566 #define MT6363_RG_BUCK_VS3_RC4_OP_CFG_ADDR 0x1910 567 #define MT6363_RG_BUCK_VS3_RC5_OP_CFG_ADDR 0x1910 568 #define MT6363_RG_BUCK_VS3_RC6_OP_CFG_ADDR 0x1910 569 #define MT6363_RG_BUCK_VS3_RC7_OP_CFG_ADDR 0x1910 570 #define MT6363_RG_BUCK_VS3_RC8_OP_CFG_ADDR 0x1911 571 #define MT6363_RG_BUCK_VS3_RC9_OP_CFG_ADDR 0x1911 572 #define MT6363_RG_BUCK_VS3_RC10_OP_CFG_ADDR 0x1911 573 #define MT6363_RG_BUCK_VS3_RC11_OP_CFG_ADDR 0x1911 574 #define MT6363_RG_BUCK_VS3_RC12_OP_CFG_ADDR 0x1911 575 #define MT6363_RG_BUCK_VS3_RC13_OP_CFG_ADDR 0x1911 576 #define MT6363_RG_BUCK_VS3_HW0_OP_CFG_ADDR 0x1912 577 #define MT6363_RG_BUCK_VS3_HW1_OP_CFG_ADDR 0x1912 578 #define MT6363_RG_BUCK_VS3_HW2_OP_CFG_ADDR 0x1912 579 #define MT6363_RG_BUCK_VS3_HW3_OP_CFG_ADDR 0x1912 580 #define MT6363_RG_BUCK_VS3_HW4_OP_CFG_ADDR 0x1912 581 #define MT6363_RG_BUCK_VS3_RC0_OP_MODE_ADDR 0x1913 582 #define MT6363_RG_BUCK_VS3_RC1_OP_MODE_ADDR 0x1913 583 #define MT6363_RG_BUCK_VS3_RC2_OP_MODE_ADDR 0x1913 584 #define MT6363_RG_BUCK_VS3_RC3_OP_MODE_ADDR 0x1913 585 #define MT6363_RG_BUCK_VS3_RC4_OP_MODE_ADDR 0x1913 586 #define MT6363_RG_BUCK_VS3_RC5_OP_MODE_ADDR 0x1913 587 #define MT6363_RG_BUCK_VS3_RC6_OP_MODE_ADDR 0x1913 588 #define MT6363_RG_BUCK_VS3_RC7_OP_MODE_ADDR 0x1913 589 #define MT6363_RG_BUCK_VS3_RC8_OP_MODE_ADDR 0x1914 590 #define MT6363_RG_BUCK_VS3_RC9_OP_MODE_ADDR 0x1914 591 #define MT6363_RG_BUCK_VS3_RC10_OP_MODE_ADDR 0x1914 592 #define MT6363_RG_BUCK_VS3_RC11_OP_MODE_ADDR 0x1914 593 #define MT6363_RG_BUCK_VS3_RC12_OP_MODE_ADDR 0x1914 594 #define MT6363_RG_BUCK_VS3_RC13_OP_MODE_ADDR 0x1914 595 #define MT6363_RG_BUCK_VS3_HW0_OP_MODE_ADDR 0x1915 596 #define MT6363_RG_BUCK_VS3_HW1_OP_MODE_ADDR 0x1915 597 #define MT6363_RG_BUCK_VS3_HW2_OP_MODE_ADDR 0x1915 598 #define MT6363_RG_BUCK_VS3_HW3_OP_MODE_ADDR 0x1915 599 #define MT6363_RG_BUCK_VS3_HW4_OP_MODE_ADDR 0x1915 600 #define MT6363_RG_LDO_VCN15_ONLV_EN_ADDR 0x1B88 601 #define MT6363_RG_LDO_VCN15_ONLV_EN_SHIFT 3 602 #define MT6363_RG_LDO_VCN15_RC0_OP_EN_ADDR 0x1B8C 603 #define MT6363_RG_LDO_VCN15_RC1_OP_EN_ADDR 0x1B8C 604 #define MT6363_RG_LDO_VCN15_RC2_OP_EN_ADDR 0x1B8C 605 #define MT6363_RG_LDO_VCN15_RC3_OP_EN_ADDR 0x1B8C 606 #define MT6363_RG_LDO_VCN15_RC4_OP_EN_ADDR 0x1B8C 607 #define MT6363_RG_LDO_VCN15_RC5_OP_EN_ADDR 0x1B8C 608 #define MT6363_RG_LDO_VCN15_RC6_OP_EN_ADDR 0x1B8C 609 #define MT6363_RG_LDO_VCN15_RC7_OP_EN_ADDR 0x1B8C 610 #define MT6363_RG_LDO_VCN15_RC8_OP_EN_ADDR 0x1B8D 611 #define MT6363_RG_LDO_VCN15_RC9_OP_EN_ADDR 0x1B8D 612 #define MT6363_RG_LDO_VCN15_RC10_OP_EN_ADDR 0x1B8D 613 #define MT6363_RG_LDO_VCN15_RC11_OP_EN_ADDR 0x1B8D 614 #define MT6363_RG_LDO_VCN15_RC12_OP_EN_ADDR 0x1B8D 615 #define MT6363_RG_LDO_VCN15_RC13_OP_EN_ADDR 0x1B8D 616 #define MT6363_RG_LDO_VCN15_HW0_OP_EN_ADDR 0x1B8E 617 #define MT6363_RG_LDO_VCN15_HW1_OP_EN_ADDR 0x1B8E 618 #define MT6363_RG_LDO_VCN15_HW2_OP_EN_ADDR 0x1B8E 619 #define MT6363_RG_LDO_VCN15_HW3_OP_EN_ADDR 0x1B8E 620 #define MT6363_RG_LDO_VCN15_HW4_OP_EN_ADDR 0x1B8E 621 #define MT6363_RG_LDO_VCN15_HW5_OP_EN_ADDR 0x1B8E 622 #define MT6363_RG_LDO_VCN15_HW6_OP_EN_ADDR 0x1B8E 623 #define MT6363_RG_LDO_VCN15_SW_OP_EN_ADDR 0x1B8E 624 #define MT6363_RG_LDO_VCN15_RC0_OP_CFG_ADDR 0x1B8F 625 #define MT6363_RG_LDO_VCN15_RC1_OP_CFG_ADDR 0x1B8F 626 #define MT6363_RG_LDO_VCN15_RC2_OP_CFG_ADDR 0x1B8F 627 #define MT6363_RG_LDO_VCN15_RC3_OP_CFG_ADDR 0x1B8F 628 #define MT6363_RG_LDO_VCN15_RC4_OP_CFG_ADDR 0x1B8F 629 #define MT6363_RG_LDO_VCN15_RC5_OP_CFG_ADDR 0x1B8F 630 #define MT6363_RG_LDO_VCN15_RC6_OP_CFG_ADDR 0x1B8F 631 #define MT6363_RG_LDO_VCN15_RC7_OP_CFG_ADDR 0x1B8F 632 #define MT6363_RG_LDO_VCN15_RC8_OP_CFG_ADDR 0x1B90 633 #define MT6363_RG_LDO_VCN15_RC9_OP_CFG_ADDR 0x1B90 634 #define MT6363_RG_LDO_VCN15_RC10_OP_CFG_ADDR 0x1B90 635 #define MT6363_RG_LDO_VCN15_RC11_OP_CFG_ADDR 0x1B90 636 #define MT6363_RG_LDO_VCN15_RC12_OP_CFG_ADDR 0x1B90 637 #define MT6363_RG_LDO_VCN15_RC13_OP_CFG_ADDR 0x1B90 638 #define MT6363_RG_LDO_VCN15_HW0_OP_CFG_ADDR 0x1B91 639 #define MT6363_RG_LDO_VCN15_HW1_OP_CFG_ADDR 0x1B91 640 #define MT6363_RG_LDO_VCN15_HW2_OP_CFG_ADDR 0x1B91 641 #define MT6363_RG_LDO_VCN15_HW3_OP_CFG_ADDR 0x1B91 642 #define MT6363_RG_LDO_VCN15_HW4_OP_CFG_ADDR 0x1B91 643 #define MT6363_RG_LDO_VCN15_HW5_OP_CFG_ADDR 0x1B91 644 #define MT6363_RG_LDO_VCN15_HW6_OP_CFG_ADDR 0x1B91 645 #define MT6363_RG_LDO_VCN15_SW_OP_CFG_ADDR 0x1B91 646 #define MT6363_RG_LDO_VCN15_RC0_OP_MODE_ADDR 0x1B92 647 #define MT6363_RG_LDO_VCN15_RC1_OP_MODE_ADDR 0x1B92 648 #define MT6363_RG_LDO_VCN15_RC2_OP_MODE_ADDR 0x1B92 649 #define MT6363_RG_LDO_VCN15_RC3_OP_MODE_ADDR 0x1B92 650 #define MT6363_RG_LDO_VCN15_RC4_OP_MODE_ADDR 0x1B92 651 #define MT6363_RG_LDO_VCN15_RC5_OP_MODE_ADDR 0x1B92 652 #define MT6363_RG_LDO_VCN15_RC6_OP_MODE_ADDR 0x1B92 653 #define MT6363_RG_LDO_VCN15_RC7_OP_MODE_ADDR 0x1B92 654 #define MT6363_RG_LDO_VCN15_RC8_OP_MODE_ADDR 0x1B93 655 #define MT6363_RG_LDO_VCN15_RC9_OP_MODE_ADDR 0x1B93 656 #define MT6363_RG_LDO_VCN15_RC10_OP_MODE_ADDR 0x1B93 657 #define MT6363_RG_LDO_VCN15_RC11_OP_MODE_ADDR 0x1B93 658 #define MT6363_RG_LDO_VCN15_RC12_OP_MODE_ADDR 0x1B93 659 #define MT6363_RG_LDO_VCN15_RC13_OP_MODE_ADDR 0x1B93 660 #define MT6363_RG_LDO_VCN15_HW0_OP_MODE_ADDR 0x1B94 661 #define MT6363_RG_LDO_VCN15_HW1_OP_MODE_ADDR 0x1B94 662 #define MT6363_RG_LDO_VCN15_HW2_OP_MODE_ADDR 0x1B94 663 #define MT6363_RG_LDO_VCN15_HW3_OP_MODE_ADDR 0x1B94 664 #define MT6363_RG_LDO_VCN15_HW4_OP_MODE_ADDR 0x1B94 665 #define MT6363_RG_LDO_VCN15_HW5_OP_MODE_ADDR 0x1B94 666 #define MT6363_RG_LDO_VCN15_HW6_OP_MODE_ADDR 0x1B94 667 #define MT6363_RG_LDO_VRF09_ONLV_EN_ADDR 0x1B96 668 #define MT6363_RG_LDO_VRF09_ONLV_EN_SHIFT 3 669 #define MT6363_RG_LDO_VRF09_RC0_OP_EN_ADDR 0x1B9A 670 #define MT6363_RG_LDO_VRF09_RC1_OP_EN_ADDR 0x1B9A 671 #define MT6363_RG_LDO_VRF09_RC2_OP_EN_ADDR 0x1B9A 672 #define MT6363_RG_LDO_VRF09_RC3_OP_EN_ADDR 0x1B9A 673 #define MT6363_RG_LDO_VRF09_RC4_OP_EN_ADDR 0x1B9A 674 #define MT6363_RG_LDO_VRF09_RC5_OP_EN_ADDR 0x1B9A 675 #define MT6363_RG_LDO_VRF09_RC6_OP_EN_ADDR 0x1B9A 676 #define MT6363_RG_LDO_VRF09_RC7_OP_EN_ADDR 0x1B9A 677 #define MT6363_RG_LDO_VRF09_RC8_OP_EN_ADDR 0x1B9B 678 #define MT6363_RG_LDO_VRF09_RC9_OP_EN_ADDR 0x1B9B 679 #define MT6363_RG_LDO_VRF09_RC10_OP_EN_ADDR 0x1B9B 680 #define MT6363_RG_LDO_VRF09_RC11_OP_EN_ADDR 0x1B9B 681 #define MT6363_RG_LDO_VRF09_RC12_OP_EN_ADDR 0x1B9B 682 #define MT6363_RG_LDO_VRF09_RC13_OP_EN_ADDR 0x1B9B 683 #define MT6363_RG_LDO_VRF09_HW0_OP_EN_ADDR 0x1B9C 684 #define MT6363_RG_LDO_VRF09_HW1_OP_EN_ADDR 0x1B9C 685 #define MT6363_RG_LDO_VRF09_HW2_OP_EN_ADDR 0x1B9C 686 #define MT6363_RG_LDO_VRF09_HW3_OP_EN_ADDR 0x1B9C 687 #define MT6363_RG_LDO_VRF09_HW4_OP_EN_ADDR 0x1B9C 688 #define MT6363_RG_LDO_VRF09_HW5_OP_EN_ADDR 0x1B9C 689 #define MT6363_RG_LDO_VRF09_HW6_OP_EN_ADDR 0x1B9C 690 #define MT6363_RG_LDO_VRF09_SW_OP_EN_ADDR 0x1B9C 691 #define MT6363_RG_LDO_VRF09_RC0_OP_CFG_ADDR 0x1B9D 692 #define MT6363_RG_LDO_VRF09_RC1_OP_CFG_ADDR 0x1B9D 693 #define MT6363_RG_LDO_VRF09_RC2_OP_CFG_ADDR 0x1B9D 694 #define MT6363_RG_LDO_VRF09_RC3_OP_CFG_ADDR 0x1B9D 695 #define MT6363_RG_LDO_VRF09_RC4_OP_CFG_ADDR 0x1B9D 696 #define MT6363_RG_LDO_VRF09_RC5_OP_CFG_ADDR 0x1B9D 697 #define MT6363_RG_LDO_VRF09_RC6_OP_CFG_ADDR 0x1B9D 698 #define MT6363_RG_LDO_VRF09_RC7_OP_CFG_ADDR 0x1B9D 699 #define MT6363_RG_LDO_VRF09_RC8_OP_CFG_ADDR 0x1B9E 700 #define MT6363_RG_LDO_VRF09_RC9_OP_CFG_ADDR 0x1B9E 701 #define MT6363_RG_LDO_VRF09_RC10_OP_CFG_ADDR 0x1B9E 702 #define MT6363_RG_LDO_VRF09_RC11_OP_CFG_ADDR 0x1B9E 703 #define MT6363_RG_LDO_VRF09_RC12_OP_CFG_ADDR 0x1B9E 704 #define MT6363_RG_LDO_VRF09_RC13_OP_CFG_ADDR 0x1B9E 705 #define MT6363_RG_LDO_VRF09_HW0_OP_CFG_ADDR 0x1B9F 706 #define MT6363_RG_LDO_VRF09_HW1_OP_CFG_ADDR 0x1B9F 707 #define MT6363_RG_LDO_VRF09_HW2_OP_CFG_ADDR 0x1B9F 708 #define MT6363_RG_LDO_VRF09_HW3_OP_CFG_ADDR 0x1B9F 709 #define MT6363_RG_LDO_VRF09_HW4_OP_CFG_ADDR 0x1B9F 710 #define MT6363_RG_LDO_VRF09_HW5_OP_CFG_ADDR 0x1B9F 711 #define MT6363_RG_LDO_VRF09_HW6_OP_CFG_ADDR 0x1B9F 712 #define MT6363_RG_LDO_VRF09_SW_OP_CFG_ADDR 0x1B9F 713 #define MT6363_RG_LDO_VRF09_RC0_OP_MODE_ADDR 0x1BA0 714 #define MT6363_RG_LDO_VRF09_RC1_OP_MODE_ADDR 0x1BA0 715 #define MT6363_RG_LDO_VRF09_RC2_OP_MODE_ADDR 0x1BA0 716 #define MT6363_RG_LDO_VRF09_RC3_OP_MODE_ADDR 0x1BA0 717 #define MT6363_RG_LDO_VRF09_RC4_OP_MODE_ADDR 0x1BA0 718 #define MT6363_RG_LDO_VRF09_RC5_OP_MODE_ADDR 0x1BA0 719 #define MT6363_RG_LDO_VRF09_RC6_OP_MODE_ADDR 0x1BA0 720 #define MT6363_RG_LDO_VRF09_RC7_OP_MODE_ADDR 0x1BA0 721 #define MT6363_RG_LDO_VRF09_RC8_OP_MODE_ADDR 0x1BA1 722 #define MT6363_RG_LDO_VRF09_RC9_OP_MODE_ADDR 0x1BA1 723 #define MT6363_RG_LDO_VRF09_RC10_OP_MODE_ADDR 0x1BA1 724 #define MT6363_RG_LDO_VRF09_RC11_OP_MODE_ADDR 0x1BA1 725 #define MT6363_RG_LDO_VRF09_RC12_OP_MODE_ADDR 0x1BA1 726 #define MT6363_RG_LDO_VRF09_RC13_OP_MODE_ADDR 0x1BA1 727 #define MT6363_RG_LDO_VRF09_HW0_OP_MODE_ADDR 0x1BA2 728 #define MT6363_RG_LDO_VRF09_HW1_OP_MODE_ADDR 0x1BA2 729 #define MT6363_RG_LDO_VRF09_HW2_OP_MODE_ADDR 0x1BA2 730 #define MT6363_RG_LDO_VRF09_HW3_OP_MODE_ADDR 0x1BA2 731 #define MT6363_RG_LDO_VRF09_HW4_OP_MODE_ADDR 0x1BA2 732 #define MT6363_RG_LDO_VRF09_HW5_OP_MODE_ADDR 0x1BA2 733 #define MT6363_RG_LDO_VRF09_HW6_OP_MODE_ADDR 0x1BA2 734 #define MT6363_RG_LDO_VRF12_ONLV_EN_ADDR 0x1BA4 735 #define MT6363_RG_LDO_VRF12_ONLV_EN_SHIFT 3 736 #define MT6363_RG_LDO_VRF12_RC0_OP_EN_ADDR 0x1BA8 737 #define MT6363_RG_LDO_VRF12_RC1_OP_EN_ADDR 0x1BA8 738 #define MT6363_RG_LDO_VRF12_RC2_OP_EN_ADDR 0x1BA8 739 #define MT6363_RG_LDO_VRF12_RC3_OP_EN_ADDR 0x1BA8 740 #define MT6363_RG_LDO_VRF12_RC4_OP_EN_ADDR 0x1BA8 741 #define MT6363_RG_LDO_VRF12_RC5_OP_EN_ADDR 0x1BA8 742 #define MT6363_RG_LDO_VRF12_RC6_OP_EN_ADDR 0x1BA8 743 #define MT6363_RG_LDO_VRF12_RC7_OP_EN_ADDR 0x1BA8 744 #define MT6363_RG_LDO_VRF12_RC8_OP_EN_ADDR 0x1BA9 745 #define MT6363_RG_LDO_VRF12_RC9_OP_EN_ADDR 0x1BA9 746 #define MT6363_RG_LDO_VRF12_RC10_OP_EN_ADDR 0x1BA9 747 #define MT6363_RG_LDO_VRF12_RC11_OP_EN_ADDR 0x1BA9 748 #define MT6363_RG_LDO_VRF12_RC12_OP_EN_ADDR 0x1BA9 749 #define MT6363_RG_LDO_VRF12_RC13_OP_EN_ADDR 0x1BA9 750 #define MT6363_RG_LDO_VRF12_HW0_OP_EN_ADDR 0x1BAA 751 #define MT6363_RG_LDO_VRF12_HW1_OP_EN_ADDR 0x1BAA 752 #define MT6363_RG_LDO_VRF12_HW2_OP_EN_ADDR 0x1BAA 753 #define MT6363_RG_LDO_VRF12_HW3_OP_EN_ADDR 0x1BAA 754 #define MT6363_RG_LDO_VRF12_HW4_OP_EN_ADDR 0x1BAA 755 #define MT6363_RG_LDO_VRF12_HW5_OP_EN_ADDR 0x1BAA 756 #define MT6363_RG_LDO_VRF12_HW6_OP_EN_ADDR 0x1BAA 757 #define MT6363_RG_LDO_VRF12_SW_OP_EN_ADDR 0x1BAA 758 #define MT6363_RG_LDO_VRF12_RC0_OP_CFG_ADDR 0x1BAB 759 #define MT6363_RG_LDO_VRF12_RC1_OP_CFG_ADDR 0x1BAB 760 #define MT6363_RG_LDO_VRF12_RC2_OP_CFG_ADDR 0x1BAB 761 #define MT6363_RG_LDO_VRF12_RC3_OP_CFG_ADDR 0x1BAB 762 #define MT6363_RG_LDO_VRF12_RC4_OP_CFG_ADDR 0x1BAB 763 #define MT6363_RG_LDO_VRF12_RC5_OP_CFG_ADDR 0x1BAB 764 #define MT6363_RG_LDO_VRF12_RC6_OP_CFG_ADDR 0x1BAB 765 #define MT6363_RG_LDO_VRF12_RC7_OP_CFG_ADDR 0x1BAB 766 #define MT6363_RG_LDO_VRF12_RC8_OP_CFG_ADDR 0x1BAC 767 #define MT6363_RG_LDO_VRF12_RC9_OP_CFG_ADDR 0x1BAC 768 #define MT6363_RG_LDO_VRF12_RC10_OP_CFG_ADDR 0x1BAC 769 #define MT6363_RG_LDO_VRF12_RC11_OP_CFG_ADDR 0x1BAC 770 #define MT6363_RG_LDO_VRF12_RC12_OP_CFG_ADDR 0x1BAC 771 #define MT6363_RG_LDO_VRF12_RC13_OP_CFG_ADDR 0x1BAC 772 #define MT6363_RG_LDO_VRF12_HW0_OP_CFG_ADDR 0x1BAD 773 #define MT6363_RG_LDO_VRF12_HW1_OP_CFG_ADDR 0x1BAD 774 #define MT6363_RG_LDO_VRF12_HW2_OP_CFG_ADDR 0x1BAD 775 #define MT6363_RG_LDO_VRF12_HW3_OP_CFG_ADDR 0x1BAD 776 #define MT6363_RG_LDO_VRF12_HW4_OP_CFG_ADDR 0x1BAD 777 #define MT6363_RG_LDO_VRF12_HW5_OP_CFG_ADDR 0x1BAD 778 #define MT6363_RG_LDO_VRF12_HW6_OP_CFG_ADDR 0x1BAD 779 #define MT6363_RG_LDO_VRF12_SW_OP_CFG_ADDR 0x1BAD 780 #define MT6363_RG_LDO_VRF12_RC0_OP_MODE_ADDR 0x1BAE 781 #define MT6363_RG_LDO_VRF12_RC1_OP_MODE_ADDR 0x1BAE 782 #define MT6363_RG_LDO_VRF12_RC2_OP_MODE_ADDR 0x1BAE 783 #define MT6363_RG_LDO_VRF12_RC3_OP_MODE_ADDR 0x1BAE 784 #define MT6363_RG_LDO_VRF12_RC4_OP_MODE_ADDR 0x1BAE 785 #define MT6363_RG_LDO_VRF12_RC5_OP_MODE_ADDR 0x1BAE 786 #define MT6363_RG_LDO_VRF12_RC6_OP_MODE_ADDR 0x1BAE 787 #define MT6363_RG_LDO_VRF12_RC7_OP_MODE_ADDR 0x1BAE 788 #define MT6363_RG_LDO_VRF12_RC8_OP_MODE_ADDR 0x1BAF 789 #define MT6363_RG_LDO_VRF12_RC9_OP_MODE_ADDR 0x1BAF 790 #define MT6363_RG_LDO_VRF12_RC10_OP_MODE_ADDR 0x1BAF 791 #define MT6363_RG_LDO_VRF12_RC11_OP_MODE_ADDR 0x1BAF 792 #define MT6363_RG_LDO_VRF12_RC12_OP_MODE_ADDR 0x1BAF 793 #define MT6363_RG_LDO_VRF12_RC13_OP_MODE_ADDR 0x1BAF 794 #define MT6363_RG_LDO_VRF12_HW0_OP_MODE_ADDR 0x1BB0 795 #define MT6363_RG_LDO_VRF12_HW1_OP_MODE_ADDR 0x1BB0 796 #define MT6363_RG_LDO_VRF12_HW2_OP_MODE_ADDR 0x1BB0 797 #define MT6363_RG_LDO_VRF12_HW3_OP_MODE_ADDR 0x1BB0 798 #define MT6363_RG_LDO_VRF12_HW4_OP_MODE_ADDR 0x1BB0 799 #define MT6363_RG_LDO_VRF12_HW5_OP_MODE_ADDR 0x1BB0 800 #define MT6363_RG_LDO_VRF12_HW6_OP_MODE_ADDR 0x1BB0 801 #define MT6363_RG_LDO_VRF13_ONLV_EN_ADDR 0x1BB2 802 #define MT6363_RG_LDO_VRF13_ONLV_EN_SHIFT 3 803 #define MT6363_RG_LDO_VRF13_RC0_OP_EN_ADDR 0x1BB6 804 #define MT6363_RG_LDO_VRF13_RC1_OP_EN_ADDR 0x1BB6 805 #define MT6363_RG_LDO_VRF13_RC2_OP_EN_ADDR 0x1BB6 806 #define MT6363_RG_LDO_VRF13_RC3_OP_EN_ADDR 0x1BB6 807 #define MT6363_RG_LDO_VRF13_RC4_OP_EN_ADDR 0x1BB6 808 #define MT6363_RG_LDO_VRF13_RC5_OP_EN_ADDR 0x1BB6 809 #define MT6363_RG_LDO_VRF13_RC6_OP_EN_ADDR 0x1BB6 810 #define MT6363_RG_LDO_VRF13_RC7_OP_EN_ADDR 0x1BB6 811 #define MT6363_RG_LDO_VRF13_RC8_OP_EN_ADDR 0x1BB7 812 #define MT6363_RG_LDO_VRF13_RC9_OP_EN_ADDR 0x1BB7 813 #define MT6363_RG_LDO_VRF13_RC10_OP_EN_ADDR 0x1BB7 814 #define MT6363_RG_LDO_VRF13_RC11_OP_EN_ADDR 0x1BB7 815 #define MT6363_RG_LDO_VRF13_RC12_OP_EN_ADDR 0x1BB7 816 #define MT6363_RG_LDO_VRF13_RC13_OP_EN_ADDR 0x1BB7 817 #define MT6363_RG_LDO_VRF13_HW0_OP_EN_ADDR 0x1BB8 818 #define MT6363_RG_LDO_VRF13_HW1_OP_EN_ADDR 0x1BB8 819 #define MT6363_RG_LDO_VRF13_HW2_OP_EN_ADDR 0x1BB8 820 #define MT6363_RG_LDO_VRF13_HW3_OP_EN_ADDR 0x1BB8 821 #define MT6363_RG_LDO_VRF13_HW4_OP_EN_ADDR 0x1BB8 822 #define MT6363_RG_LDO_VRF13_HW5_OP_EN_ADDR 0x1BB8 823 #define MT6363_RG_LDO_VRF13_HW6_OP_EN_ADDR 0x1BB8 824 #define MT6363_RG_LDO_VRF13_SW_OP_EN_ADDR 0x1BB8 825 #define MT6363_RG_LDO_VRF13_RC0_OP_CFG_ADDR 0x1BB9 826 #define MT6363_RG_LDO_VRF13_RC1_OP_CFG_ADDR 0x1BB9 827 #define MT6363_RG_LDO_VRF13_RC2_OP_CFG_ADDR 0x1BB9 828 #define MT6363_RG_LDO_VRF13_RC3_OP_CFG_ADDR 0x1BB9 829 #define MT6363_RG_LDO_VRF13_RC4_OP_CFG_ADDR 0x1BB9 830 #define MT6363_RG_LDO_VRF13_RC5_OP_CFG_ADDR 0x1BB9 831 #define MT6363_RG_LDO_VRF13_RC6_OP_CFG_ADDR 0x1BB9 832 #define MT6363_RG_LDO_VRF13_RC7_OP_CFG_ADDR 0x1BB9 833 #define MT6363_RG_LDO_VRF13_RC8_OP_CFG_ADDR 0x1BBA 834 #define MT6363_RG_LDO_VRF13_RC9_OP_CFG_ADDR 0x1BBA 835 #define MT6363_RG_LDO_VRF13_RC10_OP_CFG_ADDR 0x1BBA 836 #define MT6363_RG_LDO_VRF13_RC11_OP_CFG_ADDR 0x1BBA 837 #define MT6363_RG_LDO_VRF13_RC12_OP_CFG_ADDR 0x1BBA 838 #define MT6363_RG_LDO_VRF13_RC13_OP_CFG_ADDR 0x1BBA 839 #define MT6363_RG_LDO_VRF13_HW0_OP_CFG_ADDR 0x1BBB 840 #define MT6363_RG_LDO_VRF13_HW1_OP_CFG_ADDR 0x1BBB 841 #define MT6363_RG_LDO_VRF13_HW2_OP_CFG_ADDR 0x1BBB 842 #define MT6363_RG_LDO_VRF13_HW3_OP_CFG_ADDR 0x1BBB 843 #define MT6363_RG_LDO_VRF13_HW4_OP_CFG_ADDR 0x1BBB 844 #define MT6363_RG_LDO_VRF13_HW5_OP_CFG_ADDR 0x1BBB 845 #define MT6363_RG_LDO_VRF13_HW6_OP_CFG_ADDR 0x1BBB 846 #define MT6363_RG_LDO_VRF13_SW_OP_CFG_ADDR 0x1BBB 847 #define MT6363_RG_LDO_VRF13_RC0_OP_MODE_ADDR 0x1BBC 848 #define MT6363_RG_LDO_VRF13_RC1_OP_MODE_ADDR 0x1BBC 849 #define MT6363_RG_LDO_VRF13_RC2_OP_MODE_ADDR 0x1BBC 850 #define MT6363_RG_LDO_VRF13_RC3_OP_MODE_ADDR 0x1BBC 851 #define MT6363_RG_LDO_VRF13_RC4_OP_MODE_ADDR 0x1BBC 852 #define MT6363_RG_LDO_VRF13_RC5_OP_MODE_ADDR 0x1BBC 853 #define MT6363_RG_LDO_VRF13_RC6_OP_MODE_ADDR 0x1BBC 854 #define MT6363_RG_LDO_VRF13_RC7_OP_MODE_ADDR 0x1BBC 855 #define MT6363_RG_LDO_VRF13_RC8_OP_MODE_ADDR 0x1BBD 856 #define MT6363_RG_LDO_VRF13_RC9_OP_MODE_ADDR 0x1BBD 857 #define MT6363_RG_LDO_VRF13_RC10_OP_MODE_ADDR 0x1BBD 858 #define MT6363_RG_LDO_VRF13_RC11_OP_MODE_ADDR 0x1BBD 859 #define MT6363_RG_LDO_VRF13_RC12_OP_MODE_ADDR 0x1BBD 860 #define MT6363_RG_LDO_VRF13_RC13_OP_MODE_ADDR 0x1BBD 861 #define MT6363_RG_LDO_VRF13_HW0_OP_MODE_ADDR 0x1BBE 862 #define MT6363_RG_LDO_VRF13_HW1_OP_MODE_ADDR 0x1BBE 863 #define MT6363_RG_LDO_VRF13_HW2_OP_MODE_ADDR 0x1BBE 864 #define MT6363_RG_LDO_VRF13_HW3_OP_MODE_ADDR 0x1BBE 865 #define MT6363_RG_LDO_VRF13_HW4_OP_MODE_ADDR 0x1BBE 866 #define MT6363_RG_LDO_VRF13_HW5_OP_MODE_ADDR 0x1BBE 867 #define MT6363_RG_LDO_VRF13_HW6_OP_MODE_ADDR 0x1BBE 868 #define MT6363_RG_LDO_VRF18_ONLV_EN_ADDR 0x1BC0 869 #define MT6363_RG_LDO_VRF18_ONLV_EN_SHIFT 3 870 #define MT6363_RG_LDO_VRF18_RC0_OP_EN_ADDR 0x1BC4 871 #define MT6363_RG_LDO_VRF18_RC1_OP_EN_ADDR 0x1BC4 872 #define MT6363_RG_LDO_VRF18_RC2_OP_EN_ADDR 0x1BC4 873 #define MT6363_RG_LDO_VRF18_RC3_OP_EN_ADDR 0x1BC4 874 #define MT6363_RG_LDO_VRF18_RC4_OP_EN_ADDR 0x1BC4 875 #define MT6363_RG_LDO_VRF18_RC5_OP_EN_ADDR 0x1BC4 876 #define MT6363_RG_LDO_VRF18_RC6_OP_EN_ADDR 0x1BC4 877 #define MT6363_RG_LDO_VRF18_RC7_OP_EN_ADDR 0x1BC4 878 #define MT6363_RG_LDO_VRF18_RC8_OP_EN_ADDR 0x1BC5 879 #define MT6363_RG_LDO_VRF18_RC9_OP_EN_ADDR 0x1BC5 880 #define MT6363_RG_LDO_VRF18_RC10_OP_EN_ADDR 0x1BC5 881 #define MT6363_RG_LDO_VRF18_RC11_OP_EN_ADDR 0x1BC5 882 #define MT6363_RG_LDO_VRF18_RC12_OP_EN_ADDR 0x1BC5 883 #define MT6363_RG_LDO_VRF18_RC13_OP_EN_ADDR 0x1BC5 884 #define MT6363_RG_LDO_VRF18_HW0_OP_EN_ADDR 0x1BC6 885 #define MT6363_RG_LDO_VRF18_HW1_OP_EN_ADDR 0x1BC6 886 #define MT6363_RG_LDO_VRF18_HW2_OP_EN_ADDR 0x1BC6 887 #define MT6363_RG_LDO_VRF18_HW3_OP_EN_ADDR 0x1BC6 888 #define MT6363_RG_LDO_VRF18_HW4_OP_EN_ADDR 0x1BC6 889 #define MT6363_RG_LDO_VRF18_HW5_OP_EN_ADDR 0x1BC6 890 #define MT6363_RG_LDO_VRF18_HW6_OP_EN_ADDR 0x1BC6 891 #define MT6363_RG_LDO_VRF18_SW_OP_EN_ADDR 0x1BC6 892 #define MT6363_RG_LDO_VRF18_RC0_OP_CFG_ADDR 0x1BC7 893 #define MT6363_RG_LDO_VRF18_RC1_OP_CFG_ADDR 0x1BC7 894 #define MT6363_RG_LDO_VRF18_RC2_OP_CFG_ADDR 0x1BC7 895 #define MT6363_RG_LDO_VRF18_RC3_OP_CFG_ADDR 0x1BC7 896 #define MT6363_RG_LDO_VRF18_RC4_OP_CFG_ADDR 0x1BC7 897 #define MT6363_RG_LDO_VRF18_RC5_OP_CFG_ADDR 0x1BC7 898 #define MT6363_RG_LDO_VRF18_RC6_OP_CFG_ADDR 0x1BC7 899 #define MT6363_RG_LDO_VRF18_RC7_OP_CFG_ADDR 0x1BC7 900 #define MT6363_RG_LDO_VRF18_RC8_OP_CFG_ADDR 0x1BC8 901 #define MT6363_RG_LDO_VRF18_RC9_OP_CFG_ADDR 0x1BC8 902 #define MT6363_RG_LDO_VRF18_RC10_OP_CFG_ADDR 0x1BC8 903 #define MT6363_RG_LDO_VRF18_RC11_OP_CFG_ADDR 0x1BC8 904 #define MT6363_RG_LDO_VRF18_RC12_OP_CFG_ADDR 0x1BC8 905 #define MT6363_RG_LDO_VRF18_RC13_OP_CFG_ADDR 0x1BC8 906 #define MT6363_RG_LDO_VRF18_HW0_OP_CFG_ADDR 0x1BC9 907 #define MT6363_RG_LDO_VRF18_HW1_OP_CFG_ADDR 0x1BC9 908 #define MT6363_RG_LDO_VRF18_HW2_OP_CFG_ADDR 0x1BC9 909 #define MT6363_RG_LDO_VRF18_HW3_OP_CFG_ADDR 0x1BC9 910 #define MT6363_RG_LDO_VRF18_HW4_OP_CFG_ADDR 0x1BC9 911 #define MT6363_RG_LDO_VRF18_HW5_OP_CFG_ADDR 0x1BC9 912 #define MT6363_RG_LDO_VRF18_HW6_OP_CFG_ADDR 0x1BC9 913 #define MT6363_RG_LDO_VRF18_SW_OP_CFG_ADDR 0x1BC9 914 #define MT6363_RG_LDO_VRF18_RC0_OP_MODE_ADDR 0x1BCA 915 #define MT6363_RG_LDO_VRF18_RC1_OP_MODE_ADDR 0x1BCA 916 #define MT6363_RG_LDO_VRF18_RC2_OP_MODE_ADDR 0x1BCA 917 #define MT6363_RG_LDO_VRF18_RC3_OP_MODE_ADDR 0x1BCA 918 #define MT6363_RG_LDO_VRF18_RC4_OP_MODE_ADDR 0x1BCA 919 #define MT6363_RG_LDO_VRF18_RC5_OP_MODE_ADDR 0x1BCA 920 #define MT6363_RG_LDO_VRF18_RC6_OP_MODE_ADDR 0x1BCA 921 #define MT6363_RG_LDO_VRF18_RC7_OP_MODE_ADDR 0x1BCA 922 #define MT6363_RG_LDO_VRF18_RC8_OP_MODE_ADDR 0x1BCB 923 #define MT6363_RG_LDO_VRF18_RC9_OP_MODE_ADDR 0x1BCB 924 #define MT6363_RG_LDO_VRF18_RC10_OP_MODE_ADDR 0x1BCB 925 #define MT6363_RG_LDO_VRF18_RC11_OP_MODE_ADDR 0x1BCB 926 #define MT6363_RG_LDO_VRF18_RC12_OP_MODE_ADDR 0x1BCB 927 #define MT6363_RG_LDO_VRF18_RC13_OP_MODE_ADDR 0x1BCB 928 #define MT6363_RG_LDO_VRF18_HW0_OP_MODE_ADDR 0x1BCC 929 #define MT6363_RG_LDO_VRF18_HW1_OP_MODE_ADDR 0x1BCC 930 #define MT6363_RG_LDO_VRF18_HW2_OP_MODE_ADDR 0x1BCC 931 #define MT6363_RG_LDO_VRF18_HW3_OP_MODE_ADDR 0x1BCC 932 #define MT6363_RG_LDO_VRF18_HW4_OP_MODE_ADDR 0x1BCC 933 #define MT6363_RG_LDO_VRF18_HW5_OP_MODE_ADDR 0x1BCC 934 #define MT6363_RG_LDO_VRF18_HW6_OP_MODE_ADDR 0x1BCC 935 #define MT6363_RG_LDO_VRFIO18_ONLV_EN_ADDR 0x1BCE 936 #define MT6363_RG_LDO_VRFIO18_ONLV_EN_SHIFT 3 937 #define MT6363_RG_LDO_VRFIO18_RC0_OP_EN_ADDR 0x1BD2 938 #define MT6363_RG_LDO_VRFIO18_RC1_OP_EN_ADDR 0x1BD2 939 #define MT6363_RG_LDO_VRFIO18_RC2_OP_EN_ADDR 0x1BD2 940 #define MT6363_RG_LDO_VRFIO18_RC3_OP_EN_ADDR 0x1BD2 941 #define MT6363_RG_LDO_VRFIO18_RC4_OP_EN_ADDR 0x1BD2 942 #define MT6363_RG_LDO_VRFIO18_RC5_OP_EN_ADDR 0x1BD2 943 #define MT6363_RG_LDO_VRFIO18_RC6_OP_EN_ADDR 0x1BD2 944 #define MT6363_RG_LDO_VRFIO18_RC7_OP_EN_ADDR 0x1BD2 945 #define MT6363_RG_LDO_VRFIO18_RC8_OP_EN_ADDR 0x1BD3 946 #define MT6363_RG_LDO_VRFIO18_RC9_OP_EN_ADDR 0x1BD3 947 #define MT6363_RG_LDO_VRFIO18_RC10_OP_EN_ADDR 0x1BD3 948 #define MT6363_RG_LDO_VRFIO18_RC11_OP_EN_ADDR 0x1BD3 949 #define MT6363_RG_LDO_VRFIO18_RC12_OP_EN_ADDR 0x1BD3 950 #define MT6363_RG_LDO_VRFIO18_RC13_OP_EN_ADDR 0x1BD3 951 #define MT6363_RG_LDO_VRFIO18_HW0_OP_EN_ADDR 0x1BD4 952 #define MT6363_RG_LDO_VRFIO18_HW1_OP_EN_ADDR 0x1BD4 953 #define MT6363_RG_LDO_VRFIO18_HW2_OP_EN_ADDR 0x1BD4 954 #define MT6363_RG_LDO_VRFIO18_HW3_OP_EN_ADDR 0x1BD4 955 #define MT6363_RG_LDO_VRFIO18_HW4_OP_EN_ADDR 0x1BD4 956 #define MT6363_RG_LDO_VRFIO18_HW5_OP_EN_ADDR 0x1BD4 957 #define MT6363_RG_LDO_VRFIO18_HW6_OP_EN_ADDR 0x1BD4 958 #define MT6363_RG_LDO_VRFIO18_SW_OP_EN_ADDR 0x1BD4 959 #define MT6363_RG_LDO_VRFIO18_RC0_OP_CFG_ADDR 0x1BD5 960 #define MT6363_RG_LDO_VRFIO18_RC1_OP_CFG_ADDR 0x1BD5 961 #define MT6363_RG_LDO_VRFIO18_RC2_OP_CFG_ADDR 0x1BD5 962 #define MT6363_RG_LDO_VRFIO18_RC3_OP_CFG_ADDR 0x1BD5 963 #define MT6363_RG_LDO_VRFIO18_RC4_OP_CFG_ADDR 0x1BD5 964 #define MT6363_RG_LDO_VRFIO18_RC5_OP_CFG_ADDR 0x1BD5 965 #define MT6363_RG_LDO_VRFIO18_RC6_OP_CFG_ADDR 0x1BD5 966 #define MT6363_RG_LDO_VRFIO18_RC7_OP_CFG_ADDR 0x1BD5 967 #define MT6363_RG_LDO_VRFIO18_RC8_OP_CFG_ADDR 0x1BD6 968 #define MT6363_RG_LDO_VRFIO18_RC9_OP_CFG_ADDR 0x1BD6 969 #define MT6363_RG_LDO_VRFIO18_RC10_OP_CFG_ADDR 0x1BD6 970 #define MT6363_RG_LDO_VRFIO18_RC11_OP_CFG_ADDR 0x1BD6 971 #define MT6363_RG_LDO_VRFIO18_RC12_OP_CFG_ADDR 0x1BD6 972 #define MT6363_RG_LDO_VRFIO18_RC13_OP_CFG_ADDR 0x1BD6 973 #define MT6363_RG_LDO_VRFIO18_HW0_OP_CFG_ADDR 0x1BD7 974 #define MT6363_RG_LDO_VRFIO18_HW1_OP_CFG_ADDR 0x1BD7 975 #define MT6363_RG_LDO_VRFIO18_HW2_OP_CFG_ADDR 0x1BD7 976 #define MT6363_RG_LDO_VRFIO18_HW3_OP_CFG_ADDR 0x1BD7 977 #define MT6363_RG_LDO_VRFIO18_HW4_OP_CFG_ADDR 0x1BD7 978 #define MT6363_RG_LDO_VRFIO18_HW5_OP_CFG_ADDR 0x1BD7 979 #define MT6363_RG_LDO_VRFIO18_HW6_OP_CFG_ADDR 0x1BD7 980 #define MT6363_RG_LDO_VRFIO18_SW_OP_CFG_ADDR 0x1BD7 981 #define MT6363_RG_LDO_VRFIO18_RC0_OP_MODE_ADDR 0x1BD8 982 #define MT6363_RG_LDO_VRFIO18_RC1_OP_MODE_ADDR 0x1BD8 983 #define MT6363_RG_LDO_VRFIO18_RC2_OP_MODE_ADDR 0x1BD8 984 #define MT6363_RG_LDO_VRFIO18_RC3_OP_MODE_ADDR 0x1BD8 985 #define MT6363_RG_LDO_VRFIO18_RC4_OP_MODE_ADDR 0x1BD8 986 #define MT6363_RG_LDO_VRFIO18_RC5_OP_MODE_ADDR 0x1BD8 987 #define MT6363_RG_LDO_VRFIO18_RC6_OP_MODE_ADDR 0x1BD8 988 #define MT6363_RG_LDO_VRFIO18_RC7_OP_MODE_ADDR 0x1BD8 989 #define MT6363_RG_LDO_VRFIO18_RC8_OP_MODE_ADDR 0x1BD9 990 #define MT6363_RG_LDO_VRFIO18_RC9_OP_MODE_ADDR 0x1BD9 991 #define MT6363_RG_LDO_VRFIO18_RC10_OP_MODE_ADDR 0x1BD9 992 #define MT6363_RG_LDO_VRFIO18_RC11_OP_MODE_ADDR 0x1BD9 993 #define MT6363_RG_LDO_VRFIO18_RC12_OP_MODE_ADDR 0x1BD9 994 #define MT6363_RG_LDO_VRFIO18_RC13_OP_MODE_ADDR 0x1BD9 995 #define MT6363_RG_LDO_VRFIO18_HW0_OP_MODE_ADDR 0x1BDA 996 #define MT6363_RG_LDO_VRFIO18_HW1_OP_MODE_ADDR 0x1BDA 997 #define MT6363_RG_LDO_VRFIO18_HW2_OP_MODE_ADDR 0x1BDA 998 #define MT6363_RG_LDO_VRFIO18_HW3_OP_MODE_ADDR 0x1BDA 999 #define MT6363_RG_LDO_VRFIO18_HW4_OP_MODE_ADDR 0x1BDA 1000 #define MT6363_RG_LDO_VRFIO18_HW5_OP_MODE_ADDR 0x1BDA 1001 #define MT6363_RG_LDO_VRFIO18_HW6_OP_MODE_ADDR 0x1BDA 1002 #define MT6363_RG_LDO_VTREF18_ONLV_EN_ADDR 0x1C08 1003 #define MT6363_RG_LDO_VTREF18_ONLV_EN_SHIFT 3 1004 #define MT6363_RG_LDO_VTREF18_RC0_OP_EN_ADDR 0x1C0C 1005 #define MT6363_RG_LDO_VTREF18_RC1_OP_EN_ADDR 0x1C0C 1006 #define MT6363_RG_LDO_VTREF18_RC2_OP_EN_ADDR 0x1C0C 1007 #define MT6363_RG_LDO_VTREF18_RC3_OP_EN_ADDR 0x1C0C 1008 #define MT6363_RG_LDO_VTREF18_RC4_OP_EN_ADDR 0x1C0C 1009 #define MT6363_RG_LDO_VTREF18_RC5_OP_EN_ADDR 0x1C0C 1010 #define MT6363_RG_LDO_VTREF18_RC6_OP_EN_ADDR 0x1C0C 1011 #define MT6363_RG_LDO_VTREF18_RC7_OP_EN_ADDR 0x1C0C 1012 #define MT6363_RG_LDO_VTREF18_RC8_OP_EN_ADDR 0x1C0D 1013 #define MT6363_RG_LDO_VTREF18_RC9_OP_EN_ADDR 0x1C0D 1014 #define MT6363_RG_LDO_VTREF18_RC10_OP_EN_ADDR 0x1C0D 1015 #define MT6363_RG_LDO_VTREF18_RC11_OP_EN_ADDR 0x1C0D 1016 #define MT6363_RG_LDO_VTREF18_RC12_OP_EN_ADDR 0x1C0D 1017 #define MT6363_RG_LDO_VTREF18_RC13_OP_EN_ADDR 0x1C0D 1018 #define MT6363_RG_LDO_VTREF18_HW0_OP_EN_ADDR 0x1C0E 1019 #define MT6363_RG_LDO_VTREF18_HW1_OP_EN_ADDR 0x1C0E 1020 #define MT6363_RG_LDO_VTREF18_HW2_OP_EN_ADDR 0x1C0E 1021 #define MT6363_RG_LDO_VTREF18_HW3_OP_EN_ADDR 0x1C0E 1022 #define MT6363_RG_LDO_VTREF18_HW4_OP_EN_ADDR 0x1C0E 1023 #define MT6363_RG_LDO_VTREF18_HW5_OP_EN_ADDR 0x1C0E 1024 #define MT6363_RG_LDO_VTREF18_HW6_OP_EN_ADDR 0x1C0E 1025 #define MT6363_RG_LDO_VTREF18_SW_OP_EN_ADDR 0x1C0E 1026 #define MT6363_RG_LDO_VTREF18_RC0_OP_CFG_ADDR 0x1C0F 1027 #define MT6363_RG_LDO_VTREF18_RC1_OP_CFG_ADDR 0x1C0F 1028 #define MT6363_RG_LDO_VTREF18_RC2_OP_CFG_ADDR 0x1C0F 1029 #define MT6363_RG_LDO_VTREF18_RC3_OP_CFG_ADDR 0x1C0F 1030 #define MT6363_RG_LDO_VTREF18_RC4_OP_CFG_ADDR 0x1C0F 1031 #define MT6363_RG_LDO_VTREF18_RC5_OP_CFG_ADDR 0x1C0F 1032 #define MT6363_RG_LDO_VTREF18_RC6_OP_CFG_ADDR 0x1C0F 1033 #define MT6363_RG_LDO_VTREF18_RC7_OP_CFG_ADDR 0x1C0F 1034 #define MT6363_RG_LDO_VTREF18_RC8_OP_CFG_ADDR 0x1C10 1035 #define MT6363_RG_LDO_VTREF18_RC9_OP_CFG_ADDR 0x1C10 1036 #define MT6363_RG_LDO_VTREF18_RC10_OP_CFG_ADDR 0x1C10 1037 #define MT6363_RG_LDO_VTREF18_RC11_OP_CFG_ADDR 0x1C10 1038 #define MT6363_RG_LDO_VTREF18_RC12_OP_CFG_ADDR 0x1C10 1039 #define MT6363_RG_LDO_VTREF18_RC13_OP_CFG_ADDR 0x1C10 1040 #define MT6363_RG_LDO_VTREF18_HW0_OP_CFG_ADDR 0x1C11 1041 #define MT6363_RG_LDO_VTREF18_HW1_OP_CFG_ADDR 0x1C11 1042 #define MT6363_RG_LDO_VTREF18_HW2_OP_CFG_ADDR 0x1C11 1043 #define MT6363_RG_LDO_VTREF18_HW3_OP_CFG_ADDR 0x1C11 1044 #define MT6363_RG_LDO_VTREF18_HW4_OP_CFG_ADDR 0x1C11 1045 #define MT6363_RG_LDO_VTREF18_HW5_OP_CFG_ADDR 0x1C11 1046 #define MT6363_RG_LDO_VTREF18_HW6_OP_CFG_ADDR 0x1C11 1047 #define MT6363_RG_LDO_VTREF18_SW_OP_CFG_ADDR 0x1C11 1048 #define MT6363_RG_LDO_VTREF18_RC0_OP_MODE_ADDR 0x1C12 1049 #define MT6363_RG_LDO_VTREF18_RC1_OP_MODE_ADDR 0x1C12 1050 #define MT6363_RG_LDO_VTREF18_RC2_OP_MODE_ADDR 0x1C12 1051 #define MT6363_RG_LDO_VTREF18_RC3_OP_MODE_ADDR 0x1C12 1052 #define MT6363_RG_LDO_VTREF18_RC4_OP_MODE_ADDR 0x1C12 1053 #define MT6363_RG_LDO_VTREF18_RC5_OP_MODE_ADDR 0x1C12 1054 #define MT6363_RG_LDO_VTREF18_RC6_OP_MODE_ADDR 0x1C12 1055 #define MT6363_RG_LDO_VTREF18_RC7_OP_MODE_ADDR 0x1C12 1056 #define MT6363_RG_LDO_VTREF18_RC8_OP_MODE_ADDR 0x1C13 1057 #define MT6363_RG_LDO_VTREF18_RC9_OP_MODE_ADDR 0x1C13 1058 #define MT6363_RG_LDO_VTREF18_RC10_OP_MODE_ADDR 0x1C13 1059 #define MT6363_RG_LDO_VTREF18_RC11_OP_MODE_ADDR 0x1C13 1060 #define MT6363_RG_LDO_VTREF18_RC12_OP_MODE_ADDR 0x1C13 1061 #define MT6363_RG_LDO_VTREF18_RC13_OP_MODE_ADDR 0x1C13 1062 #define MT6363_RG_LDO_VTREF18_HW0_OP_MODE_ADDR 0x1C14 1063 #define MT6363_RG_LDO_VTREF18_HW1_OP_MODE_ADDR 0x1C14 1064 #define MT6363_RG_LDO_VTREF18_HW2_OP_MODE_ADDR 0x1C14 1065 #define MT6363_RG_LDO_VTREF18_HW3_OP_MODE_ADDR 0x1C14 1066 #define MT6363_RG_LDO_VTREF18_HW4_OP_MODE_ADDR 0x1C14 1067 #define MT6363_RG_LDO_VTREF18_HW5_OP_MODE_ADDR 0x1C14 1068 #define MT6363_RG_LDO_VTREF18_HW6_OP_MODE_ADDR 0x1C14 1069 #define MT6363_RG_LDO_VAUX18_ONLV_EN_ADDR 0x1C16 1070 #define MT6363_RG_LDO_VAUX18_ONLV_EN_SHIFT 3 1071 #define MT6363_RG_LDO_VAUX18_RC0_OP_EN_ADDR 0x1C1A 1072 #define MT6363_RG_LDO_VAUX18_RC1_OP_EN_ADDR 0x1C1A 1073 #define MT6363_RG_LDO_VAUX18_RC2_OP_EN_ADDR 0x1C1A 1074 #define MT6363_RG_LDO_VAUX18_RC3_OP_EN_ADDR 0x1C1A 1075 #define MT6363_RG_LDO_VAUX18_RC4_OP_EN_ADDR 0x1C1A 1076 #define MT6363_RG_LDO_VAUX18_RC5_OP_EN_ADDR 0x1C1A 1077 #define MT6363_RG_LDO_VAUX18_RC6_OP_EN_ADDR 0x1C1A 1078 #define MT6363_RG_LDO_VAUX18_RC7_OP_EN_ADDR 0x1C1A 1079 #define MT6363_RG_LDO_VAUX18_RC8_OP_EN_ADDR 0x1C1B 1080 #define MT6363_RG_LDO_VAUX18_RC9_OP_EN_ADDR 0x1C1B 1081 #define MT6363_RG_LDO_VAUX18_RC10_OP_EN_ADDR 0x1C1B 1082 #define MT6363_RG_LDO_VAUX18_RC11_OP_EN_ADDR 0x1C1B 1083 #define MT6363_RG_LDO_VAUX18_RC12_OP_EN_ADDR 0x1C1B 1084 #define MT6363_RG_LDO_VAUX18_RC13_OP_EN_ADDR 0x1C1B 1085 #define MT6363_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1C1C 1086 #define MT6363_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1C1C 1087 #define MT6363_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1C1C 1088 #define MT6363_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1C1C 1089 #define MT6363_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1C1C 1090 #define MT6363_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1C1C 1091 #define MT6363_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1C1C 1092 #define MT6363_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1C1C 1093 #define MT6363_RG_LDO_VAUX18_RC0_OP_CFG_ADDR 0x1C1D 1094 #define MT6363_RG_LDO_VAUX18_RC1_OP_CFG_ADDR 0x1C1D 1095 #define MT6363_RG_LDO_VAUX18_RC2_OP_CFG_ADDR 0x1C1D 1096 #define MT6363_RG_LDO_VAUX18_RC3_OP_CFG_ADDR 0x1C1D 1097 #define MT6363_RG_LDO_VAUX18_RC4_OP_CFG_ADDR 0x1C1D 1098 #define MT6363_RG_LDO_VAUX18_RC5_OP_CFG_ADDR 0x1C1D 1099 #define MT6363_RG_LDO_VAUX18_RC6_OP_CFG_ADDR 0x1C1D 1100 #define MT6363_RG_LDO_VAUX18_RC7_OP_CFG_ADDR 0x1C1D 1101 #define MT6363_RG_LDO_VAUX18_RC8_OP_CFG_ADDR 0x1C1E 1102 #define MT6363_RG_LDO_VAUX18_RC9_OP_CFG_ADDR 0x1C1E 1103 #define MT6363_RG_LDO_VAUX18_RC10_OP_CFG_ADDR 0x1C1E 1104 #define MT6363_RG_LDO_VAUX18_RC11_OP_CFG_ADDR 0x1C1E 1105 #define MT6363_RG_LDO_VAUX18_RC12_OP_CFG_ADDR 0x1C1E 1106 #define MT6363_RG_LDO_VAUX18_RC13_OP_CFG_ADDR 0x1C1E 1107 #define MT6363_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1C1F 1108 #define MT6363_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1C1F 1109 #define MT6363_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1C1F 1110 #define MT6363_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1C1F 1111 #define MT6363_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1C1F 1112 #define MT6363_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1C1F 1113 #define MT6363_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1C1F 1114 #define MT6363_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1C1F 1115 #define MT6363_RG_LDO_VAUX18_RC0_OP_MODE_ADDR 0x1C20 1116 #define MT6363_RG_LDO_VAUX18_RC1_OP_MODE_ADDR 0x1C20 1117 #define MT6363_RG_LDO_VAUX18_RC2_OP_MODE_ADDR 0x1C20 1118 #define MT6363_RG_LDO_VAUX18_RC3_OP_MODE_ADDR 0x1C20 1119 #define MT6363_RG_LDO_VAUX18_RC4_OP_MODE_ADDR 0x1C20 1120 #define MT6363_RG_LDO_VAUX18_RC5_OP_MODE_ADDR 0x1C20 1121 #define MT6363_RG_LDO_VAUX18_RC6_OP_MODE_ADDR 0x1C20 1122 #define MT6363_RG_LDO_VAUX18_RC7_OP_MODE_ADDR 0x1C20 1123 #define MT6363_RG_LDO_VAUX18_RC8_OP_MODE_ADDR 0x1C21 1124 #define MT6363_RG_LDO_VAUX18_RC9_OP_MODE_ADDR 0x1C21 1125 #define MT6363_RG_LDO_VAUX18_RC10_OP_MODE_ADDR 0x1C21 1126 #define MT6363_RG_LDO_VAUX18_RC11_OP_MODE_ADDR 0x1C21 1127 #define MT6363_RG_LDO_VAUX18_RC12_OP_MODE_ADDR 0x1C21 1128 #define MT6363_RG_LDO_VAUX18_RC13_OP_MODE_ADDR 0x1C21 1129 #define MT6363_RG_LDO_VAUX18_HW0_OP_MODE_ADDR 0x1C22 1130 #define MT6363_RG_LDO_VAUX18_HW1_OP_MODE_ADDR 0x1C22 1131 #define MT6363_RG_LDO_VAUX18_HW2_OP_MODE_ADDR 0x1C22 1132 #define MT6363_RG_LDO_VAUX18_HW3_OP_MODE_ADDR 0x1C22 1133 #define MT6363_RG_LDO_VAUX18_HW4_OP_MODE_ADDR 0x1C22 1134 #define MT6363_RG_LDO_VAUX18_HW5_OP_MODE_ADDR 0x1C22 1135 #define MT6363_RG_LDO_VAUX18_HW6_OP_MODE_ADDR 0x1C22 1136 #define MT6363_RG_LDO_VEMC_ONLV_EN_ADDR 0x1C24 1137 #define MT6363_RG_LDO_VEMC_ONLV_EN_SHIFT 3 1138 #define MT6363_RG_LDO_VEMC_RC0_OP_EN_ADDR 0x1C28 1139 #define MT6363_RG_LDO_VEMC_RC1_OP_EN_ADDR 0x1C28 1140 #define MT6363_RG_LDO_VEMC_RC2_OP_EN_ADDR 0x1C28 1141 #define MT6363_RG_LDO_VEMC_RC3_OP_EN_ADDR 0x1C28 1142 #define MT6363_RG_LDO_VEMC_RC4_OP_EN_ADDR 0x1C28 1143 #define MT6363_RG_LDO_VEMC_RC5_OP_EN_ADDR 0x1C28 1144 #define MT6363_RG_LDO_VEMC_RC6_OP_EN_ADDR 0x1C28 1145 #define MT6363_RG_LDO_VEMC_RC7_OP_EN_ADDR 0x1C28 1146 #define MT6363_RG_LDO_VEMC_RC8_OP_EN_ADDR 0x1C29 1147 #define MT6363_RG_LDO_VEMC_RC9_OP_EN_ADDR 0x1C29 1148 #define MT6363_RG_LDO_VEMC_RC10_OP_EN_ADDR 0x1C29 1149 #define MT6363_RG_LDO_VEMC_RC11_OP_EN_ADDR 0x1C29 1150 #define MT6363_RG_LDO_VEMC_RC12_OP_EN_ADDR 0x1C29 1151 #define MT6363_RG_LDO_VEMC_RC13_OP_EN_ADDR 0x1C29 1152 #define MT6363_RG_LDO_VEMC_HW0_OP_EN_ADDR 0x1C2A 1153 #define MT6363_RG_LDO_VEMC_HW1_OP_EN_ADDR 0x1C2A 1154 #define MT6363_RG_LDO_VEMC_HW2_OP_EN_ADDR 0x1C2A 1155 #define MT6363_RG_LDO_VEMC_HW3_OP_EN_ADDR 0x1C2A 1156 #define MT6363_RG_LDO_VEMC_HW4_OP_EN_ADDR 0x1C2A 1157 #define MT6363_RG_LDO_VEMC_HW5_OP_EN_ADDR 0x1C2A 1158 #define MT6363_RG_LDO_VEMC_HW6_OP_EN_ADDR 0x1C2A 1159 #define MT6363_RG_LDO_VEMC_SW_OP_EN_ADDR 0x1C2A 1160 #define MT6363_RG_LDO_VEMC_RC0_OP_CFG_ADDR 0x1C2B 1161 #define MT6363_RG_LDO_VEMC_RC1_OP_CFG_ADDR 0x1C2B 1162 #define MT6363_RG_LDO_VEMC_RC2_OP_CFG_ADDR 0x1C2B 1163 #define MT6363_RG_LDO_VEMC_RC3_OP_CFG_ADDR 0x1C2B 1164 #define MT6363_RG_LDO_VEMC_RC4_OP_CFG_ADDR 0x1C2B 1165 #define MT6363_RG_LDO_VEMC_RC5_OP_CFG_ADDR 0x1C2B 1166 #define MT6363_RG_LDO_VEMC_RC6_OP_CFG_ADDR 0x1C2B 1167 #define MT6363_RG_LDO_VEMC_RC7_OP_CFG_ADDR 0x1C2B 1168 #define MT6363_RG_LDO_VEMC_RC8_OP_CFG_ADDR 0x1C2C 1169 #define MT6363_RG_LDO_VEMC_RC9_OP_CFG_ADDR 0x1C2C 1170 #define MT6363_RG_LDO_VEMC_RC10_OP_CFG_ADDR 0x1C2C 1171 #define MT6363_RG_LDO_VEMC_RC11_OP_CFG_ADDR 0x1C2C 1172 #define MT6363_RG_LDO_VEMC_RC12_OP_CFG_ADDR 0x1C2C 1173 #define MT6363_RG_LDO_VEMC_RC13_OP_CFG_ADDR 0x1C2C 1174 #define MT6363_RG_LDO_VEMC_HW0_OP_CFG_ADDR 0x1C2D 1175 #define MT6363_RG_LDO_VEMC_HW1_OP_CFG_ADDR 0x1C2D 1176 #define MT6363_RG_LDO_VEMC_HW2_OP_CFG_ADDR 0x1C2D 1177 #define MT6363_RG_LDO_VEMC_HW3_OP_CFG_ADDR 0x1C2D 1178 #define MT6363_RG_LDO_VEMC_HW4_OP_CFG_ADDR 0x1C2D 1179 #define MT6363_RG_LDO_VEMC_HW5_OP_CFG_ADDR 0x1C2D 1180 #define MT6363_RG_LDO_VEMC_HW6_OP_CFG_ADDR 0x1C2D 1181 #define MT6363_RG_LDO_VEMC_SW_OP_CFG_ADDR 0x1C2D 1182 #define MT6363_RG_LDO_VEMC_RC0_OP_MODE_ADDR 0x1C2E 1183 #define MT6363_RG_LDO_VEMC_RC1_OP_MODE_ADDR 0x1C2E 1184 #define MT6363_RG_LDO_VEMC_RC2_OP_MODE_ADDR 0x1C2E 1185 #define MT6363_RG_LDO_VEMC_RC3_OP_MODE_ADDR 0x1C2E 1186 #define MT6363_RG_LDO_VEMC_RC4_OP_MODE_ADDR 0x1C2E 1187 #define MT6363_RG_LDO_VEMC_RC5_OP_MODE_ADDR 0x1C2E 1188 #define MT6363_RG_LDO_VEMC_RC6_OP_MODE_ADDR 0x1C2E 1189 #define MT6363_RG_LDO_VEMC_RC7_OP_MODE_ADDR 0x1C2E 1190 #define MT6363_RG_LDO_VEMC_RC8_OP_MODE_ADDR 0x1C2F 1191 #define MT6363_RG_LDO_VEMC_RC9_OP_MODE_ADDR 0x1C2F 1192 #define MT6363_RG_LDO_VEMC_RC10_OP_MODE_ADDR 0x1C2F 1193 #define MT6363_RG_LDO_VEMC_RC11_OP_MODE_ADDR 0x1C2F 1194 #define MT6363_RG_LDO_VEMC_RC12_OP_MODE_ADDR 0x1C2F 1195 #define MT6363_RG_LDO_VEMC_RC13_OP_MODE_ADDR 0x1C2F 1196 #define MT6363_RG_LDO_VEMC_HW0_OP_MODE_ADDR 0x1C30 1197 #define MT6363_RG_LDO_VEMC_HW1_OP_MODE_ADDR 0x1C30 1198 #define MT6363_RG_LDO_VEMC_HW2_OP_MODE_ADDR 0x1C30 1199 #define MT6363_RG_LDO_VEMC_HW3_OP_MODE_ADDR 0x1C30 1200 #define MT6363_RG_LDO_VEMC_HW4_OP_MODE_ADDR 0x1C30 1201 #define MT6363_RG_LDO_VEMC_HW5_OP_MODE_ADDR 0x1C30 1202 #define MT6363_RG_LDO_VEMC_HW6_OP_MODE_ADDR 0x1C30 1203 #define MT6363_RG_LDO_VUFS12_ONLV_EN_ADDR 0x1C32 1204 #define MT6363_RG_LDO_VUFS12_ONLV_EN_SHIFT 3 1205 #define MT6363_RG_LDO_VUFS12_RC0_OP_EN_ADDR 0x1C36 1206 #define MT6363_RG_LDO_VUFS12_RC1_OP_EN_ADDR 0x1C36 1207 #define MT6363_RG_LDO_VUFS12_RC2_OP_EN_ADDR 0x1C36 1208 #define MT6363_RG_LDO_VUFS12_RC3_OP_EN_ADDR 0x1C36 1209 #define MT6363_RG_LDO_VUFS12_RC4_OP_EN_ADDR 0x1C36 1210 #define MT6363_RG_LDO_VUFS12_RC5_OP_EN_ADDR 0x1C36 1211 #define MT6363_RG_LDO_VUFS12_RC6_OP_EN_ADDR 0x1C36 1212 #define MT6363_RG_LDO_VUFS12_RC7_OP_EN_ADDR 0x1C36 1213 #define MT6363_RG_LDO_VUFS12_RC8_OP_EN_ADDR 0x1C37 1214 #define MT6363_RG_LDO_VUFS12_RC9_OP_EN_ADDR 0x1C37 1215 #define MT6363_RG_LDO_VUFS12_RC10_OP_EN_ADDR 0x1C37 1216 #define MT6363_RG_LDO_VUFS12_RC11_OP_EN_ADDR 0x1C37 1217 #define MT6363_RG_LDO_VUFS12_RC12_OP_EN_ADDR 0x1C37 1218 #define MT6363_RG_LDO_VUFS12_RC13_OP_EN_ADDR 0x1C37 1219 #define MT6363_RG_LDO_VUFS12_HW0_OP_EN_ADDR 0x1C38 1220 #define MT6363_RG_LDO_VUFS12_HW1_OP_EN_ADDR 0x1C38 1221 #define MT6363_RG_LDO_VUFS12_HW2_OP_EN_ADDR 0x1C38 1222 #define MT6363_RG_LDO_VUFS12_HW3_OP_EN_ADDR 0x1C38 1223 #define MT6363_RG_LDO_VUFS12_HW4_OP_EN_ADDR 0x1C38 1224 #define MT6363_RG_LDO_VUFS12_HW5_OP_EN_ADDR 0x1C38 1225 #define MT6363_RG_LDO_VUFS12_HW6_OP_EN_ADDR 0x1C38 1226 #define MT6363_RG_LDO_VUFS12_SW_OP_EN_ADDR 0x1C38 1227 #define MT6363_RG_LDO_VUFS12_RC0_OP_CFG_ADDR 0x1C39 1228 #define MT6363_RG_LDO_VUFS12_RC1_OP_CFG_ADDR 0x1C39 1229 #define MT6363_RG_LDO_VUFS12_RC2_OP_CFG_ADDR 0x1C39 1230 #define MT6363_RG_LDO_VUFS12_RC3_OP_CFG_ADDR 0x1C39 1231 #define MT6363_RG_LDO_VUFS12_RC4_OP_CFG_ADDR 0x1C39 1232 #define MT6363_RG_LDO_VUFS12_RC5_OP_CFG_ADDR 0x1C39 1233 #define MT6363_RG_LDO_VUFS12_RC6_OP_CFG_ADDR 0x1C39 1234 #define MT6363_RG_LDO_VUFS12_RC7_OP_CFG_ADDR 0x1C39 1235 #define MT6363_RG_LDO_VUFS12_RC8_OP_CFG_ADDR 0x1C3A 1236 #define MT6363_RG_LDO_VUFS12_RC9_OP_CFG_ADDR 0x1C3A 1237 #define MT6363_RG_LDO_VUFS12_RC10_OP_CFG_ADDR 0x1C3A 1238 #define MT6363_RG_LDO_VUFS12_RC11_OP_CFG_ADDR 0x1C3A 1239 #define MT6363_RG_LDO_VUFS12_RC12_OP_CFG_ADDR 0x1C3A 1240 #define MT6363_RG_LDO_VUFS12_RC13_OP_CFG_ADDR 0x1C3A 1241 #define MT6363_RG_LDO_VUFS12_HW0_OP_CFG_ADDR 0x1C3B 1242 #define MT6363_RG_LDO_VUFS12_HW1_OP_CFG_ADDR 0x1C3B 1243 #define MT6363_RG_LDO_VUFS12_HW2_OP_CFG_ADDR 0x1C3B 1244 #define MT6363_RG_LDO_VUFS12_HW3_OP_CFG_ADDR 0x1C3B 1245 #define MT6363_RG_LDO_VUFS12_HW4_OP_CFG_ADDR 0x1C3B 1246 #define MT6363_RG_LDO_VUFS12_HW5_OP_CFG_ADDR 0x1C3B 1247 #define MT6363_RG_LDO_VUFS12_HW6_OP_CFG_ADDR 0x1C3B 1248 #define MT6363_RG_LDO_VUFS12_SW_OP_CFG_ADDR 0x1C3B 1249 #define MT6363_RG_LDO_VUFS12_RC0_OP_MODE_ADDR 0x1C3C 1250 #define MT6363_RG_LDO_VUFS12_RC1_OP_MODE_ADDR 0x1C3C 1251 #define MT6363_RG_LDO_VUFS12_RC2_OP_MODE_ADDR 0x1C3C 1252 #define MT6363_RG_LDO_VUFS12_RC3_OP_MODE_ADDR 0x1C3C 1253 #define MT6363_RG_LDO_VUFS12_RC4_OP_MODE_ADDR 0x1C3C 1254 #define MT6363_RG_LDO_VUFS12_RC5_OP_MODE_ADDR 0x1C3C 1255 #define MT6363_RG_LDO_VUFS12_RC6_OP_MODE_ADDR 0x1C3C 1256 #define MT6363_RG_LDO_VUFS12_RC7_OP_MODE_ADDR 0x1C3C 1257 #define MT6363_RG_LDO_VUFS12_RC8_OP_MODE_ADDR 0x1C3D 1258 #define MT6363_RG_LDO_VUFS12_RC9_OP_MODE_ADDR 0x1C3D 1259 #define MT6363_RG_LDO_VUFS12_RC10_OP_MODE_ADDR 0x1C3D 1260 #define MT6363_RG_LDO_VUFS12_RC11_OP_MODE_ADDR 0x1C3D 1261 #define MT6363_RG_LDO_VUFS12_RC12_OP_MODE_ADDR 0x1C3D 1262 #define MT6363_RG_LDO_VUFS12_RC13_OP_MODE_ADDR 0x1C3D 1263 #define MT6363_RG_LDO_VUFS12_HW0_OP_MODE_ADDR 0x1C3E 1264 #define MT6363_RG_LDO_VUFS12_HW1_OP_MODE_ADDR 0x1C3E 1265 #define MT6363_RG_LDO_VUFS12_HW2_OP_MODE_ADDR 0x1C3E 1266 #define MT6363_RG_LDO_VUFS12_HW3_OP_MODE_ADDR 0x1C3E 1267 #define MT6363_RG_LDO_VUFS12_HW4_OP_MODE_ADDR 0x1C3E 1268 #define MT6363_RG_LDO_VUFS12_HW5_OP_MODE_ADDR 0x1C3E 1269 #define MT6363_RG_LDO_VUFS12_HW6_OP_MODE_ADDR 0x1C3E 1270 #define MT6363_RG_LDO_VUFS18_ONLV_EN_ADDR 0x1C40 1271 #define MT6363_RG_LDO_VUFS18_ONLV_EN_SHIFT 3 1272 #define MT6363_RG_LDO_VUFS18_RC0_OP_EN_ADDR 0x1C44 1273 #define MT6363_RG_LDO_VUFS18_RC1_OP_EN_ADDR 0x1C44 1274 #define MT6363_RG_LDO_VUFS18_RC2_OP_EN_ADDR 0x1C44 1275 #define MT6363_RG_LDO_VUFS18_RC3_OP_EN_ADDR 0x1C44 1276 #define MT6363_RG_LDO_VUFS18_RC4_OP_EN_ADDR 0x1C44 1277 #define MT6363_RG_LDO_VUFS18_RC5_OP_EN_ADDR 0x1C44 1278 #define MT6363_RG_LDO_VUFS18_RC6_OP_EN_ADDR 0x1C44 1279 #define MT6363_RG_LDO_VUFS18_RC7_OP_EN_ADDR 0x1C44 1280 #define MT6363_RG_LDO_VUFS18_RC8_OP_EN_ADDR 0x1C45 1281 #define MT6363_RG_LDO_VUFS18_RC9_OP_EN_ADDR 0x1C45 1282 #define MT6363_RG_LDO_VUFS18_RC10_OP_EN_ADDR 0x1C45 1283 #define MT6363_RG_LDO_VUFS18_RC11_OP_EN_ADDR 0x1C45 1284 #define MT6363_RG_LDO_VUFS18_RC12_OP_EN_ADDR 0x1C45 1285 #define MT6363_RG_LDO_VUFS18_RC13_OP_EN_ADDR 0x1C45 1286 #define MT6363_RG_LDO_VUFS18_HW0_OP_EN_ADDR 0x1C46 1287 #define MT6363_RG_LDO_VUFS18_HW1_OP_EN_ADDR 0x1C46 1288 #define MT6363_RG_LDO_VUFS18_HW2_OP_EN_ADDR 0x1C46 1289 #define MT6363_RG_LDO_VUFS18_HW3_OP_EN_ADDR 0x1C46 1290 #define MT6363_RG_LDO_VUFS18_HW4_OP_EN_ADDR 0x1C46 1291 #define MT6363_RG_LDO_VUFS18_HW5_OP_EN_ADDR 0x1C46 1292 #define MT6363_RG_LDO_VUFS18_HW6_OP_EN_ADDR 0x1C46 1293 #define MT6363_RG_LDO_VUFS18_SW_OP_EN_ADDR 0x1C46 1294 #define MT6363_RG_LDO_VUFS18_RC0_OP_CFG_ADDR 0x1C47 1295 #define MT6363_RG_LDO_VUFS18_RC1_OP_CFG_ADDR 0x1C47 1296 #define MT6363_RG_LDO_VUFS18_RC2_OP_CFG_ADDR 0x1C47 1297 #define MT6363_RG_LDO_VUFS18_RC3_OP_CFG_ADDR 0x1C47 1298 #define MT6363_RG_LDO_VUFS18_RC4_OP_CFG_ADDR 0x1C47 1299 #define MT6363_RG_LDO_VUFS18_RC5_OP_CFG_ADDR 0x1C47 1300 #define MT6363_RG_LDO_VUFS18_RC6_OP_CFG_ADDR 0x1C47 1301 #define MT6363_RG_LDO_VUFS18_RC7_OP_CFG_ADDR 0x1C47 1302 #define MT6363_RG_LDO_VUFS18_RC8_OP_CFG_ADDR 0x1C48 1303 #define MT6363_RG_LDO_VUFS18_RC9_OP_CFG_ADDR 0x1C48 1304 #define MT6363_RG_LDO_VUFS18_RC10_OP_CFG_ADDR 0x1C48 1305 #define MT6363_RG_LDO_VUFS18_RC11_OP_CFG_ADDR 0x1C48 1306 #define MT6363_RG_LDO_VUFS18_RC12_OP_CFG_ADDR 0x1C48 1307 #define MT6363_RG_LDO_VUFS18_RC13_OP_CFG_ADDR 0x1C48 1308 #define MT6363_RG_LDO_VUFS18_HW0_OP_CFG_ADDR 0x1C49 1309 #define MT6363_RG_LDO_VUFS18_HW1_OP_CFG_ADDR 0x1C49 1310 #define MT6363_RG_LDO_VUFS18_HW2_OP_CFG_ADDR 0x1C49 1311 #define MT6363_RG_LDO_VUFS18_HW3_OP_CFG_ADDR 0x1C49 1312 #define MT6363_RG_LDO_VUFS18_HW4_OP_CFG_ADDR 0x1C49 1313 #define MT6363_RG_LDO_VUFS18_HW5_OP_CFG_ADDR 0x1C49 1314 #define MT6363_RG_LDO_VUFS18_HW6_OP_CFG_ADDR 0x1C49 1315 #define MT6363_RG_LDO_VUFS18_SW_OP_CFG_ADDR 0x1C49 1316 #define MT6363_RG_LDO_VUFS18_RC0_OP_MODE_ADDR 0x1C4A 1317 #define MT6363_RG_LDO_VUFS18_RC1_OP_MODE_ADDR 0x1C4A 1318 #define MT6363_RG_LDO_VUFS18_RC2_OP_MODE_ADDR 0x1C4A 1319 #define MT6363_RG_LDO_VUFS18_RC3_OP_MODE_ADDR 0x1C4A 1320 #define MT6363_RG_LDO_VUFS18_RC4_OP_MODE_ADDR 0x1C4A 1321 #define MT6363_RG_LDO_VUFS18_RC5_OP_MODE_ADDR 0x1C4A 1322 #define MT6363_RG_LDO_VUFS18_RC6_OP_MODE_ADDR 0x1C4A 1323 #define MT6363_RG_LDO_VUFS18_RC7_OP_MODE_ADDR 0x1C4A 1324 #define MT6363_RG_LDO_VUFS18_RC8_OP_MODE_ADDR 0x1C4B 1325 #define MT6363_RG_LDO_VUFS18_RC9_OP_MODE_ADDR 0x1C4B 1326 #define MT6363_RG_LDO_VUFS18_RC10_OP_MODE_ADDR 0x1C4B 1327 #define MT6363_RG_LDO_VUFS18_RC11_OP_MODE_ADDR 0x1C4B 1328 #define MT6363_RG_LDO_VUFS18_RC12_OP_MODE_ADDR 0x1C4B 1329 #define MT6363_RG_LDO_VUFS18_RC13_OP_MODE_ADDR 0x1C4B 1330 #define MT6363_RG_LDO_VUFS18_HW0_OP_MODE_ADDR 0x1C4C 1331 #define MT6363_RG_LDO_VUFS18_HW1_OP_MODE_ADDR 0x1C4C 1332 #define MT6363_RG_LDO_VUFS18_HW2_OP_MODE_ADDR 0x1C4C 1333 #define MT6363_RG_LDO_VUFS18_HW3_OP_MODE_ADDR 0x1C4C 1334 #define MT6363_RG_LDO_VUFS18_HW4_OP_MODE_ADDR 0x1C4C 1335 #define MT6363_RG_LDO_VUFS18_HW5_OP_MODE_ADDR 0x1C4C 1336 #define MT6363_RG_LDO_VUFS18_HW6_OP_MODE_ADDR 0x1C4C 1337 #define MT6363_RG_LDO_VIO18_ONLV_EN_ADDR 0x1C4E 1338 #define MT6363_RG_LDO_VIO18_ONLV_EN_SHIFT 3 1339 #define MT6363_RG_LDO_VIO18_RC0_OP_EN_ADDR 0x1C52 1340 #define MT6363_RG_LDO_VIO18_RC1_OP_EN_ADDR 0x1C52 1341 #define MT6363_RG_LDO_VIO18_RC2_OP_EN_ADDR 0x1C52 1342 #define MT6363_RG_LDO_VIO18_RC3_OP_EN_ADDR 0x1C52 1343 #define MT6363_RG_LDO_VIO18_RC4_OP_EN_ADDR 0x1C52 1344 #define MT6363_RG_LDO_VIO18_RC5_OP_EN_ADDR 0x1C52 1345 #define MT6363_RG_LDO_VIO18_RC6_OP_EN_ADDR 0x1C52 1346 #define MT6363_RG_LDO_VIO18_RC7_OP_EN_ADDR 0x1C52 1347 #define MT6363_RG_LDO_VIO18_RC8_OP_EN_ADDR 0x1C53 1348 #define MT6363_RG_LDO_VIO18_RC9_OP_EN_ADDR 0x1C53 1349 #define MT6363_RG_LDO_VIO18_RC10_OP_EN_ADDR 0x1C53 1350 #define MT6363_RG_LDO_VIO18_RC11_OP_EN_ADDR 0x1C53 1351 #define MT6363_RG_LDO_VIO18_RC12_OP_EN_ADDR 0x1C53 1352 #define MT6363_RG_LDO_VIO18_RC13_OP_EN_ADDR 0x1C53 1353 #define MT6363_RG_LDO_VIO18_HW0_OP_EN_ADDR 0x1C54 1354 #define MT6363_RG_LDO_VIO18_HW1_OP_EN_ADDR 0x1C54 1355 #define MT6363_RG_LDO_VIO18_HW2_OP_EN_ADDR 0x1C54 1356 #define MT6363_RG_LDO_VIO18_HW3_OP_EN_ADDR 0x1C54 1357 #define MT6363_RG_LDO_VIO18_HW4_OP_EN_ADDR 0x1C54 1358 #define MT6363_RG_LDO_VIO18_HW5_OP_EN_ADDR 0x1C54 1359 #define MT6363_RG_LDO_VIO18_HW6_OP_EN_ADDR 0x1C54 1360 #define MT6363_RG_LDO_VIO18_SW_OP_EN_ADDR 0x1C54 1361 #define MT6363_RG_LDO_VIO18_RC0_OP_CFG_ADDR 0x1C55 1362 #define MT6363_RG_LDO_VIO18_RC1_OP_CFG_ADDR 0x1C55 1363 #define MT6363_RG_LDO_VIO18_RC2_OP_CFG_ADDR 0x1C55 1364 #define MT6363_RG_LDO_VIO18_RC3_OP_CFG_ADDR 0x1C55 1365 #define MT6363_RG_LDO_VIO18_RC4_OP_CFG_ADDR 0x1C55 1366 #define MT6363_RG_LDO_VIO18_RC5_OP_CFG_ADDR 0x1C55 1367 #define MT6363_RG_LDO_VIO18_RC6_OP_CFG_ADDR 0x1C55 1368 #define MT6363_RG_LDO_VIO18_RC7_OP_CFG_ADDR 0x1C55 1369 #define MT6363_RG_LDO_VIO18_RC8_OP_CFG_ADDR 0x1C56 1370 #define MT6363_RG_LDO_VIO18_RC9_OP_CFG_ADDR 0x1C56 1371 #define MT6363_RG_LDO_VIO18_RC10_OP_CFG_ADDR 0x1C56 1372 #define MT6363_RG_LDO_VIO18_RC11_OP_CFG_ADDR 0x1C56 1373 #define MT6363_RG_LDO_VIO18_RC12_OP_CFG_ADDR 0x1C56 1374 #define MT6363_RG_LDO_VIO18_RC13_OP_CFG_ADDR 0x1C56 1375 #define MT6363_RG_LDO_VIO18_HW0_OP_CFG_ADDR 0x1C57 1376 #define MT6363_RG_LDO_VIO18_HW1_OP_CFG_ADDR 0x1C57 1377 #define MT6363_RG_LDO_VIO18_HW2_OP_CFG_ADDR 0x1C57 1378 #define MT6363_RG_LDO_VIO18_HW3_OP_CFG_ADDR 0x1C57 1379 #define MT6363_RG_LDO_VIO18_HW4_OP_CFG_ADDR 0x1C57 1380 #define MT6363_RG_LDO_VIO18_HW5_OP_CFG_ADDR 0x1C57 1381 #define MT6363_RG_LDO_VIO18_HW6_OP_CFG_ADDR 0x1C57 1382 #define MT6363_RG_LDO_VIO18_SW_OP_CFG_ADDR 0x1C57 1383 #define MT6363_RG_LDO_VIO18_RC0_OP_MODE_ADDR 0x1C58 1384 #define MT6363_RG_LDO_VIO18_RC1_OP_MODE_ADDR 0x1C58 1385 #define MT6363_RG_LDO_VIO18_RC2_OP_MODE_ADDR 0x1C58 1386 #define MT6363_RG_LDO_VIO18_RC3_OP_MODE_ADDR 0x1C58 1387 #define MT6363_RG_LDO_VIO18_RC4_OP_MODE_ADDR 0x1C58 1388 #define MT6363_RG_LDO_VIO18_RC5_OP_MODE_ADDR 0x1C58 1389 #define MT6363_RG_LDO_VIO18_RC6_OP_MODE_ADDR 0x1C58 1390 #define MT6363_RG_LDO_VIO18_RC7_OP_MODE_ADDR 0x1C58 1391 #define MT6363_RG_LDO_VIO18_RC8_OP_MODE_ADDR 0x1C59 1392 #define MT6363_RG_LDO_VIO18_RC9_OP_MODE_ADDR 0x1C59 1393 #define MT6363_RG_LDO_VIO18_RC10_OP_MODE_ADDR 0x1C59 1394 #define MT6363_RG_LDO_VIO18_RC11_OP_MODE_ADDR 0x1C59 1395 #define MT6363_RG_LDO_VIO18_RC12_OP_MODE_ADDR 0x1C59 1396 #define MT6363_RG_LDO_VIO18_RC13_OP_MODE_ADDR 0x1C59 1397 #define MT6363_RG_LDO_VIO18_HW0_OP_MODE_ADDR 0x1C5A 1398 #define MT6363_RG_LDO_VIO18_HW1_OP_MODE_ADDR 0x1C5A 1399 #define MT6363_RG_LDO_VIO18_HW2_OP_MODE_ADDR 0x1C5A 1400 #define MT6363_RG_LDO_VIO18_HW3_OP_MODE_ADDR 0x1C5A 1401 #define MT6363_RG_LDO_VIO18_HW4_OP_MODE_ADDR 0x1C5A 1402 #define MT6363_RG_LDO_VIO18_HW5_OP_MODE_ADDR 0x1C5A 1403 #define MT6363_RG_LDO_VIO18_HW6_OP_MODE_ADDR 0x1C5A 1404 #define MT6363_RG_LDO_VIO075_ONLV_EN_ADDR 0x1C88 1405 #define MT6363_RG_LDO_VIO075_ONLV_EN_SHIFT 3 1406 #define MT6363_RG_LDO_VIO075_RC0_OP_EN_ADDR 0x1C8C 1407 #define MT6363_RG_LDO_VIO075_RC1_OP_EN_ADDR 0x1C8C 1408 #define MT6363_RG_LDO_VIO075_RC2_OP_EN_ADDR 0x1C8C 1409 #define MT6363_RG_LDO_VIO075_RC3_OP_EN_ADDR 0x1C8C 1410 #define MT6363_RG_LDO_VIO075_RC4_OP_EN_ADDR 0x1C8C 1411 #define MT6363_RG_LDO_VIO075_RC5_OP_EN_ADDR 0x1C8C 1412 #define MT6363_RG_LDO_VIO075_RC6_OP_EN_ADDR 0x1C8C 1413 #define MT6363_RG_LDO_VIO075_RC7_OP_EN_ADDR 0x1C8C 1414 #define MT6363_RG_LDO_VIO075_RC8_OP_EN_ADDR 0x1C8D 1415 #define MT6363_RG_LDO_VIO075_RC9_OP_EN_ADDR 0x1C8D 1416 #define MT6363_RG_LDO_VIO075_RC10_OP_EN_ADDR 0x1C8D 1417 #define MT6363_RG_LDO_VIO075_RC11_OP_EN_ADDR 0x1C8D 1418 #define MT6363_RG_LDO_VIO075_RC12_OP_EN_ADDR 0x1C8D 1419 #define MT6363_RG_LDO_VIO075_RC13_OP_EN_ADDR 0x1C8D 1420 #define MT6363_RG_LDO_VIO075_HW0_OP_EN_ADDR 0x1C8E 1421 #define MT6363_RG_LDO_VIO075_HW1_OP_EN_ADDR 0x1C8E 1422 #define MT6363_RG_LDO_VIO075_HW2_OP_EN_ADDR 0x1C8E 1423 #define MT6363_RG_LDO_VIO075_HW3_OP_EN_ADDR 0x1C8E 1424 #define MT6363_RG_LDO_VIO075_HW4_OP_EN_ADDR 0x1C8E 1425 #define MT6363_RG_LDO_VIO075_HW5_OP_EN_ADDR 0x1C8E 1426 #define MT6363_RG_LDO_VIO075_HW6_OP_EN_ADDR 0x1C8E 1427 #define MT6363_RG_LDO_VIO075_SW_OP_EN_ADDR 0x1C8E 1428 #define MT6363_RG_LDO_VIO075_RC0_OP_CFG_ADDR 0x1C8F 1429 #define MT6363_RG_LDO_VIO075_RC1_OP_CFG_ADDR 0x1C8F 1430 #define MT6363_RG_LDO_VIO075_RC2_OP_CFG_ADDR 0x1C8F 1431 #define MT6363_RG_LDO_VIO075_RC3_OP_CFG_ADDR 0x1C8F 1432 #define MT6363_RG_LDO_VIO075_RC4_OP_CFG_ADDR 0x1C8F 1433 #define MT6363_RG_LDO_VIO075_RC5_OP_CFG_ADDR 0x1C8F 1434 #define MT6363_RG_LDO_VIO075_RC6_OP_CFG_ADDR 0x1C8F 1435 #define MT6363_RG_LDO_VIO075_RC7_OP_CFG_ADDR 0x1C8F 1436 #define MT6363_RG_LDO_VIO075_RC8_OP_CFG_ADDR 0x1C90 1437 #define MT6363_RG_LDO_VIO075_RC9_OP_CFG_ADDR 0x1C90 1438 #define MT6363_RG_LDO_VIO075_RC10_OP_CFG_ADDR 0x1C90 1439 #define MT6363_RG_LDO_VIO075_RC11_OP_CFG_ADDR 0x1C90 1440 #define MT6363_RG_LDO_VIO075_RC12_OP_CFG_ADDR 0x1C90 1441 #define MT6363_RG_LDO_VIO075_RC13_OP_CFG_ADDR 0x1C90 1442 #define MT6363_RG_LDO_VIO075_HW0_OP_CFG_ADDR 0x1C91 1443 #define MT6363_RG_LDO_VIO075_HW1_OP_CFG_ADDR 0x1C91 1444 #define MT6363_RG_LDO_VIO075_HW2_OP_CFG_ADDR 0x1C91 1445 #define MT6363_RG_LDO_VIO075_HW3_OP_CFG_ADDR 0x1C91 1446 #define MT6363_RG_LDO_VIO075_HW4_OP_CFG_ADDR 0x1C91 1447 #define MT6363_RG_LDO_VIO075_HW5_OP_CFG_ADDR 0x1C91 1448 #define MT6363_RG_LDO_VIO075_HW6_OP_CFG_ADDR 0x1C91 1449 #define MT6363_RG_LDO_VIO075_SW_OP_CFG_ADDR 0x1C91 1450 #define MT6363_RG_LDO_VIO075_RC0_OP_MODE_ADDR 0x1C92 1451 #define MT6363_RG_LDO_VIO075_RC1_OP_MODE_ADDR 0x1C92 1452 #define MT6363_RG_LDO_VIO075_RC2_OP_MODE_ADDR 0x1C92 1453 #define MT6363_RG_LDO_VIO075_RC3_OP_MODE_ADDR 0x1C92 1454 #define MT6363_RG_LDO_VIO075_RC4_OP_MODE_ADDR 0x1C92 1455 #define MT6363_RG_LDO_VIO075_RC5_OP_MODE_ADDR 0x1C92 1456 #define MT6363_RG_LDO_VIO075_RC6_OP_MODE_ADDR 0x1C92 1457 #define MT6363_RG_LDO_VIO075_RC7_OP_MODE_ADDR 0x1C92 1458 #define MT6363_RG_LDO_VIO075_RC8_OP_MODE_ADDR 0x1C93 1459 #define MT6363_RG_LDO_VIO075_RC9_OP_MODE_ADDR 0x1C93 1460 #define MT6363_RG_LDO_VIO075_RC10_OP_MODE_ADDR 0x1C93 1461 #define MT6363_RG_LDO_VIO075_RC11_OP_MODE_ADDR 0x1C93 1462 #define MT6363_RG_LDO_VIO075_RC12_OP_MODE_ADDR 0x1C93 1463 #define MT6363_RG_LDO_VIO075_RC13_OP_MODE_ADDR 0x1C93 1464 #define MT6363_RG_LDO_VIO075_HW0_OP_MODE_ADDR 0x1C94 1465 #define MT6363_RG_LDO_VIO075_HW1_OP_MODE_ADDR 0x1C94 1466 #define MT6363_RG_LDO_VIO075_HW2_OP_MODE_ADDR 0x1C94 1467 #define MT6363_RG_LDO_VIO075_HW3_OP_MODE_ADDR 0x1C94 1468 #define MT6363_RG_LDO_VIO075_HW4_OP_MODE_ADDR 0x1C94 1469 #define MT6363_RG_LDO_VIO075_HW5_OP_MODE_ADDR 0x1C94 1470 #define MT6363_RG_LDO_VIO075_HW6_OP_MODE_ADDR 0x1C94 1471 #define MT6363_RG_LDO_VA12_1_ONLV_EN_ADDR 0x1C96 1472 #define MT6363_RG_LDO_VA12_1_ONLV_EN_SHIFT 3 1473 #define MT6363_RG_LDO_VA12_1_RC0_OP_EN_ADDR 0x1C9A 1474 #define MT6363_RG_LDO_VA12_1_RC1_OP_EN_ADDR 0x1C9A 1475 #define MT6363_RG_LDO_VA12_1_RC2_OP_EN_ADDR 0x1C9A 1476 #define MT6363_RG_LDO_VA12_1_RC3_OP_EN_ADDR 0x1C9A 1477 #define MT6363_RG_LDO_VA12_1_RC4_OP_EN_ADDR 0x1C9A 1478 #define MT6363_RG_LDO_VA12_1_RC5_OP_EN_ADDR 0x1C9A 1479 #define MT6363_RG_LDO_VA12_1_RC6_OP_EN_ADDR 0x1C9A 1480 #define MT6363_RG_LDO_VA12_1_RC7_OP_EN_ADDR 0x1C9A 1481 #define MT6363_RG_LDO_VA12_1_RC8_OP_EN_ADDR 0x1C9B 1482 #define MT6363_RG_LDO_VA12_1_RC9_OP_EN_ADDR 0x1C9B 1483 #define MT6363_RG_LDO_VA12_1_RC10_OP_EN_ADDR 0x1C9B 1484 #define MT6363_RG_LDO_VA12_1_RC11_OP_EN_ADDR 0x1C9B 1485 #define MT6363_RG_LDO_VA12_1_RC12_OP_EN_ADDR 0x1C9B 1486 #define MT6363_RG_LDO_VA12_1_RC13_OP_EN_ADDR 0x1C9B 1487 #define MT6363_RG_LDO_VA12_1_HW0_OP_EN_ADDR 0x1C9C 1488 #define MT6363_RG_LDO_VA12_1_HW1_OP_EN_ADDR 0x1C9C 1489 #define MT6363_RG_LDO_VA12_1_HW2_OP_EN_ADDR 0x1C9C 1490 #define MT6363_RG_LDO_VA12_1_HW3_OP_EN_ADDR 0x1C9C 1491 #define MT6363_RG_LDO_VA12_1_HW4_OP_EN_ADDR 0x1C9C 1492 #define MT6363_RG_LDO_VA12_1_HW5_OP_EN_ADDR 0x1C9C 1493 #define MT6363_RG_LDO_VA12_1_HW6_OP_EN_ADDR 0x1C9C 1494 #define MT6363_RG_LDO_VA12_1_SW_OP_EN_ADDR 0x1C9C 1495 #define MT6363_RG_LDO_VA12_1_RC0_OP_CFG_ADDR 0x1C9D 1496 #define MT6363_RG_LDO_VA12_1_RC1_OP_CFG_ADDR 0x1C9D 1497 #define MT6363_RG_LDO_VA12_1_RC2_OP_CFG_ADDR 0x1C9D 1498 #define MT6363_RG_LDO_VA12_1_RC3_OP_CFG_ADDR 0x1C9D 1499 #define MT6363_RG_LDO_VA12_1_RC4_OP_CFG_ADDR 0x1C9D 1500 #define MT6363_RG_LDO_VA12_1_RC5_OP_CFG_ADDR 0x1C9D 1501 #define MT6363_RG_LDO_VA12_1_RC6_OP_CFG_ADDR 0x1C9D 1502 #define MT6363_RG_LDO_VA12_1_RC7_OP_CFG_ADDR 0x1C9D 1503 #define MT6363_RG_LDO_VA12_1_RC8_OP_CFG_ADDR 0x1C9E 1504 #define MT6363_RG_LDO_VA12_1_RC9_OP_CFG_ADDR 0x1C9E 1505 #define MT6363_RG_LDO_VA12_1_RC10_OP_CFG_ADDR 0x1C9E 1506 #define MT6363_RG_LDO_VA12_1_RC11_OP_CFG_ADDR 0x1C9E 1507 #define MT6363_RG_LDO_VA12_1_RC12_OP_CFG_ADDR 0x1C9E 1508 #define MT6363_RG_LDO_VA12_1_RC13_OP_CFG_ADDR 0x1C9E 1509 #define MT6363_RG_LDO_VA12_1_HW0_OP_CFG_ADDR 0x1C9F 1510 #define MT6363_RG_LDO_VA12_1_HW1_OP_CFG_ADDR 0x1C9F 1511 #define MT6363_RG_LDO_VA12_1_HW2_OP_CFG_ADDR 0x1C9F 1512 #define MT6363_RG_LDO_VA12_1_HW3_OP_CFG_ADDR 0x1C9F 1513 #define MT6363_RG_LDO_VA12_1_HW4_OP_CFG_ADDR 0x1C9F 1514 #define MT6363_RG_LDO_VA12_1_HW5_OP_CFG_ADDR 0x1C9F 1515 #define MT6363_RG_LDO_VA12_1_HW6_OP_CFG_ADDR 0x1C9F 1516 #define MT6363_RG_LDO_VA12_1_SW_OP_CFG_ADDR 0x1C9F 1517 #define MT6363_RG_LDO_VA12_1_RC0_OP_MODE_ADDR 0x1CA0 1518 #define MT6363_RG_LDO_VA12_1_RC1_OP_MODE_ADDR 0x1CA0 1519 #define MT6363_RG_LDO_VA12_1_RC2_OP_MODE_ADDR 0x1CA0 1520 #define MT6363_RG_LDO_VA12_1_RC3_OP_MODE_ADDR 0x1CA0 1521 #define MT6363_RG_LDO_VA12_1_RC4_OP_MODE_ADDR 0x1CA0 1522 #define MT6363_RG_LDO_VA12_1_RC5_OP_MODE_ADDR 0x1CA0 1523 #define MT6363_RG_LDO_VA12_1_RC6_OP_MODE_ADDR 0x1CA0 1524 #define MT6363_RG_LDO_VA12_1_RC7_OP_MODE_ADDR 0x1CA0 1525 #define MT6363_RG_LDO_VA12_1_RC8_OP_MODE_ADDR 0x1CA1 1526 #define MT6363_RG_LDO_VA12_1_RC9_OP_MODE_ADDR 0x1CA1 1527 #define MT6363_RG_LDO_VA12_1_RC10_OP_MODE_ADDR 0x1CA1 1528 #define MT6363_RG_LDO_VA12_1_RC11_OP_MODE_ADDR 0x1CA1 1529 #define MT6363_RG_LDO_VA12_1_RC12_OP_MODE_ADDR 0x1CA1 1530 #define MT6363_RG_LDO_VA12_1_RC13_OP_MODE_ADDR 0x1CA1 1531 #define MT6363_RG_LDO_VA12_1_HW0_OP_MODE_ADDR 0x1CA2 1532 #define MT6363_RG_LDO_VA12_1_HW1_OP_MODE_ADDR 0x1CA2 1533 #define MT6363_RG_LDO_VA12_1_HW2_OP_MODE_ADDR 0x1CA2 1534 #define MT6363_RG_LDO_VA12_1_HW3_OP_MODE_ADDR 0x1CA2 1535 #define MT6363_RG_LDO_VA12_1_HW4_OP_MODE_ADDR 0x1CA2 1536 #define MT6363_RG_LDO_VA12_1_HW5_OP_MODE_ADDR 0x1CA2 1537 #define MT6363_RG_LDO_VA12_1_HW6_OP_MODE_ADDR 0x1CA2 1538 #define MT6363_RG_LDO_VA12_2_ONLV_EN_ADDR 0x1CA4 1539 #define MT6363_RG_LDO_VA12_2_ONLV_EN_SHIFT 3 1540 #define MT6363_RG_LDO_VA12_2_RC0_OP_EN_ADDR 0x1CA8 1541 #define MT6363_RG_LDO_VA12_2_RC1_OP_EN_ADDR 0x1CA8 1542 #define MT6363_RG_LDO_VA12_2_RC2_OP_EN_ADDR 0x1CA8 1543 #define MT6363_RG_LDO_VA12_2_RC3_OP_EN_ADDR 0x1CA8 1544 #define MT6363_RG_LDO_VA12_2_RC4_OP_EN_ADDR 0x1CA8 1545 #define MT6363_RG_LDO_VA12_2_RC5_OP_EN_ADDR 0x1CA8 1546 #define MT6363_RG_LDO_VA12_2_RC6_OP_EN_ADDR 0x1CA8 1547 #define MT6363_RG_LDO_VA12_2_RC7_OP_EN_ADDR 0x1CA8 1548 #define MT6363_RG_LDO_VA12_2_RC8_OP_EN_ADDR 0x1CA9 1549 #define MT6363_RG_LDO_VA12_2_RC9_OP_EN_ADDR 0x1CA9 1550 #define MT6363_RG_LDO_VA12_2_RC10_OP_EN_ADDR 0x1CA9 1551 #define MT6363_RG_LDO_VA12_2_RC11_OP_EN_ADDR 0x1CA9 1552 #define MT6363_RG_LDO_VA12_2_RC12_OP_EN_ADDR 0x1CA9 1553 #define MT6363_RG_LDO_VA12_2_RC13_OP_EN_ADDR 0x1CA9 1554 #define MT6363_RG_LDO_VA12_2_HW0_OP_EN_ADDR 0x1CAA 1555 #define MT6363_RG_LDO_VA12_2_HW1_OP_EN_ADDR 0x1CAA 1556 #define MT6363_RG_LDO_VA12_2_HW2_OP_EN_ADDR 0x1CAA 1557 #define MT6363_RG_LDO_VA12_2_HW3_OP_EN_ADDR 0x1CAA 1558 #define MT6363_RG_LDO_VA12_2_HW4_OP_EN_ADDR 0x1CAA 1559 #define MT6363_RG_LDO_VA12_2_HW5_OP_EN_ADDR 0x1CAA 1560 #define MT6363_RG_LDO_VA12_2_HW6_OP_EN_ADDR 0x1CAA 1561 #define MT6363_RG_LDO_VA12_2_SW_OP_EN_ADDR 0x1CAA 1562 #define MT6363_RG_LDO_VA12_2_RC0_OP_CFG_ADDR 0x1CAB 1563 #define MT6363_RG_LDO_VA12_2_RC1_OP_CFG_ADDR 0x1CAB 1564 #define MT6363_RG_LDO_VA12_2_RC2_OP_CFG_ADDR 0x1CAB 1565 #define MT6363_RG_LDO_VA12_2_RC3_OP_CFG_ADDR 0x1CAB 1566 #define MT6363_RG_LDO_VA12_2_RC4_OP_CFG_ADDR 0x1CAB 1567 #define MT6363_RG_LDO_VA12_2_RC5_OP_CFG_ADDR 0x1CAB 1568 #define MT6363_RG_LDO_VA12_2_RC6_OP_CFG_ADDR 0x1CAB 1569 #define MT6363_RG_LDO_VA12_2_RC7_OP_CFG_ADDR 0x1CAB 1570 #define MT6363_RG_LDO_VA12_2_RC8_OP_CFG_ADDR 0x1CAC 1571 #define MT6363_RG_LDO_VA12_2_RC9_OP_CFG_ADDR 0x1CAC 1572 #define MT6363_RG_LDO_VA12_2_RC10_OP_CFG_ADDR 0x1CAC 1573 #define MT6363_RG_LDO_VA12_2_RC11_OP_CFG_ADDR 0x1CAC 1574 #define MT6363_RG_LDO_VA12_2_RC12_OP_CFG_ADDR 0x1CAC 1575 #define MT6363_RG_LDO_VA12_2_RC13_OP_CFG_ADDR 0x1CAC 1576 #define MT6363_RG_LDO_VA12_2_HW0_OP_CFG_ADDR 0x1CAD 1577 #define MT6363_RG_LDO_VA12_2_HW1_OP_CFG_ADDR 0x1CAD 1578 #define MT6363_RG_LDO_VA12_2_HW2_OP_CFG_ADDR 0x1CAD 1579 #define MT6363_RG_LDO_VA12_2_HW3_OP_CFG_ADDR 0x1CAD 1580 #define MT6363_RG_LDO_VA12_2_HW4_OP_CFG_ADDR 0x1CAD 1581 #define MT6363_RG_LDO_VA12_2_HW5_OP_CFG_ADDR 0x1CAD 1582 #define MT6363_RG_LDO_VA12_2_HW6_OP_CFG_ADDR 0x1CAD 1583 #define MT6363_RG_LDO_VA12_2_SW_OP_CFG_ADDR 0x1CAD 1584 #define MT6363_RG_LDO_VA12_2_RC0_OP_MODE_ADDR 0x1CAE 1585 #define MT6363_RG_LDO_VA12_2_RC1_OP_MODE_ADDR 0x1CAE 1586 #define MT6363_RG_LDO_VA12_2_RC2_OP_MODE_ADDR 0x1CAE 1587 #define MT6363_RG_LDO_VA12_2_RC3_OP_MODE_ADDR 0x1CAE 1588 #define MT6363_RG_LDO_VA12_2_RC4_OP_MODE_ADDR 0x1CAE 1589 #define MT6363_RG_LDO_VA12_2_RC5_OP_MODE_ADDR 0x1CAE 1590 #define MT6363_RG_LDO_VA12_2_RC6_OP_MODE_ADDR 0x1CAE 1591 #define MT6363_RG_LDO_VA12_2_RC7_OP_MODE_ADDR 0x1CAE 1592 #define MT6363_RG_LDO_VA12_2_RC8_OP_MODE_ADDR 0x1CAF 1593 #define MT6363_RG_LDO_VA12_2_RC9_OP_MODE_ADDR 0x1CAF 1594 #define MT6363_RG_LDO_VA12_2_RC10_OP_MODE_ADDR 0x1CAF 1595 #define MT6363_RG_LDO_VA12_2_RC11_OP_MODE_ADDR 0x1CAF 1596 #define MT6363_RG_LDO_VA12_2_RC12_OP_MODE_ADDR 0x1CAF 1597 #define MT6363_RG_LDO_VA12_2_RC13_OP_MODE_ADDR 0x1CAF 1598 #define MT6363_RG_LDO_VA12_2_HW0_OP_MODE_ADDR 0x1CB0 1599 #define MT6363_RG_LDO_VA12_2_HW1_OP_MODE_ADDR 0x1CB0 1600 #define MT6363_RG_LDO_VA12_2_HW2_OP_MODE_ADDR 0x1CB0 1601 #define MT6363_RG_LDO_VA12_2_HW3_OP_MODE_ADDR 0x1CB0 1602 #define MT6363_RG_LDO_VA12_2_HW4_OP_MODE_ADDR 0x1CB0 1603 #define MT6363_RG_LDO_VA12_2_HW5_OP_MODE_ADDR 0x1CB0 1604 #define MT6363_RG_LDO_VA12_2_HW6_OP_MODE_ADDR 0x1CB0 1605 #define MT6363_RG_LDO_VA15_ONLV_EN_ADDR 0x1CB2 1606 #define MT6363_RG_LDO_VA15_ONLV_EN_SHIFT 3 1607 #define MT6363_RG_LDO_VA15_RC0_OP_EN_ADDR 0x1CB6 1608 #define MT6363_RG_LDO_VA15_RC1_OP_EN_ADDR 0x1CB6 1609 #define MT6363_RG_LDO_VA15_RC2_OP_EN_ADDR 0x1CB6 1610 #define MT6363_RG_LDO_VA15_RC3_OP_EN_ADDR 0x1CB6 1611 #define MT6363_RG_LDO_VA15_RC4_OP_EN_ADDR 0x1CB6 1612 #define MT6363_RG_LDO_VA15_RC5_OP_EN_ADDR 0x1CB6 1613 #define MT6363_RG_LDO_VA15_RC6_OP_EN_ADDR 0x1CB6 1614 #define MT6363_RG_LDO_VA15_RC7_OP_EN_ADDR 0x1CB6 1615 #define MT6363_RG_LDO_VA15_RC8_OP_EN_ADDR 0x1CB7 1616 #define MT6363_RG_LDO_VA15_RC9_OP_EN_ADDR 0x1CB7 1617 #define MT6363_RG_LDO_VA15_RC10_OP_EN_ADDR 0x1CB7 1618 #define MT6363_RG_LDO_VA15_RC11_OP_EN_ADDR 0x1CB7 1619 #define MT6363_RG_LDO_VA15_RC12_OP_EN_ADDR 0x1CB7 1620 #define MT6363_RG_LDO_VA15_RC13_OP_EN_ADDR 0x1CB7 1621 #define MT6363_RG_LDO_VA15_HW0_OP_EN_ADDR 0x1CB8 1622 #define MT6363_RG_LDO_VA15_HW1_OP_EN_ADDR 0x1CB8 1623 #define MT6363_RG_LDO_VA15_HW2_OP_EN_ADDR 0x1CB8 1624 #define MT6363_RG_LDO_VA15_HW3_OP_EN_ADDR 0x1CB8 1625 #define MT6363_RG_LDO_VA15_HW4_OP_EN_ADDR 0x1CB8 1626 #define MT6363_RG_LDO_VA15_HW5_OP_EN_ADDR 0x1CB8 1627 #define MT6363_RG_LDO_VA15_HW6_OP_EN_ADDR 0x1CB8 1628 #define MT6363_RG_LDO_VA15_SW_OP_EN_ADDR 0x1CB8 1629 #define MT6363_RG_LDO_VA15_RC0_OP_CFG_ADDR 0x1CB9 1630 #define MT6363_RG_LDO_VA15_RC1_OP_CFG_ADDR 0x1CB9 1631 #define MT6363_RG_LDO_VA15_RC2_OP_CFG_ADDR 0x1CB9 1632 #define MT6363_RG_LDO_VA15_RC3_OP_CFG_ADDR 0x1CB9 1633 #define MT6363_RG_LDO_VA15_RC4_OP_CFG_ADDR 0x1CB9 1634 #define MT6363_RG_LDO_VA15_RC5_OP_CFG_ADDR 0x1CB9 1635 #define MT6363_RG_LDO_VA15_RC6_OP_CFG_ADDR 0x1CB9 1636 #define MT6363_RG_LDO_VA15_RC7_OP_CFG_ADDR 0x1CB9 1637 #define MT6363_RG_LDO_VA15_RC8_OP_CFG_ADDR 0x1CBA 1638 #define MT6363_RG_LDO_VA15_RC9_OP_CFG_ADDR 0x1CBA 1639 #define MT6363_RG_LDO_VA15_RC10_OP_CFG_ADDR 0x1CBA 1640 #define MT6363_RG_LDO_VA15_RC11_OP_CFG_ADDR 0x1CBA 1641 #define MT6363_RG_LDO_VA15_RC12_OP_CFG_ADDR 0x1CBA 1642 #define MT6363_RG_LDO_VA15_RC13_OP_CFG_ADDR 0x1CBA 1643 #define MT6363_RG_LDO_VA15_HW0_OP_CFG_ADDR 0x1CBB 1644 #define MT6363_RG_LDO_VA15_HW1_OP_CFG_ADDR 0x1CBB 1645 #define MT6363_RG_LDO_VA15_HW2_OP_CFG_ADDR 0x1CBB 1646 #define MT6363_RG_LDO_VA15_HW3_OP_CFG_ADDR 0x1CBB 1647 #define MT6363_RG_LDO_VA15_HW4_OP_CFG_ADDR 0x1CBB 1648 #define MT6363_RG_LDO_VA15_HW5_OP_CFG_ADDR 0x1CBB 1649 #define MT6363_RG_LDO_VA15_HW6_OP_CFG_ADDR 0x1CBB 1650 #define MT6363_RG_LDO_VA15_SW_OP_CFG_ADDR 0x1CBB 1651 #define MT6363_RG_LDO_VA15_RC0_OP_MODE_ADDR 0x1CBC 1652 #define MT6363_RG_LDO_VA15_RC1_OP_MODE_ADDR 0x1CBC 1653 #define MT6363_RG_LDO_VA15_RC2_OP_MODE_ADDR 0x1CBC 1654 #define MT6363_RG_LDO_VA15_RC3_OP_MODE_ADDR 0x1CBC 1655 #define MT6363_RG_LDO_VA15_RC4_OP_MODE_ADDR 0x1CBC 1656 #define MT6363_RG_LDO_VA15_RC5_OP_MODE_ADDR 0x1CBC 1657 #define MT6363_RG_LDO_VA15_RC6_OP_MODE_ADDR 0x1CBC 1658 #define MT6363_RG_LDO_VA15_RC7_OP_MODE_ADDR 0x1CBC 1659 #define MT6363_RG_LDO_VA15_RC8_OP_MODE_ADDR 0x1CBD 1660 #define MT6363_RG_LDO_VA15_RC9_OP_MODE_ADDR 0x1CBD 1661 #define MT6363_RG_LDO_VA15_RC10_OP_MODE_ADDR 0x1CBD 1662 #define MT6363_RG_LDO_VA15_RC11_OP_MODE_ADDR 0x1CBD 1663 #define MT6363_RG_LDO_VA15_RC12_OP_MODE_ADDR 0x1CBD 1664 #define MT6363_RG_LDO_VA15_RC13_OP_MODE_ADDR 0x1CBD 1665 #define MT6363_RG_LDO_VA15_HW0_OP_MODE_ADDR 0x1CBE 1666 #define MT6363_RG_LDO_VA15_HW1_OP_MODE_ADDR 0x1CBE 1667 #define MT6363_RG_LDO_VA15_HW2_OP_MODE_ADDR 0x1CBE 1668 #define MT6363_RG_LDO_VA15_HW3_OP_MODE_ADDR 0x1CBE 1669 #define MT6363_RG_LDO_VA15_HW4_OP_MODE_ADDR 0x1CBE 1670 #define MT6363_RG_LDO_VA15_HW5_OP_MODE_ADDR 0x1CBE 1671 #define MT6363_RG_LDO_VA15_HW6_OP_MODE_ADDR 0x1CBE 1672 #define MT6363_RG_LDO_VM18_ONLV_EN_ADDR 0x1CC0 1673 #define MT6363_RG_LDO_VM18_ONLV_EN_SHIFT 3 1674 #define MT6363_RG_LDO_VM18_RC0_OP_EN_ADDR 0x1CC4 1675 #define MT6363_RG_LDO_VM18_RC1_OP_EN_ADDR 0x1CC4 1676 #define MT6363_RG_LDO_VM18_RC2_OP_EN_ADDR 0x1CC4 1677 #define MT6363_RG_LDO_VM18_RC3_OP_EN_ADDR 0x1CC4 1678 #define MT6363_RG_LDO_VM18_RC4_OP_EN_ADDR 0x1CC4 1679 #define MT6363_RG_LDO_VM18_RC5_OP_EN_ADDR 0x1CC4 1680 #define MT6363_RG_LDO_VM18_RC6_OP_EN_ADDR 0x1CC4 1681 #define MT6363_RG_LDO_VM18_RC7_OP_EN_ADDR 0x1CC4 1682 #define MT6363_RG_LDO_VM18_RC8_OP_EN_ADDR 0x1CC5 1683 #define MT6363_RG_LDO_VM18_RC9_OP_EN_ADDR 0x1CC5 1684 #define MT6363_RG_LDO_VM18_RC10_OP_EN_ADDR 0x1CC5 1685 #define MT6363_RG_LDO_VM18_RC11_OP_EN_ADDR 0x1CC5 1686 #define MT6363_RG_LDO_VM18_RC12_OP_EN_ADDR 0x1CC5 1687 #define MT6363_RG_LDO_VM18_RC13_OP_EN_ADDR 0x1CC5 1688 #define MT6363_RG_LDO_VM18_HW0_OP_EN_ADDR 0x1CC6 1689 #define MT6363_RG_LDO_VM18_HW1_OP_EN_ADDR 0x1CC6 1690 #define MT6363_RG_LDO_VM18_HW2_OP_EN_ADDR 0x1CC6 1691 #define MT6363_RG_LDO_VM18_HW3_OP_EN_ADDR 0x1CC6 1692 #define MT6363_RG_LDO_VM18_HW4_OP_EN_ADDR 0x1CC6 1693 #define MT6363_RG_LDO_VM18_HW5_OP_EN_ADDR 0x1CC6 1694 #define MT6363_RG_LDO_VM18_HW6_OP_EN_ADDR 0x1CC6 1695 #define MT6363_RG_LDO_VM18_SW_OP_EN_ADDR 0x1CC6 1696 #define MT6363_RG_LDO_VM18_RC0_OP_CFG_ADDR 0x1CC7 1697 #define MT6363_RG_LDO_VM18_RC1_OP_CFG_ADDR 0x1CC7 1698 #define MT6363_RG_LDO_VM18_RC2_OP_CFG_ADDR 0x1CC7 1699 #define MT6363_RG_LDO_VM18_RC3_OP_CFG_ADDR 0x1CC7 1700 #define MT6363_RG_LDO_VM18_RC4_OP_CFG_ADDR 0x1CC7 1701 #define MT6363_RG_LDO_VM18_RC5_OP_CFG_ADDR 0x1CC7 1702 #define MT6363_RG_LDO_VM18_RC6_OP_CFG_ADDR 0x1CC7 1703 #define MT6363_RG_LDO_VM18_RC7_OP_CFG_ADDR 0x1CC7 1704 #define MT6363_RG_LDO_VM18_RC8_OP_CFG_ADDR 0x1CC8 1705 #define MT6363_RG_LDO_VM18_RC9_OP_CFG_ADDR 0x1CC8 1706 #define MT6363_RG_LDO_VM18_RC10_OP_CFG_ADDR 0x1CC8 1707 #define MT6363_RG_LDO_VM18_RC11_OP_CFG_ADDR 0x1CC8 1708 #define MT6363_RG_LDO_VM18_RC12_OP_CFG_ADDR 0x1CC8 1709 #define MT6363_RG_LDO_VM18_RC13_OP_CFG_ADDR 0x1CC8 1710 #define MT6363_RG_LDO_VM18_HW0_OP_CFG_ADDR 0x1CC9 1711 #define MT6363_RG_LDO_VM18_HW1_OP_CFG_ADDR 0x1CC9 1712 #define MT6363_RG_LDO_VM18_HW2_OP_CFG_ADDR 0x1CC9 1713 #define MT6363_RG_LDO_VM18_HW3_OP_CFG_ADDR 0x1CC9 1714 #define MT6363_RG_LDO_VM18_HW4_OP_CFG_ADDR 0x1CC9 1715 #define MT6363_RG_LDO_VM18_HW5_OP_CFG_ADDR 0x1CC9 1716 #define MT6363_RG_LDO_VM18_HW6_OP_CFG_ADDR 0x1CC9 1717 #define MT6363_RG_LDO_VM18_SW_OP_CFG_ADDR 0x1CC9 1718 #define MT6363_RG_LDO_VM18_RC0_OP_MODE_ADDR 0x1CCA 1719 #define MT6363_RG_LDO_VM18_RC1_OP_MODE_ADDR 0x1CCA 1720 #define MT6363_RG_LDO_VM18_RC2_OP_MODE_ADDR 0x1CCA 1721 #define MT6363_RG_LDO_VM18_RC3_OP_MODE_ADDR 0x1CCA 1722 #define MT6363_RG_LDO_VM18_RC4_OP_MODE_ADDR 0x1CCA 1723 #define MT6363_RG_LDO_VM18_RC5_OP_MODE_ADDR 0x1CCA 1724 #define MT6363_RG_LDO_VM18_RC6_OP_MODE_ADDR 0x1CCA 1725 #define MT6363_RG_LDO_VM18_RC7_OP_MODE_ADDR 0x1CCA 1726 #define MT6363_RG_LDO_VM18_RC8_OP_MODE_ADDR 0x1CCB 1727 #define MT6363_RG_LDO_VM18_RC9_OP_MODE_ADDR 0x1CCB 1728 #define MT6363_RG_LDO_VM18_RC10_OP_MODE_ADDR 0x1CCB 1729 #define MT6363_RG_LDO_VM18_RC11_OP_MODE_ADDR 0x1CCB 1730 #define MT6363_RG_LDO_VM18_RC12_OP_MODE_ADDR 0x1CCB 1731 #define MT6363_RG_LDO_VM18_RC13_OP_MODE_ADDR 0x1CCB 1732 #define MT6363_RG_LDO_VM18_HW0_OP_MODE_ADDR 0x1CCC 1733 #define MT6363_RG_LDO_VM18_HW1_OP_MODE_ADDR 0x1CCC 1734 #define MT6363_RG_LDO_VM18_HW2_OP_MODE_ADDR 0x1CCC 1735 #define MT6363_RG_LDO_VM18_HW3_OP_MODE_ADDR 0x1CCC 1736 #define MT6363_RG_LDO_VM18_HW4_OP_MODE_ADDR 0x1CCC 1737 #define MT6363_RG_LDO_VM18_HW5_OP_MODE_ADDR 0x1CCC 1738 #define MT6363_RG_LDO_VM18_HW6_OP_MODE_ADDR 0x1CCC 1739 #define MT6363_RG_LDO_VCN13_ONLV_EN_ADDR 0x1D08 1740 #define MT6363_RG_LDO_VCN13_ONLV_EN_SHIFT 3 1741 #define MT6363_RG_LDO_VCN13_VOSEL_SLEEP_ADDR 0x1D0D 1742 #define MT6363_RG_LDO_VCN13_RC0_OP_EN_ADDR 0x1D14 1743 #define MT6363_RG_LDO_VCN13_RC1_OP_EN_ADDR 0x1D14 1744 #define MT6363_RG_LDO_VCN13_RC2_OP_EN_ADDR 0x1D14 1745 #define MT6363_RG_LDO_VCN13_RC3_OP_EN_ADDR 0x1D14 1746 #define MT6363_RG_LDO_VCN13_RC4_OP_EN_ADDR 0x1D14 1747 #define MT6363_RG_LDO_VCN13_RC5_OP_EN_ADDR 0x1D14 1748 #define MT6363_RG_LDO_VCN13_RC6_OP_EN_ADDR 0x1D14 1749 #define MT6363_RG_LDO_VCN13_RC7_OP_EN_ADDR 0x1D14 1750 #define MT6363_RG_LDO_VCN13_RC8_OP_EN_ADDR 0x1D15 1751 #define MT6363_RG_LDO_VCN13_RC9_OP_EN_ADDR 0x1D15 1752 #define MT6363_RG_LDO_VCN13_RC10_OP_EN_ADDR 0x1D15 1753 #define MT6363_RG_LDO_VCN13_RC11_OP_EN_ADDR 0x1D15 1754 #define MT6363_RG_LDO_VCN13_RC12_OP_EN_ADDR 0x1D15 1755 #define MT6363_RG_LDO_VCN13_RC13_OP_EN_ADDR 0x1D15 1756 #define MT6363_RG_LDO_VCN13_HW0_OP_EN_ADDR 0x1D16 1757 #define MT6363_RG_LDO_VCN13_HW1_OP_EN_ADDR 0x1D16 1758 #define MT6363_RG_LDO_VCN13_HW2_OP_EN_ADDR 0x1D16 1759 #define MT6363_RG_LDO_VCN13_HW3_OP_EN_ADDR 0x1D16 1760 #define MT6363_RG_LDO_VCN13_HW4_OP_EN_ADDR 0x1D16 1761 #define MT6363_RG_LDO_VCN13_HW5_OP_EN_ADDR 0x1D16 1762 #define MT6363_RG_LDO_VCN13_HW6_OP_EN_ADDR 0x1D16 1763 #define MT6363_RG_LDO_VCN13_SW_OP_EN_ADDR 0x1D16 1764 #define MT6363_RG_LDO_VCN13_RC0_OP_CFG_ADDR 0x1D17 1765 #define MT6363_RG_LDO_VCN13_RC1_OP_CFG_ADDR 0x1D17 1766 #define MT6363_RG_LDO_VCN13_RC2_OP_CFG_ADDR 0x1D17 1767 #define MT6363_RG_LDO_VCN13_RC3_OP_CFG_ADDR 0x1D17 1768 #define MT6363_RG_LDO_VCN13_RC4_OP_CFG_ADDR 0x1D17 1769 #define MT6363_RG_LDO_VCN13_RC5_OP_CFG_ADDR 0x1D17 1770 #define MT6363_RG_LDO_VCN13_RC6_OP_CFG_ADDR 0x1D17 1771 #define MT6363_RG_LDO_VCN13_RC7_OP_CFG_ADDR 0x1D17 1772 #define MT6363_RG_LDO_VCN13_RC8_OP_CFG_ADDR 0x1D18 1773 #define MT6363_RG_LDO_VCN13_RC9_OP_CFG_ADDR 0x1D18 1774 #define MT6363_RG_LDO_VCN13_RC10_OP_CFG_ADDR 0x1D18 1775 #define MT6363_RG_LDO_VCN13_RC11_OP_CFG_ADDR 0x1D18 1776 #define MT6363_RG_LDO_VCN13_RC12_OP_CFG_ADDR 0x1D18 1777 #define MT6363_RG_LDO_VCN13_RC13_OP_CFG_ADDR 0x1D18 1778 #define MT6363_RG_LDO_VCN13_HW0_OP_CFG_ADDR 0x1D19 1779 #define MT6363_RG_LDO_VCN13_HW1_OP_CFG_ADDR 0x1D19 1780 #define MT6363_RG_LDO_VCN13_HW2_OP_CFG_ADDR 0x1D19 1781 #define MT6363_RG_LDO_VCN13_HW3_OP_CFG_ADDR 0x1D19 1782 #define MT6363_RG_LDO_VCN13_HW4_OP_CFG_ADDR 0x1D19 1783 #define MT6363_RG_LDO_VCN13_HW5_OP_CFG_ADDR 0x1D19 1784 #define MT6363_RG_LDO_VCN13_HW6_OP_CFG_ADDR 0x1D19 1785 #define MT6363_RG_LDO_VCN13_SW_OP_CFG_ADDR 0x1D19 1786 #define MT6363_RG_LDO_VCN13_RC0_OP_MODE_ADDR 0x1D1A 1787 #define MT6363_RG_LDO_VCN13_RC1_OP_MODE_ADDR 0x1D1A 1788 #define MT6363_RG_LDO_VCN13_RC2_OP_MODE_ADDR 0x1D1A 1789 #define MT6363_RG_LDO_VCN13_RC3_OP_MODE_ADDR 0x1D1A 1790 #define MT6363_RG_LDO_VCN13_RC4_OP_MODE_ADDR 0x1D1A 1791 #define MT6363_RG_LDO_VCN13_RC5_OP_MODE_ADDR 0x1D1A 1792 #define MT6363_RG_LDO_VCN13_RC6_OP_MODE_ADDR 0x1D1A 1793 #define MT6363_RG_LDO_VCN13_RC7_OP_MODE_ADDR 0x1D1A 1794 #define MT6363_RG_LDO_VCN13_RC8_OP_MODE_ADDR 0x1D1B 1795 #define MT6363_RG_LDO_VCN13_RC9_OP_MODE_ADDR 0x1D1B 1796 #define MT6363_RG_LDO_VCN13_RC10_OP_MODE_ADDR 0x1D1B 1797 #define MT6363_RG_LDO_VCN13_RC11_OP_MODE_ADDR 0x1D1B 1798 #define MT6363_RG_LDO_VCN13_RC12_OP_MODE_ADDR 0x1D1B 1799 #define MT6363_RG_LDO_VCN13_RC13_OP_MODE_ADDR 0x1D1B 1800 #define MT6363_RG_LDO_VCN13_HW0_OP_MODE_ADDR 0x1D1C 1801 #define MT6363_RG_LDO_VCN13_HW1_OP_MODE_ADDR 0x1D1C 1802 #define MT6363_RG_LDO_VCN13_HW2_OP_MODE_ADDR 0x1D1C 1803 #define MT6363_RG_LDO_VCN13_HW3_OP_MODE_ADDR 0x1D1C 1804 #define MT6363_RG_LDO_VCN13_HW4_OP_MODE_ADDR 0x1D1C 1805 #define MT6363_RG_LDO_VCN13_HW5_OP_MODE_ADDR 0x1D1C 1806 #define MT6363_RG_LDO_VCN13_HW6_OP_MODE_ADDR 0x1D1C 1807 #define MT6363_RG_LDO_VSRAM_DIGRF_ONLV_EN_ADDR 0x1D1E 1808 #define MT6363_RG_LDO_VSRAM_DIGRF_ONLV_EN_SHIFT 3 1809 #define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_SLEEP_ADDR 0x1D23 1810 #define MT6363_RG_LDO_VSRAM_DIGRF_RC0_OP_EN_ADDR 0x1D2A 1811 #define MT6363_RG_LDO_VSRAM_DIGRF_RC1_OP_EN_ADDR 0x1D2A 1812 #define MT6363_RG_LDO_VSRAM_DIGRF_RC2_OP_EN_ADDR 0x1D2A 1813 #define MT6363_RG_LDO_VSRAM_DIGRF_RC3_OP_EN_ADDR 0x1D2A 1814 #define MT6363_RG_LDO_VSRAM_DIGRF_RC4_OP_EN_ADDR 0x1D2A 1815 #define MT6363_RG_LDO_VSRAM_DIGRF_RC5_OP_EN_ADDR 0x1D2A 1816 #define MT6363_RG_LDO_VSRAM_DIGRF_RC6_OP_EN_ADDR 0x1D2A 1817 #define MT6363_RG_LDO_VSRAM_DIGRF_RC7_OP_EN_ADDR 0x1D2A 1818 #define MT6363_RG_LDO_VSRAM_DIGRF_RC8_OP_EN_ADDR 0x1D2B 1819 #define MT6363_RG_LDO_VSRAM_DIGRF_RC9_OP_EN_ADDR 0x1D2B 1820 #define MT6363_RG_LDO_VSRAM_DIGRF_RC10_OP_EN_ADDR 0x1D2B 1821 #define MT6363_RG_LDO_VSRAM_DIGRF_RC11_OP_EN_ADDR 0x1D2B 1822 #define MT6363_RG_LDO_VSRAM_DIGRF_RC12_OP_EN_ADDR 0x1D2B 1823 #define MT6363_RG_LDO_VSRAM_DIGRF_RC13_OP_EN_ADDR 0x1D2B 1824 #define MT6363_RG_LDO_VSRAM_DIGRF_HW0_OP_EN_ADDR 0x1D2C 1825 #define MT6363_RG_LDO_VSRAM_DIGRF_HW1_OP_EN_ADDR 0x1D2C 1826 #define MT6363_RG_LDO_VSRAM_DIGRF_HW2_OP_EN_ADDR 0x1D2C 1827 #define MT6363_RG_LDO_VSRAM_DIGRF_HW3_OP_EN_ADDR 0x1D2C 1828 #define MT6363_RG_LDO_VSRAM_DIGRF_HW4_OP_EN_ADDR 0x1D2C 1829 #define MT6363_RG_LDO_VSRAM_DIGRF_HW5_OP_EN_ADDR 0x1D2C 1830 #define MT6363_RG_LDO_VSRAM_DIGRF_HW6_OP_EN_ADDR 0x1D2C 1831 #define MT6363_RG_LDO_VSRAM_DIGRF_SW_OP_EN_ADDR 0x1D2C 1832 #define MT6363_RG_LDO_VSRAM_DIGRF_RC0_OP_CFG_ADDR 0x1D2D 1833 #define MT6363_RG_LDO_VSRAM_DIGRF_RC1_OP_CFG_ADDR 0x1D2D 1834 #define MT6363_RG_LDO_VSRAM_DIGRF_RC2_OP_CFG_ADDR 0x1D2D 1835 #define MT6363_RG_LDO_VSRAM_DIGRF_RC3_OP_CFG_ADDR 0x1D2D 1836 #define MT6363_RG_LDO_VSRAM_DIGRF_RC4_OP_CFG_ADDR 0x1D2D 1837 #define MT6363_RG_LDO_VSRAM_DIGRF_RC5_OP_CFG_ADDR 0x1D2D 1838 #define MT6363_RG_LDO_VSRAM_DIGRF_RC6_OP_CFG_ADDR 0x1D2D 1839 #define MT6363_RG_LDO_VSRAM_DIGRF_RC7_OP_CFG_ADDR 0x1D2D 1840 #define MT6363_RG_LDO_VSRAM_DIGRF_RC8_OP_CFG_ADDR 0x1D2E 1841 #define MT6363_RG_LDO_VSRAM_DIGRF_RC9_OP_CFG_ADDR 0x1D2E 1842 #define MT6363_RG_LDO_VSRAM_DIGRF_RC10_OP_CFG_ADDR 0x1D2E 1843 #define MT6363_RG_LDO_VSRAM_DIGRF_RC11_OP_CFG_ADDR 0x1D2E 1844 #define MT6363_RG_LDO_VSRAM_DIGRF_RC12_OP_CFG_ADDR 0x1D2E 1845 #define MT6363_RG_LDO_VSRAM_DIGRF_RC13_OP_CFG_ADDR 0x1D2E 1846 #define MT6363_RG_LDO_VSRAM_DIGRF_HW0_OP_CFG_ADDR 0x1D2F 1847 #define MT6363_RG_LDO_VSRAM_DIGRF_HW1_OP_CFG_ADDR 0x1D2F 1848 #define MT6363_RG_LDO_VSRAM_DIGRF_HW2_OP_CFG_ADDR 0x1D2F 1849 #define MT6363_RG_LDO_VSRAM_DIGRF_HW3_OP_CFG_ADDR 0x1D2F 1850 #define MT6363_RG_LDO_VSRAM_DIGRF_HW4_OP_CFG_ADDR 0x1D2F 1851 #define MT6363_RG_LDO_VSRAM_DIGRF_HW5_OP_CFG_ADDR 0x1D2F 1852 #define MT6363_RG_LDO_VSRAM_DIGRF_HW6_OP_CFG_ADDR 0x1D2F 1853 #define MT6363_RG_LDO_VSRAM_DIGRF_SW_OP_CFG_ADDR 0x1D2F 1854 #define MT6363_RG_LDO_VSRAM_DIGRF_RC0_OP_MODE_ADDR 0x1D30 1855 #define MT6363_RG_LDO_VSRAM_DIGRF_RC1_OP_MODE_ADDR 0x1D30 1856 #define MT6363_RG_LDO_VSRAM_DIGRF_RC2_OP_MODE_ADDR 0x1D30 1857 #define MT6363_RG_LDO_VSRAM_DIGRF_RC3_OP_MODE_ADDR 0x1D30 1858 #define MT6363_RG_LDO_VSRAM_DIGRF_RC4_OP_MODE_ADDR 0x1D30 1859 #define MT6363_RG_LDO_VSRAM_DIGRF_RC5_OP_MODE_ADDR 0x1D30 1860 #define MT6363_RG_LDO_VSRAM_DIGRF_RC6_OP_MODE_ADDR 0x1D30 1861 #define MT6363_RG_LDO_VSRAM_DIGRF_RC7_OP_MODE_ADDR 0x1D30 1862 #define MT6363_RG_LDO_VSRAM_DIGRF_RC8_OP_MODE_ADDR 0x1D31 1863 #define MT6363_RG_LDO_VSRAM_DIGRF_RC9_OP_MODE_ADDR 0x1D31 1864 #define MT6363_RG_LDO_VSRAM_DIGRF_RC10_OP_MODE_ADDR 0x1D31 1865 #define MT6363_RG_LDO_VSRAM_DIGRF_RC11_OP_MODE_ADDR 0x1D31 1866 #define MT6363_RG_LDO_VSRAM_DIGRF_RC12_OP_MODE_ADDR 0x1D31 1867 #define MT6363_RG_LDO_VSRAM_DIGRF_RC13_OP_MODE_ADDR 0x1D31 1868 #define MT6363_RG_LDO_VSRAM_DIGRF_HW0_OP_MODE_ADDR 0x1D32 1869 #define MT6363_RG_LDO_VSRAM_DIGRF_HW1_OP_MODE_ADDR 0x1D32 1870 #define MT6363_RG_LDO_VSRAM_DIGRF_HW2_OP_MODE_ADDR 0x1D32 1871 #define MT6363_RG_LDO_VSRAM_DIGRF_HW3_OP_MODE_ADDR 0x1D32 1872 #define MT6363_RG_LDO_VSRAM_DIGRF_HW4_OP_MODE_ADDR 0x1D32 1873 #define MT6363_RG_LDO_VSRAM_DIGRF_HW5_OP_MODE_ADDR 0x1D32 1874 #define MT6363_RG_LDO_VSRAM_DIGRF_HW6_OP_MODE_ADDR 0x1D32 1875 #define MT6363_RG_LDO_VSRAM_MDFE_ONLV_EN_ADDR 0x1D88 1876 #define MT6363_RG_LDO_VSRAM_MDFE_ONLV_EN_SHIFT 3 1877 #define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_SLEEP_ADDR 0x1D8D 1878 #define MT6363_RG_LDO_VSRAM_MDFE_RC0_OP_EN_ADDR 0x1D94 1879 #define MT6363_RG_LDO_VSRAM_MDFE_RC1_OP_EN_ADDR 0x1D94 1880 #define MT6363_RG_LDO_VSRAM_MDFE_RC2_OP_EN_ADDR 0x1D94 1881 #define MT6363_RG_LDO_VSRAM_MDFE_RC3_OP_EN_ADDR 0x1D94 1882 #define MT6363_RG_LDO_VSRAM_MDFE_RC4_OP_EN_ADDR 0x1D94 1883 #define MT6363_RG_LDO_VSRAM_MDFE_RC5_OP_EN_ADDR 0x1D94 1884 #define MT6363_RG_LDO_VSRAM_MDFE_RC6_OP_EN_ADDR 0x1D94 1885 #define MT6363_RG_LDO_VSRAM_MDFE_RC7_OP_EN_ADDR 0x1D94 1886 #define MT6363_RG_LDO_VSRAM_MDFE_RC8_OP_EN_ADDR 0x1D95 1887 #define MT6363_RG_LDO_VSRAM_MDFE_RC9_OP_EN_ADDR 0x1D95 1888 #define MT6363_RG_LDO_VSRAM_MDFE_RC10_OP_EN_ADDR 0x1D95 1889 #define MT6363_RG_LDO_VSRAM_MDFE_RC11_OP_EN_ADDR 0x1D95 1890 #define MT6363_RG_LDO_VSRAM_MDFE_RC12_OP_EN_ADDR 0x1D95 1891 #define MT6363_RG_LDO_VSRAM_MDFE_RC13_OP_EN_ADDR 0x1D95 1892 #define MT6363_RG_LDO_VSRAM_MDFE_HW0_OP_EN_ADDR 0x1D96 1893 #define MT6363_RG_LDO_VSRAM_MDFE_HW1_OP_EN_ADDR 0x1D96 1894 #define MT6363_RG_LDO_VSRAM_MDFE_HW2_OP_EN_ADDR 0x1D96 1895 #define MT6363_RG_LDO_VSRAM_MDFE_HW3_OP_EN_ADDR 0x1D96 1896 #define MT6363_RG_LDO_VSRAM_MDFE_HW4_OP_EN_ADDR 0x1D96 1897 #define MT6363_RG_LDO_VSRAM_MDFE_HW5_OP_EN_ADDR 0x1D96 1898 #define MT6363_RG_LDO_VSRAM_MDFE_HW6_OP_EN_ADDR 0x1D96 1899 #define MT6363_RG_LDO_VSRAM_MDFE_SW_OP_EN_ADDR 0x1D96 1900 #define MT6363_RG_LDO_VSRAM_MDFE_RC0_OP_CFG_ADDR 0x1D97 1901 #define MT6363_RG_LDO_VSRAM_MDFE_RC1_OP_CFG_ADDR 0x1D97 1902 #define MT6363_RG_LDO_VSRAM_MDFE_RC2_OP_CFG_ADDR 0x1D97 1903 #define MT6363_RG_LDO_VSRAM_MDFE_RC3_OP_CFG_ADDR 0x1D97 1904 #define MT6363_RG_LDO_VSRAM_MDFE_RC4_OP_CFG_ADDR 0x1D97 1905 #define MT6363_RG_LDO_VSRAM_MDFE_RC5_OP_CFG_ADDR 0x1D97 1906 #define MT6363_RG_LDO_VSRAM_MDFE_RC6_OP_CFG_ADDR 0x1D97 1907 #define MT6363_RG_LDO_VSRAM_MDFE_RC7_OP_CFG_ADDR 0x1D97 1908 #define MT6363_RG_LDO_VSRAM_MDFE_RC8_OP_CFG_ADDR 0x1D98 1909 #define MT6363_RG_LDO_VSRAM_MDFE_RC9_OP_CFG_ADDR 0x1D98 1910 #define MT6363_RG_LDO_VSRAM_MDFE_RC10_OP_CFG_ADDR 0x1D98 1911 #define MT6363_RG_LDO_VSRAM_MDFE_RC11_OP_CFG_ADDR 0x1D98 1912 #define MT6363_RG_LDO_VSRAM_MDFE_RC12_OP_CFG_ADDR 0x1D98 1913 #define MT6363_RG_LDO_VSRAM_MDFE_RC13_OP_CFG_ADDR 0x1D98 1914 #define MT6363_RG_LDO_VSRAM_MDFE_HW0_OP_CFG_ADDR 0x1D99 1915 #define MT6363_RG_LDO_VSRAM_MDFE_HW1_OP_CFG_ADDR 0x1D99 1916 #define MT6363_RG_LDO_VSRAM_MDFE_HW2_OP_CFG_ADDR 0x1D99 1917 #define MT6363_RG_LDO_VSRAM_MDFE_HW3_OP_CFG_ADDR 0x1D99 1918 #define MT6363_RG_LDO_VSRAM_MDFE_HW4_OP_CFG_ADDR 0x1D99 1919 #define MT6363_RG_LDO_VSRAM_MDFE_HW5_OP_CFG_ADDR 0x1D99 1920 #define MT6363_RG_LDO_VSRAM_MDFE_HW6_OP_CFG_ADDR 0x1D99 1921 #define MT6363_RG_LDO_VSRAM_MDFE_SW_OP_CFG_ADDR 0x1D99 1922 #define MT6363_RG_LDO_VSRAM_MDFE_RC0_OP_MODE_ADDR 0x1D9A 1923 #define MT6363_RG_LDO_VSRAM_MDFE_RC1_OP_MODE_ADDR 0x1D9A 1924 #define MT6363_RG_LDO_VSRAM_MDFE_RC2_OP_MODE_ADDR 0x1D9A 1925 #define MT6363_RG_LDO_VSRAM_MDFE_RC3_OP_MODE_ADDR 0x1D9A 1926 #define MT6363_RG_LDO_VSRAM_MDFE_RC4_OP_MODE_ADDR 0x1D9A 1927 #define MT6363_RG_LDO_VSRAM_MDFE_RC5_OP_MODE_ADDR 0x1D9A 1928 #define MT6363_RG_LDO_VSRAM_MDFE_RC6_OP_MODE_ADDR 0x1D9A 1929 #define MT6363_RG_LDO_VSRAM_MDFE_RC7_OP_MODE_ADDR 0x1D9A 1930 #define MT6363_RG_LDO_VSRAM_MDFE_RC8_OP_MODE_ADDR 0x1D9B 1931 #define MT6363_RG_LDO_VSRAM_MDFE_RC9_OP_MODE_ADDR 0x1D9B 1932 #define MT6363_RG_LDO_VSRAM_MDFE_RC10_OP_MODE_ADDR 0x1D9B 1933 #define MT6363_RG_LDO_VSRAM_MDFE_RC11_OP_MODE_ADDR 0x1D9B 1934 #define MT6363_RG_LDO_VSRAM_MDFE_RC12_OP_MODE_ADDR 0x1D9B 1935 #define MT6363_RG_LDO_VSRAM_MDFE_RC13_OP_MODE_ADDR 0x1D9B 1936 #define MT6363_RG_LDO_VSRAM_MDFE_HW0_OP_MODE_ADDR 0x1D9C 1937 #define MT6363_RG_LDO_VSRAM_MDFE_HW1_OP_MODE_ADDR 0x1D9C 1938 #define MT6363_RG_LDO_VSRAM_MDFE_HW2_OP_MODE_ADDR 0x1D9C 1939 #define MT6363_RG_LDO_VSRAM_MDFE_HW3_OP_MODE_ADDR 0x1D9C 1940 #define MT6363_RG_LDO_VSRAM_MDFE_HW4_OP_MODE_ADDR 0x1D9C 1941 #define MT6363_RG_LDO_VSRAM_MDFE_HW5_OP_MODE_ADDR 0x1D9C 1942 #define MT6363_RG_LDO_VSRAM_MDFE_HW6_OP_MODE_ADDR 0x1D9C 1943 #define MT6363_RG_LDO_VSRAM_MODEM_ONLV_EN_ADDR 0x1DA3 1944 #define MT6363_RG_LDO_VSRAM_MODEM_ONLV_EN_SHIFT 3 1945 #define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_SLEEP_ADDR 0x1DA8 1946 #define MT6363_RG_LDO_VSRAM_MODEM_RC0_OP_EN_ADDR 0x1DAF 1947 #define MT6363_RG_LDO_VSRAM_MODEM_RC1_OP_EN_ADDR 0x1DAF 1948 #define MT6363_RG_LDO_VSRAM_MODEM_RC2_OP_EN_ADDR 0x1DAF 1949 #define MT6363_RG_LDO_VSRAM_MODEM_RC3_OP_EN_ADDR 0x1DAF 1950 #define MT6363_RG_LDO_VSRAM_MODEM_RC4_OP_EN_ADDR 0x1DAF 1951 #define MT6363_RG_LDO_VSRAM_MODEM_RC5_OP_EN_ADDR 0x1DAF 1952 #define MT6363_RG_LDO_VSRAM_MODEM_RC6_OP_EN_ADDR 0x1DAF 1953 #define MT6363_RG_LDO_VSRAM_MODEM_RC7_OP_EN_ADDR 0x1DAF 1954 #define MT6363_RG_LDO_VSRAM_MODEM_RC8_OP_EN_ADDR 0x1DB0 1955 #define MT6363_RG_LDO_VSRAM_MODEM_RC9_OP_EN_ADDR 0x1DB0 1956 #define MT6363_RG_LDO_VSRAM_MODEM_RC10_OP_EN_ADDR 0x1DB0 1957 #define MT6363_RG_LDO_VSRAM_MODEM_RC11_OP_EN_ADDR 0x1DB0 1958 #define MT6363_RG_LDO_VSRAM_MODEM_RC12_OP_EN_ADDR 0x1DB0 1959 #define MT6363_RG_LDO_VSRAM_MODEM_RC13_OP_EN_ADDR 0x1DB0 1960 #define MT6363_RG_LDO_VSRAM_MODEM_HW0_OP_EN_ADDR 0x1DB1 1961 #define MT6363_RG_LDO_VSRAM_MODEM_HW1_OP_EN_ADDR 0x1DB1 1962 #define MT6363_RG_LDO_VSRAM_MODEM_HW2_OP_EN_ADDR 0x1DB1 1963 #define MT6363_RG_LDO_VSRAM_MODEM_HW3_OP_EN_ADDR 0x1DB1 1964 #define MT6363_RG_LDO_VSRAM_MODEM_HW4_OP_EN_ADDR 0x1DB1 1965 #define MT6363_RG_LDO_VSRAM_MODEM_HW5_OP_EN_ADDR 0x1DB1 1966 #define MT6363_RG_LDO_VSRAM_MODEM_HW6_OP_EN_ADDR 0x1DB1 1967 #define MT6363_RG_LDO_VSRAM_MODEM_SW_OP_EN_ADDR 0x1DB1 1968 #define MT6363_RG_LDO_VSRAM_MODEM_RC0_OP_CFG_ADDR 0x1DB2 1969 #define MT6363_RG_LDO_VSRAM_MODEM_RC1_OP_CFG_ADDR 0x1DB2 1970 #define MT6363_RG_LDO_VSRAM_MODEM_RC2_OP_CFG_ADDR 0x1DB2 1971 #define MT6363_RG_LDO_VSRAM_MODEM_RC3_OP_CFG_ADDR 0x1DB2 1972 #define MT6363_RG_LDO_VSRAM_MODEM_RC4_OP_CFG_ADDR 0x1DB2 1973 #define MT6363_RG_LDO_VSRAM_MODEM_RC5_OP_CFG_ADDR 0x1DB2 1974 #define MT6363_RG_LDO_VSRAM_MODEM_RC6_OP_CFG_ADDR 0x1DB2 1975 #define MT6363_RG_LDO_VSRAM_MODEM_RC7_OP_CFG_ADDR 0x1DB2 1976 #define MT6363_RG_LDO_VSRAM_MODEM_RC8_OP_CFG_ADDR 0x1DB3 1977 #define MT6363_RG_LDO_VSRAM_MODEM_RC9_OP_CFG_ADDR 0x1DB3 1978 #define MT6363_RG_LDO_VSRAM_MODEM_RC10_OP_CFG_ADDR 0x1DB3 1979 #define MT6363_RG_LDO_VSRAM_MODEM_RC11_OP_CFG_ADDR 0x1DB3 1980 #define MT6363_RG_LDO_VSRAM_MODEM_RC12_OP_CFG_ADDR 0x1DB3 1981 #define MT6363_RG_LDO_VSRAM_MODEM_RC13_OP_CFG_ADDR 0x1DB3 1982 #define MT6363_RG_LDO_VSRAM_MODEM_HW0_OP_CFG_ADDR 0x1DB4 1983 #define MT6363_RG_LDO_VSRAM_MODEM_HW1_OP_CFG_ADDR 0x1DB4 1984 #define MT6363_RG_LDO_VSRAM_MODEM_HW2_OP_CFG_ADDR 0x1DB4 1985 #define MT6363_RG_LDO_VSRAM_MODEM_HW3_OP_CFG_ADDR 0x1DB4 1986 #define MT6363_RG_LDO_VSRAM_MODEM_HW4_OP_CFG_ADDR 0x1DB4 1987 #define MT6363_RG_LDO_VSRAM_MODEM_HW5_OP_CFG_ADDR 0x1DB4 1988 #define MT6363_RG_LDO_VSRAM_MODEM_HW6_OP_CFG_ADDR 0x1DB4 1989 #define MT6363_RG_LDO_VSRAM_MODEM_SW_OP_CFG_ADDR 0x1DB4 1990 #define MT6363_RG_LDO_VSRAM_MODEM_RC0_OP_MODE_ADDR 0x1DB5 1991 #define MT6363_RG_LDO_VSRAM_MODEM_RC1_OP_MODE_ADDR 0x1DB5 1992 #define MT6363_RG_LDO_VSRAM_MODEM_RC2_OP_MODE_ADDR 0x1DB5 1993 #define MT6363_RG_LDO_VSRAM_MODEM_RC3_OP_MODE_ADDR 0x1DB5 1994 #define MT6363_RG_LDO_VSRAM_MODEM_RC4_OP_MODE_ADDR 0x1DB5 1995 #define MT6363_RG_LDO_VSRAM_MODEM_RC5_OP_MODE_ADDR 0x1DB5 1996 #define MT6363_RG_LDO_VSRAM_MODEM_RC6_OP_MODE_ADDR 0x1DB5 1997 #define MT6363_RG_LDO_VSRAM_MODEM_RC7_OP_MODE_ADDR 0x1DB5 1998 #define MT6363_RG_LDO_VSRAM_MODEM_RC8_OP_MODE_ADDR 0x1DB6 1999 #define MT6363_RG_LDO_VSRAM_MODEM_RC9_OP_MODE_ADDR 0x1DB6 2000 #define MT6363_RG_LDO_VSRAM_MODEM_RC10_OP_MODE_ADDR 0x1DB6 2001 #define MT6363_RG_LDO_VSRAM_MODEM_RC11_OP_MODE_ADDR 0x1DB6 2002 #define MT6363_RG_LDO_VSRAM_MODEM_RC12_OP_MODE_ADDR 0x1DB6 2003 #define MT6363_RG_LDO_VSRAM_MODEM_RC13_OP_MODE_ADDR 0x1DB6 2004 #define MT6363_RG_LDO_VSRAM_MODEM_HW0_OP_MODE_ADDR 0x1DB7 2005 #define MT6363_RG_LDO_VSRAM_MODEM_HW1_OP_MODE_ADDR 0x1DB7 2006 #define MT6363_RG_LDO_VSRAM_MODEM_HW2_OP_MODE_ADDR 0x1DB7 2007 #define MT6363_RG_LDO_VSRAM_MODEM_HW3_OP_MODE_ADDR 0x1DB7 2008 #define MT6363_RG_LDO_VSRAM_MODEM_HW4_OP_MODE_ADDR 0x1DB7 2009 #define MT6363_RG_LDO_VSRAM_MODEM_HW5_OP_MODE_ADDR 0x1DB7 2010 #define MT6363_RG_LDO_VSRAM_MODEM_HW6_OP_MODE_ADDR 0x1DB7 2011 #define MT6363_RG_LDO_VSRAM_CPUB_ONLV_EN_ADDR 0x1E08 2012 #define MT6363_RG_LDO_VSRAM_CPUB_ONLV_EN_SHIFT 3 2013 #define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_SLEEP_ADDR 0x1E0D 2014 #define MT6363_RG_LDO_VSRAM_CPUB_RC0_OP_EN_ADDR 0x1E14 2015 #define MT6363_RG_LDO_VSRAM_CPUB_RC1_OP_EN_ADDR 0x1E14 2016 #define MT6363_RG_LDO_VSRAM_CPUB_RC2_OP_EN_ADDR 0x1E14 2017 #define MT6363_RG_LDO_VSRAM_CPUB_RC3_OP_EN_ADDR 0x1E14 2018 #define MT6363_RG_LDO_VSRAM_CPUB_RC4_OP_EN_ADDR 0x1E14 2019 #define MT6363_RG_LDO_VSRAM_CPUB_RC5_OP_EN_ADDR 0x1E14 2020 #define MT6363_RG_LDO_VSRAM_CPUB_RC6_OP_EN_ADDR 0x1E14 2021 #define MT6363_RG_LDO_VSRAM_CPUB_RC7_OP_EN_ADDR 0x1E14 2022 #define MT6363_RG_LDO_VSRAM_CPUB_RC8_OP_EN_ADDR 0x1E15 2023 #define MT6363_RG_LDO_VSRAM_CPUB_RC9_OP_EN_ADDR 0x1E15 2024 #define MT6363_RG_LDO_VSRAM_CPUB_RC10_OP_EN_ADDR 0x1E15 2025 #define MT6363_RG_LDO_VSRAM_CPUB_RC11_OP_EN_ADDR 0x1E15 2026 #define MT6363_RG_LDO_VSRAM_CPUB_RC12_OP_EN_ADDR 0x1E15 2027 #define MT6363_RG_LDO_VSRAM_CPUB_RC13_OP_EN_ADDR 0x1E15 2028 #define MT6363_RG_LDO_VSRAM_CPUB_HW0_OP_EN_ADDR 0x1E16 2029 #define MT6363_RG_LDO_VSRAM_CPUB_HW1_OP_EN_ADDR 0x1E16 2030 #define MT6363_RG_LDO_VSRAM_CPUB_HW2_OP_EN_ADDR 0x1E16 2031 #define MT6363_RG_LDO_VSRAM_CPUB_HW3_OP_EN_ADDR 0x1E16 2032 #define MT6363_RG_LDO_VSRAM_CPUB_HW4_OP_EN_ADDR 0x1E16 2033 #define MT6363_RG_LDO_VSRAM_CPUB_HW5_OP_EN_ADDR 0x1E16 2034 #define MT6363_RG_LDO_VSRAM_CPUB_HW6_OP_EN_ADDR 0x1E16 2035 #define MT6363_RG_LDO_VSRAM_CPUB_SW_OP_EN_ADDR 0x1E16 2036 #define MT6363_RG_LDO_VSRAM_CPUB_RC0_OP_CFG_ADDR 0x1E17 2037 #define MT6363_RG_LDO_VSRAM_CPUB_RC1_OP_CFG_ADDR 0x1E17 2038 #define MT6363_RG_LDO_VSRAM_CPUB_RC2_OP_CFG_ADDR 0x1E17 2039 #define MT6363_RG_LDO_VSRAM_CPUB_RC3_OP_CFG_ADDR 0x1E17 2040 #define MT6363_RG_LDO_VSRAM_CPUB_RC4_OP_CFG_ADDR 0x1E17 2041 #define MT6363_RG_LDO_VSRAM_CPUB_RC5_OP_CFG_ADDR 0x1E17 2042 #define MT6363_RG_LDO_VSRAM_CPUB_RC6_OP_CFG_ADDR 0x1E17 2043 #define MT6363_RG_LDO_VSRAM_CPUB_RC7_OP_CFG_ADDR 0x1E17 2044 #define MT6363_RG_LDO_VSRAM_CPUB_RC8_OP_CFG_ADDR 0x1E18 2045 #define MT6363_RG_LDO_VSRAM_CPUB_RC9_OP_CFG_ADDR 0x1E18 2046 #define MT6363_RG_LDO_VSRAM_CPUB_RC10_OP_CFG_ADDR 0x1E18 2047 #define MT6363_RG_LDO_VSRAM_CPUB_RC11_OP_CFG_ADDR 0x1E18 2048 #define MT6363_RG_LDO_VSRAM_CPUB_RC12_OP_CFG_ADDR 0x1E18 2049 #define MT6363_RG_LDO_VSRAM_CPUB_RC13_OP_CFG_ADDR 0x1E18 2050 #define MT6363_RG_LDO_VSRAM_CPUB_HW0_OP_CFG_ADDR 0x1E19 2051 #define MT6363_RG_LDO_VSRAM_CPUB_HW1_OP_CFG_ADDR 0x1E19 2052 #define MT6363_RG_LDO_VSRAM_CPUB_HW2_OP_CFG_ADDR 0x1E19 2053 #define MT6363_RG_LDO_VSRAM_CPUB_HW3_OP_CFG_ADDR 0x1E19 2054 #define MT6363_RG_LDO_VSRAM_CPUB_HW4_OP_CFG_ADDR 0x1E19 2055 #define MT6363_RG_LDO_VSRAM_CPUB_HW5_OP_CFG_ADDR 0x1E19 2056 #define MT6363_RG_LDO_VSRAM_CPUB_HW6_OP_CFG_ADDR 0x1E19 2057 #define MT6363_RG_LDO_VSRAM_CPUB_SW_OP_CFG_ADDR 0x1E19 2058 #define MT6363_RG_LDO_VSRAM_CPUB_RC0_OP_MODE_ADDR 0x1E1A 2059 #define MT6363_RG_LDO_VSRAM_CPUB_RC1_OP_MODE_ADDR 0x1E1A 2060 #define MT6363_RG_LDO_VSRAM_CPUB_RC2_OP_MODE_ADDR 0x1E1A 2061 #define MT6363_RG_LDO_VSRAM_CPUB_RC3_OP_MODE_ADDR 0x1E1A 2062 #define MT6363_RG_LDO_VSRAM_CPUB_RC4_OP_MODE_ADDR 0x1E1A 2063 #define MT6363_RG_LDO_VSRAM_CPUB_RC5_OP_MODE_ADDR 0x1E1A 2064 #define MT6363_RG_LDO_VSRAM_CPUB_RC6_OP_MODE_ADDR 0x1E1A 2065 #define MT6363_RG_LDO_VSRAM_CPUB_RC7_OP_MODE_ADDR 0x1E1A 2066 #define MT6363_RG_LDO_VSRAM_CPUB_RC8_OP_MODE_ADDR 0x1E1B 2067 #define MT6363_RG_LDO_VSRAM_CPUB_RC9_OP_MODE_ADDR 0x1E1B 2068 #define MT6363_RG_LDO_VSRAM_CPUB_RC10_OP_MODE_ADDR 0x1E1B 2069 #define MT6363_RG_LDO_VSRAM_CPUB_RC11_OP_MODE_ADDR 0x1E1B 2070 #define MT6363_RG_LDO_VSRAM_CPUB_RC12_OP_MODE_ADDR 0x1E1B 2071 #define MT6363_RG_LDO_VSRAM_CPUB_RC13_OP_MODE_ADDR 0x1E1B 2072 #define MT6363_RG_LDO_VSRAM_CPUB_HW0_OP_MODE_ADDR 0x1E1C 2073 #define MT6363_RG_LDO_VSRAM_CPUB_HW1_OP_MODE_ADDR 0x1E1C 2074 #define MT6363_RG_LDO_VSRAM_CPUB_HW2_OP_MODE_ADDR 0x1E1C 2075 #define MT6363_RG_LDO_VSRAM_CPUB_HW3_OP_MODE_ADDR 0x1E1C 2076 #define MT6363_RG_LDO_VSRAM_CPUB_HW4_OP_MODE_ADDR 0x1E1C 2077 #define MT6363_RG_LDO_VSRAM_CPUB_HW5_OP_MODE_ADDR 0x1E1C 2078 #define MT6363_RG_LDO_VSRAM_CPUB_HW6_OP_MODE_ADDR 0x1E1C 2079 #define MT6363_RG_LDO_VSRAM_CPUM_ONLV_EN_ADDR 0x1E1E 2080 #define MT6363_RG_LDO_VSRAM_CPUM_ONLV_EN_SHIFT 3 2081 #define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_SLEEP_ADDR 0x1E23 2082 #define MT6363_RG_LDO_VSRAM_CPUM_RC0_OP_EN_ADDR 0x1E2A 2083 #define MT6363_RG_LDO_VSRAM_CPUM_RC1_OP_EN_ADDR 0x1E2A 2084 #define MT6363_RG_LDO_VSRAM_CPUM_RC2_OP_EN_ADDR 0x1E2A 2085 #define MT6363_RG_LDO_VSRAM_CPUM_RC3_OP_EN_ADDR 0x1E2A 2086 #define MT6363_RG_LDO_VSRAM_CPUM_RC4_OP_EN_ADDR 0x1E2A 2087 #define MT6363_RG_LDO_VSRAM_CPUM_RC5_OP_EN_ADDR 0x1E2A 2088 #define MT6363_RG_LDO_VSRAM_CPUM_RC6_OP_EN_ADDR 0x1E2A 2089 #define MT6363_RG_LDO_VSRAM_CPUM_RC7_OP_EN_ADDR 0x1E2A 2090 #define MT6363_RG_LDO_VSRAM_CPUM_RC8_OP_EN_ADDR 0x1E2B 2091 #define MT6363_RG_LDO_VSRAM_CPUM_RC9_OP_EN_ADDR 0x1E2B 2092 #define MT6363_RG_LDO_VSRAM_CPUM_RC10_OP_EN_ADDR 0x1E2B 2093 #define MT6363_RG_LDO_VSRAM_CPUM_RC11_OP_EN_ADDR 0x1E2B 2094 #define MT6363_RG_LDO_VSRAM_CPUM_RC12_OP_EN_ADDR 0x1E2B 2095 #define MT6363_RG_LDO_VSRAM_CPUM_RC13_OP_EN_ADDR 0x1E2B 2096 #define MT6363_RG_LDO_VSRAM_CPUM_HW0_OP_EN_ADDR 0x1E2C 2097 #define MT6363_RG_LDO_VSRAM_CPUM_HW1_OP_EN_ADDR 0x1E2C 2098 #define MT6363_RG_LDO_VSRAM_CPUM_HW2_OP_EN_ADDR 0x1E2C 2099 #define MT6363_RG_LDO_VSRAM_CPUM_HW3_OP_EN_ADDR 0x1E2C 2100 #define MT6363_RG_LDO_VSRAM_CPUM_HW4_OP_EN_ADDR 0x1E2C 2101 #define MT6363_RG_LDO_VSRAM_CPUM_HW5_OP_EN_ADDR 0x1E2C 2102 #define MT6363_RG_LDO_VSRAM_CPUM_HW6_OP_EN_ADDR 0x1E2C 2103 #define MT6363_RG_LDO_VSRAM_CPUM_SW_OP_EN_ADDR 0x1E2C 2104 #define MT6363_RG_LDO_VSRAM_CPUM_RC0_OP_CFG_ADDR 0x1E2D 2105 #define MT6363_RG_LDO_VSRAM_CPUM_RC1_OP_CFG_ADDR 0x1E2D 2106 #define MT6363_RG_LDO_VSRAM_CPUM_RC2_OP_CFG_ADDR 0x1E2D 2107 #define MT6363_RG_LDO_VSRAM_CPUM_RC3_OP_CFG_ADDR 0x1E2D 2108 #define MT6363_RG_LDO_VSRAM_CPUM_RC4_OP_CFG_ADDR 0x1E2D 2109 #define MT6363_RG_LDO_VSRAM_CPUM_RC5_OP_CFG_ADDR 0x1E2D 2110 #define MT6363_RG_LDO_VSRAM_CPUM_RC6_OP_CFG_ADDR 0x1E2D 2111 #define MT6363_RG_LDO_VSRAM_CPUM_RC7_OP_CFG_ADDR 0x1E2D 2112 #define MT6363_RG_LDO_VSRAM_CPUM_RC8_OP_CFG_ADDR 0x1E2E 2113 #define MT6363_RG_LDO_VSRAM_CPUM_RC9_OP_CFG_ADDR 0x1E2E 2114 #define MT6363_RG_LDO_VSRAM_CPUM_RC10_OP_CFG_ADDR 0x1E2E 2115 #define MT6363_RG_LDO_VSRAM_CPUM_RC11_OP_CFG_ADDR 0x1E2E 2116 #define MT6363_RG_LDO_VSRAM_CPUM_RC12_OP_CFG_ADDR 0x1E2E 2117 #define MT6363_RG_LDO_VSRAM_CPUM_RC13_OP_CFG_ADDR 0x1E2E 2118 #define MT6363_RG_LDO_VSRAM_CPUM_HW0_OP_CFG_ADDR 0x1E2F 2119 #define MT6363_RG_LDO_VSRAM_CPUM_HW1_OP_CFG_ADDR 0x1E2F 2120 #define MT6363_RG_LDO_VSRAM_CPUM_HW2_OP_CFG_ADDR 0x1E2F 2121 #define MT6363_RG_LDO_VSRAM_CPUM_HW3_OP_CFG_ADDR 0x1E2F 2122 #define MT6363_RG_LDO_VSRAM_CPUM_HW4_OP_CFG_ADDR 0x1E2F 2123 #define MT6363_RG_LDO_VSRAM_CPUM_HW5_OP_CFG_ADDR 0x1E2F 2124 #define MT6363_RG_LDO_VSRAM_CPUM_HW6_OP_CFG_ADDR 0x1E2F 2125 #define MT6363_RG_LDO_VSRAM_CPUM_SW_OP_CFG_ADDR 0x1E2F 2126 #define MT6363_RG_LDO_VSRAM_CPUM_RC0_OP_MODE_ADDR 0x1E30 2127 #define MT6363_RG_LDO_VSRAM_CPUM_RC1_OP_MODE_ADDR 0x1E30 2128 #define MT6363_RG_LDO_VSRAM_CPUM_RC2_OP_MODE_ADDR 0x1E30 2129 #define MT6363_RG_LDO_VSRAM_CPUM_RC3_OP_MODE_ADDR 0x1E30 2130 #define MT6363_RG_LDO_VSRAM_CPUM_RC4_OP_MODE_ADDR 0x1E30 2131 #define MT6363_RG_LDO_VSRAM_CPUM_RC5_OP_MODE_ADDR 0x1E30 2132 #define MT6363_RG_LDO_VSRAM_CPUM_RC6_OP_MODE_ADDR 0x1E30 2133 #define MT6363_RG_LDO_VSRAM_CPUM_RC7_OP_MODE_ADDR 0x1E30 2134 #define MT6363_RG_LDO_VSRAM_CPUM_RC8_OP_MODE_ADDR 0x1E31 2135 #define MT6363_RG_LDO_VSRAM_CPUM_RC9_OP_MODE_ADDR 0x1E31 2136 #define MT6363_RG_LDO_VSRAM_CPUM_RC10_OP_MODE_ADDR 0x1E31 2137 #define MT6363_RG_LDO_VSRAM_CPUM_RC11_OP_MODE_ADDR 0x1E31 2138 #define MT6363_RG_LDO_VSRAM_CPUM_RC12_OP_MODE_ADDR 0x1E31 2139 #define MT6363_RG_LDO_VSRAM_CPUM_RC13_OP_MODE_ADDR 0x1E31 2140 #define MT6363_RG_LDO_VSRAM_CPUM_HW0_OP_MODE_ADDR 0x1E32 2141 #define MT6363_RG_LDO_VSRAM_CPUM_HW1_OP_MODE_ADDR 0x1E32 2142 #define MT6363_RG_LDO_VSRAM_CPUM_HW2_OP_MODE_ADDR 0x1E32 2143 #define MT6363_RG_LDO_VSRAM_CPUM_HW3_OP_MODE_ADDR 0x1E32 2144 #define MT6363_RG_LDO_VSRAM_CPUM_HW4_OP_MODE_ADDR 0x1E32 2145 #define MT6363_RG_LDO_VSRAM_CPUM_HW5_OP_MODE_ADDR 0x1E32 2146 #define MT6363_RG_LDO_VSRAM_CPUM_HW6_OP_MODE_ADDR 0x1E32 2147 #define MT6363_RG_LDO_VSRAM_CPUL_ONLV_EN_ADDR 0x1E88 2148 #define MT6363_RG_LDO_VSRAM_CPUL_ONLV_EN_SHIFT 3 2149 #define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_SLEEP_ADDR 0x1E8D 2150 #define MT6363_RG_LDO_VSRAM_CPUL_RC0_OP_EN_ADDR 0x1E94 2151 #define MT6363_RG_LDO_VSRAM_CPUL_RC1_OP_EN_ADDR 0x1E94 2152 #define MT6363_RG_LDO_VSRAM_CPUL_RC2_OP_EN_ADDR 0x1E94 2153 #define MT6363_RG_LDO_VSRAM_CPUL_RC3_OP_EN_ADDR 0x1E94 2154 #define MT6363_RG_LDO_VSRAM_CPUL_RC4_OP_EN_ADDR 0x1E94 2155 #define MT6363_RG_LDO_VSRAM_CPUL_RC5_OP_EN_ADDR 0x1E94 2156 #define MT6363_RG_LDO_VSRAM_CPUL_RC6_OP_EN_ADDR 0x1E94 2157 #define MT6363_RG_LDO_VSRAM_CPUL_RC7_OP_EN_ADDR 0x1E94 2158 #define MT6363_RG_LDO_VSRAM_CPUL_RC8_OP_EN_ADDR 0x1E95 2159 #define MT6363_RG_LDO_VSRAM_CPUL_RC9_OP_EN_ADDR 0x1E95 2160 #define MT6363_RG_LDO_VSRAM_CPUL_RC10_OP_EN_ADDR 0x1E95 2161 #define MT6363_RG_LDO_VSRAM_CPUL_RC11_OP_EN_ADDR 0x1E95 2162 #define MT6363_RG_LDO_VSRAM_CPUL_RC12_OP_EN_ADDR 0x1E95 2163 #define MT6363_RG_LDO_VSRAM_CPUL_RC13_OP_EN_ADDR 0x1E95 2164 #define MT6363_RG_LDO_VSRAM_CPUL_HW0_OP_EN_ADDR 0x1E96 2165 #define MT6363_RG_LDO_VSRAM_CPUL_HW1_OP_EN_ADDR 0x1E96 2166 #define MT6363_RG_LDO_VSRAM_CPUL_HW2_OP_EN_ADDR 0x1E96 2167 #define MT6363_RG_LDO_VSRAM_CPUL_HW3_OP_EN_ADDR 0x1E96 2168 #define MT6363_RG_LDO_VSRAM_CPUL_HW4_OP_EN_ADDR 0x1E96 2169 #define MT6363_RG_LDO_VSRAM_CPUL_HW5_OP_EN_ADDR 0x1E96 2170 #define MT6363_RG_LDO_VSRAM_CPUL_HW6_OP_EN_ADDR 0x1E96 2171 #define MT6363_RG_LDO_VSRAM_CPUL_SW_OP_EN_ADDR 0x1E96 2172 #define MT6363_RG_LDO_VSRAM_CPUL_RC0_OP_CFG_ADDR 0x1E97 2173 #define MT6363_RG_LDO_VSRAM_CPUL_RC1_OP_CFG_ADDR 0x1E97 2174 #define MT6363_RG_LDO_VSRAM_CPUL_RC2_OP_CFG_ADDR 0x1E97 2175 #define MT6363_RG_LDO_VSRAM_CPUL_RC3_OP_CFG_ADDR 0x1E97 2176 #define MT6363_RG_LDO_VSRAM_CPUL_RC4_OP_CFG_ADDR 0x1E97 2177 #define MT6363_RG_LDO_VSRAM_CPUL_RC5_OP_CFG_ADDR 0x1E97 2178 #define MT6363_RG_LDO_VSRAM_CPUL_RC6_OP_CFG_ADDR 0x1E97 2179 #define MT6363_RG_LDO_VSRAM_CPUL_RC7_OP_CFG_ADDR 0x1E97 2180 #define MT6363_RG_LDO_VSRAM_CPUL_RC8_OP_CFG_ADDR 0x1E98 2181 #define MT6363_RG_LDO_VSRAM_CPUL_RC9_OP_CFG_ADDR 0x1E98 2182 #define MT6363_RG_LDO_VSRAM_CPUL_RC10_OP_CFG_ADDR 0x1E98 2183 #define MT6363_RG_LDO_VSRAM_CPUL_RC11_OP_CFG_ADDR 0x1E98 2184 #define MT6363_RG_LDO_VSRAM_CPUL_RC12_OP_CFG_ADDR 0x1E98 2185 #define MT6363_RG_LDO_VSRAM_CPUL_RC13_OP_CFG_ADDR 0x1E98 2186 #define MT6363_RG_LDO_VSRAM_CPUL_HW0_OP_CFG_ADDR 0x1E99 2187 #define MT6363_RG_LDO_VSRAM_CPUL_HW1_OP_CFG_ADDR 0x1E99 2188 #define MT6363_RG_LDO_VSRAM_CPUL_HW2_OP_CFG_ADDR 0x1E99 2189 #define MT6363_RG_LDO_VSRAM_CPUL_HW3_OP_CFG_ADDR 0x1E99 2190 #define MT6363_RG_LDO_VSRAM_CPUL_HW4_OP_CFG_ADDR 0x1E99 2191 #define MT6363_RG_LDO_VSRAM_CPUL_HW5_OP_CFG_ADDR 0x1E99 2192 #define MT6363_RG_LDO_VSRAM_CPUL_HW6_OP_CFG_ADDR 0x1E99 2193 #define MT6363_RG_LDO_VSRAM_CPUL_SW_OP_CFG_ADDR 0x1E99 2194 #define MT6363_RG_LDO_VSRAM_CPUL_RC0_OP_MODE_ADDR 0x1E9A 2195 #define MT6363_RG_LDO_VSRAM_CPUL_RC1_OP_MODE_ADDR 0x1E9A 2196 #define MT6363_RG_LDO_VSRAM_CPUL_RC2_OP_MODE_ADDR 0x1E9A 2197 #define MT6363_RG_LDO_VSRAM_CPUL_RC3_OP_MODE_ADDR 0x1E9A 2198 #define MT6363_RG_LDO_VSRAM_CPUL_RC4_OP_MODE_ADDR 0x1E9A 2199 #define MT6363_RG_LDO_VSRAM_CPUL_RC5_OP_MODE_ADDR 0x1E9A 2200 #define MT6363_RG_LDO_VSRAM_CPUL_RC6_OP_MODE_ADDR 0x1E9A 2201 #define MT6363_RG_LDO_VSRAM_CPUL_RC7_OP_MODE_ADDR 0x1E9A 2202 #define MT6363_RG_LDO_VSRAM_CPUL_RC8_OP_MODE_ADDR 0x1E9B 2203 #define MT6363_RG_LDO_VSRAM_CPUL_RC9_OP_MODE_ADDR 0x1E9B 2204 #define MT6363_RG_LDO_VSRAM_CPUL_RC10_OP_MODE_ADDR 0x1E9B 2205 #define MT6363_RG_LDO_VSRAM_CPUL_RC11_OP_MODE_ADDR 0x1E9B 2206 #define MT6363_RG_LDO_VSRAM_CPUL_RC12_OP_MODE_ADDR 0x1E9B 2207 #define MT6363_RG_LDO_VSRAM_CPUL_RC13_OP_MODE_ADDR 0x1E9B 2208 #define MT6363_RG_LDO_VSRAM_CPUL_HW0_OP_MODE_ADDR 0x1E9C 2209 #define MT6363_RG_LDO_VSRAM_CPUL_HW1_OP_MODE_ADDR 0x1E9C 2210 #define MT6363_RG_LDO_VSRAM_CPUL_HW2_OP_MODE_ADDR 0x1E9C 2211 #define MT6363_RG_LDO_VSRAM_CPUL_HW3_OP_MODE_ADDR 0x1E9C 2212 #define MT6363_RG_LDO_VSRAM_CPUL_HW4_OP_MODE_ADDR 0x1E9C 2213 #define MT6363_RG_LDO_VSRAM_CPUL_HW5_OP_MODE_ADDR 0x1E9C 2214 #define MT6363_RG_LDO_VSRAM_CPUL_HW6_OP_MODE_ADDR 0x1E9C 2215 #define MT6363_RG_LDO_VSRAM_APU_ONLV_EN_ADDR 0x1E9E 2216 #define MT6363_RG_LDO_VSRAM_APU_ONLV_EN_SHIFT 3 2217 #define MT6363_RG_LDO_VSRAM_APU_VOSEL_SLEEP_ADDR 0x1EA3 2218 #define MT6363_RG_LDO_VSRAM_APU_RC0_OP_EN_ADDR 0x1EAA 2219 #define MT6363_RG_LDO_VSRAM_APU_RC1_OP_EN_ADDR 0x1EAA 2220 #define MT6363_RG_LDO_VSRAM_APU_RC2_OP_EN_ADDR 0x1EAA 2221 #define MT6363_RG_LDO_VSRAM_APU_RC3_OP_EN_ADDR 0x1EAA 2222 #define MT6363_RG_LDO_VSRAM_APU_RC4_OP_EN_ADDR 0x1EAA 2223 #define MT6363_RG_LDO_VSRAM_APU_RC5_OP_EN_ADDR 0x1EAA 2224 #define MT6363_RG_LDO_VSRAM_APU_RC6_OP_EN_ADDR 0x1EAA 2225 #define MT6363_RG_LDO_VSRAM_APU_RC7_OP_EN_ADDR 0x1EAA 2226 #define MT6363_RG_LDO_VSRAM_APU_RC8_OP_EN_ADDR 0x1EAB 2227 #define MT6363_RG_LDO_VSRAM_APU_RC9_OP_EN_ADDR 0x1EAB 2228 #define MT6363_RG_LDO_VSRAM_APU_RC10_OP_EN_ADDR 0x1EAB 2229 #define MT6363_RG_LDO_VSRAM_APU_RC11_OP_EN_ADDR 0x1EAB 2230 #define MT6363_RG_LDO_VSRAM_APU_RC12_OP_EN_ADDR 0x1EAB 2231 #define MT6363_RG_LDO_VSRAM_APU_RC13_OP_EN_ADDR 0x1EAB 2232 #define MT6363_RG_LDO_VSRAM_APU_HW0_OP_EN_ADDR 0x1EAC 2233 #define MT6363_RG_LDO_VSRAM_APU_HW1_OP_EN_ADDR 0x1EAC 2234 #define MT6363_RG_LDO_VSRAM_APU_HW2_OP_EN_ADDR 0x1EAC 2235 #define MT6363_RG_LDO_VSRAM_APU_HW3_OP_EN_ADDR 0x1EAC 2236 #define MT6363_RG_LDO_VSRAM_APU_HW4_OP_EN_ADDR 0x1EAC 2237 #define MT6363_RG_LDO_VSRAM_APU_HW5_OP_EN_ADDR 0x1EAC 2238 #define MT6363_RG_LDO_VSRAM_APU_HW6_OP_EN_ADDR 0x1EAC 2239 #define MT6363_RG_LDO_VSRAM_APU_SW_OP_EN_ADDR 0x1EAC 2240 #define MT6363_RG_LDO_VSRAM_APU_RC0_OP_CFG_ADDR 0x1EAD 2241 #define MT6363_RG_LDO_VSRAM_APU_RC1_OP_CFG_ADDR 0x1EAD 2242 #define MT6363_RG_LDO_VSRAM_APU_RC2_OP_CFG_ADDR 0x1EAD 2243 #define MT6363_RG_LDO_VSRAM_APU_RC3_OP_CFG_ADDR 0x1EAD 2244 #define MT6363_RG_LDO_VSRAM_APU_RC4_OP_CFG_ADDR 0x1EAD 2245 #define MT6363_RG_LDO_VSRAM_APU_RC5_OP_CFG_ADDR 0x1EAD 2246 #define MT6363_RG_LDO_VSRAM_APU_RC6_OP_CFG_ADDR 0x1EAD 2247 #define MT6363_RG_LDO_VSRAM_APU_RC7_OP_CFG_ADDR 0x1EAD 2248 #define MT6363_RG_LDO_VSRAM_APU_RC8_OP_CFG_ADDR 0x1EAE 2249 #define MT6363_RG_LDO_VSRAM_APU_RC9_OP_CFG_ADDR 0x1EAE 2250 #define MT6363_RG_LDO_VSRAM_APU_RC10_OP_CFG_ADDR 0x1EAE 2251 #define MT6363_RG_LDO_VSRAM_APU_RC11_OP_CFG_ADDR 0x1EAE 2252 #define MT6363_RG_LDO_VSRAM_APU_RC12_OP_CFG_ADDR 0x1EAE 2253 #define MT6363_RG_LDO_VSRAM_APU_RC13_OP_CFG_ADDR 0x1EAE 2254 #define MT6363_RG_LDO_VSRAM_APU_HW0_OP_CFG_ADDR 0x1EAF 2255 #define MT6363_RG_LDO_VSRAM_APU_HW1_OP_CFG_ADDR 0x1EAF 2256 #define MT6363_RG_LDO_VSRAM_APU_HW2_OP_CFG_ADDR 0x1EAF 2257 #define MT6363_RG_LDO_VSRAM_APU_HW3_OP_CFG_ADDR 0x1EAF 2258 #define MT6363_RG_LDO_VSRAM_APU_HW4_OP_CFG_ADDR 0x1EAF 2259 #define MT6363_RG_LDO_VSRAM_APU_HW5_OP_CFG_ADDR 0x1EAF 2260 #define MT6363_RG_LDO_VSRAM_APU_HW6_OP_CFG_ADDR 0x1EAF 2261 #define MT6363_RG_LDO_VSRAM_APU_SW_OP_CFG_ADDR 0x1EAF 2262 #define MT6363_RG_LDO_VSRAM_APU_RC0_OP_MODE_ADDR 0x1EB0 2263 #define MT6363_RG_LDO_VSRAM_APU_RC1_OP_MODE_ADDR 0x1EB0 2264 #define MT6363_RG_LDO_VSRAM_APU_RC2_OP_MODE_ADDR 0x1EB0 2265 #define MT6363_RG_LDO_VSRAM_APU_RC3_OP_MODE_ADDR 0x1EB0 2266 #define MT6363_RG_LDO_VSRAM_APU_RC4_OP_MODE_ADDR 0x1EB0 2267 #define MT6363_RG_LDO_VSRAM_APU_RC5_OP_MODE_ADDR 0x1EB0 2268 #define MT6363_RG_LDO_VSRAM_APU_RC6_OP_MODE_ADDR 0x1EB0 2269 #define MT6363_RG_LDO_VSRAM_APU_RC7_OP_MODE_ADDR 0x1EB0 2270 #define MT6363_RG_LDO_VSRAM_APU_RC8_OP_MODE_ADDR 0x1EB1 2271 #define MT6363_RG_LDO_VSRAM_APU_RC9_OP_MODE_ADDR 0x1EB1 2272 #define MT6363_RG_LDO_VSRAM_APU_RC10_OP_MODE_ADDR 0x1EB1 2273 #define MT6363_RG_LDO_VSRAM_APU_RC11_OP_MODE_ADDR 0x1EB1 2274 #define MT6363_RG_LDO_VSRAM_APU_RC12_OP_MODE_ADDR 0x1EB1 2275 #define MT6363_RG_LDO_VSRAM_APU_RC13_OP_MODE_ADDR 0x1EB1 2276 #define MT6363_RG_LDO_VSRAM_APU_HW0_OP_MODE_ADDR 0x1EB2 2277 #define MT6363_RG_LDO_VSRAM_APU_HW1_OP_MODE_ADDR 0x1EB2 2278 #define MT6363_RG_LDO_VSRAM_APU_HW2_OP_MODE_ADDR 0x1EB2 2279 #define MT6363_RG_LDO_VSRAM_APU_HW3_OP_MODE_ADDR 0x1EB2 2280 #define MT6363_RG_LDO_VSRAM_APU_HW4_OP_MODE_ADDR 0x1EB2 2281 #define MT6363_RG_LDO_VSRAM_APU_HW5_OP_MODE_ADDR 0x1EB2 2282 #define MT6363_RG_LDO_VSRAM_APU_HW6_OP_MODE_ADDR 0x1EB2 2283 #define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT0_ADDR 0x189A 2284 #define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT1_ADDR 0x189A 2285 #define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT2_ADDR 0x189A 2286 #define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT3_ADDR 0x189A 2287 #define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT4_ADDR 0x189A 2288 #define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT5_ADDR 0x189A 2289 #define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT6_ADDR 0x189A 2290 #define MT6363_RG_BUCK_VS1_VOTER_EN_LO_BIT7_ADDR 0x189A 2291 #define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT0_ADDR 0x189D 2292 #define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT1_ADDR 0x189D 2293 #define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT2_ADDR 0x189D 2294 #define MT6363_RG_BUCK_VS1_VOTER_EN_HI_BIT3_ADDR 0x189D 2295 #define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT0_ADDR 0x149A 2296 #define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT1_ADDR 0x149A 2297 #define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT2_ADDR 0x149A 2298 #define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT3_ADDR 0x149A 2299 #define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT4_ADDR 0x149A 2300 #define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT5_ADDR 0x149A 2301 #define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT6_ADDR 0x149A 2302 #define MT6363_RG_BUCK_VS2_VOTER_EN_LO_BIT7_ADDR 0x149A 2303 #define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT0_ADDR 0x149D 2304 #define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT1_ADDR 0x149D 2305 #define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT2_ADDR 0x149D 2306 #define MT6363_RG_BUCK_VS2_VOTER_EN_HI_BIT3_ADDR 0x149D 2307 #define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT0_ADDR 0x191A 2308 #define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT1_ADDR 0x191A 2309 #define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT2_ADDR 0x191A 2310 #define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT3_ADDR 0x191A 2311 #define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT4_ADDR 0x191A 2312 #define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT5_ADDR 0x191A 2313 #define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT6_ADDR 0x191A 2314 #define MT6363_RG_BUCK_VS3_VOTER_EN_LO_BIT7_ADDR 0x191A 2315 #define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT0_ADDR 0x191D 2316 #define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT1_ADDR 0x191D 2317 #define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT2_ADDR 0x191D 2318 #define MT6363_RG_BUCK_VS3_VOTER_EN_HI_BIT3_ADDR 0x191D 2319 2320 #endif /* MT6363_LOWPOWER_REG_H */ 2321