1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MCUCFG_V1_H 8 #define MCUCFG_V1_H 9 10 #ifndef __ASSEMBLER__ 11 #include <stdint.h> 12 #endif /*__ASSEMBLER__*/ 13 #include <platform_def.h> 14 15 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) \ 16 (MCUCFG_BASE + 0x2290 + ((cpu) * 8)) 17 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) \ 18 (MCUCFG_BASE + 0x2294 + ((cpu) * 8)) 19 20 #define MP2_CPUCFG (MCUCFG_BASE + 0x2208) 21 22 #define MP2_CPU0_STANDBYWFE BIT(4) 23 #define MP2_CPU1_STANDBYWFE BIT(5) 24 25 #define MP0_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x788) 26 #define MP1_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x78C) 27 #define MP1_CPUTOP_SPMC_SRAM_CTL (MCUCFG_BASE + 0x790) 28 29 #define sw_spark_en BIT(0) 30 #define sw_no_wait_for_q_channel BIT(1) 31 #define sw_fsm_override BIT(2) 32 #define sw_logic_pre1_pdb BIT(3) 33 #define sw_logic_pre2_pdb BIT(4) 34 #define sw_logic_pdb BIT(5) 35 #define sw_iso BIT(6) 36 #define sw_sram_sleepb (0x3FU << 7) 37 #define sw_sram_isointb BIT(13) 38 #define sw_clk_dis BIT(14) 39 #define sw_ckiso BIT(15) 40 #define sw_pd (0x3FU << 16) 41 #define sw_hot_plug_reset BIT(22) 42 #define sw_pwr_on_override_en BIT(23) 43 #define sw_pwr_on BIT(24) 44 #define sw_coq_dis BIT(25) 45 #define logic_pdbo_all_off_ack BIT(26) 46 #define logic_pdbo_all_on_ack BIT(27) 47 #define logic_pre2_pdbo_all_on_ack BIT(28) 48 #define logic_pre1_pdbo_all_on_ack BIT(29) 49 50 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \ 51 (MCUCFG_BASE + 0x1C30 + (cluster) * 0x2000 + (cpu) * 4) 52 53 #define CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1C30) 54 #define CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1C34) 55 #define CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1C38) 56 #define CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1C3C) 57 58 #define CPUSYS1_CPU0_SPMC_CTL (MCUCFG_BASE + 0x3C30) 59 #define CPUSYS1_CPU1_SPMC_CTL (MCUCFG_BASE + 0x3C34) 60 #define CPUSYS1_CPU2_SPMC_CTL (MCUCFG_BASE + 0x3C38) 61 #define CPUSYS1_CPU3_SPMC_CTL (MCUCFG_BASE + 0x3C3C) 62 63 #define cpu_sw_spark_en BIT(0) 64 #define cpu_sw_no_wait_for_q_channel BIT(1) 65 #define cpu_sw_fsm_override BIT(2) 66 #define cpu_sw_logic_pre1_pdb BIT(3) 67 #define cpu_sw_logic_pre2_pdb BIT(4) 68 #define cpu_sw_logic_pdb BIT(5) 69 #define cpu_sw_iso BIT(6) 70 #define cpu_sw_sram_sleepb BIT(7) 71 #define cpu_sw_sram_isointb BIT(8) 72 #define cpu_sw_clk_dis BIT(9) 73 #define cpu_sw_ckiso BIT(10) 74 #define cpu_sw_pd (0x1FU<<11) 75 #define cpu_sw_hot_plug_reset BIT(16) 76 #define cpu_sw_powr_on_override_en BIT(17) 77 #define cpu_sw_pwr_on BIT(18) 78 #define cpu_spark2ldo_allswoff BIT(19) 79 #define cpu_pdbo_all_on_ack BIT(20) 80 #define cpu_pre2_pdbo_allon_ack BIT(21) 81 #define cpu_pre1_pdbo_allon_ack BIT(22) 82 83 /* CPC related registers */ 84 #define CPC_MCUSYS_CPC_OFF_THRES (MCUCFG_BASE + 0xa714) 85 #define CPC_MCUSYS_PWR_CTRL (MCUCFG_BASE + 0xa804) 86 #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUCFG_BASE + 0xa814) 87 #define CPC_MCUSYS_LAST_CORE_REQ (MCUCFG_BASE + 0xa818) 88 #define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUCFG_BASE + 0xa81c) 89 #define CPC_MCUSYS_LAST_CORE_RESP (MCUCFG_BASE + 0xa824) 90 #define CPC_MCUSYS_PWR_ON_MASK (MCUCFG_BASE + 0xa828) 91 #define CPC_SPMC_PWR_STATUS (MCUCFG_BASE + 0xa840) 92 #define CPC_WAKEUP_REQ (MCUCFG_BASE + 0xa84c) 93 #define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUCFG_BASE + 0xa8a8) 94 #define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUCFG_BASE + 0xa8ac) 95 #define CPC_MCUSYS_CPC_DBG_SETTING (MCUCFG_BASE + 0xab00) 96 #define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUCFG_BASE + 0xab04) 97 #define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUCFG_BASE + 0xab08) 98 #define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUCFG_BASE + 0xab0c) 99 #define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUCFG_BASE + 0xab10) 100 #define CPC_MCUSYS_TRACE_SEL (MCUCFG_BASE + 0xab14) 101 #define CPC_MCUSYS_TRACE_DATA (MCUCFG_BASE + 0xab20) 102 #define CPC_CPU0_LATENCY (MCUCFG_BASE + 0xab40) 103 #define CPC_CLUSTER_OFF_LATENCY (MCUCFG_BASE + 0xab60) 104 #define CPC_CLUSTER_ON_LATENCY (MCUCFG_BASE + 0xab64) 105 #define CPC_MCUSYS_LATENCY (MCUCFG_BASE + 0xab68) 106 #define CPC_MCUSYS_CLUSTER_COUNTER (MCUCFG_BASE + 0xab70) 107 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUCFG_BASE + 0xab74) 108 #define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu)) 109 110 /* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */ 111 #define CPC_CTRL_ENABLE BIT(16) 112 #ifdef CPU_PM_SPM_CORE_POWERON 113 #define SSPM_ALL_PWR_CTRL_EN BIT(13) 114 #else 115 #define SSPM_ALL_PWR_CTRL_EN BIT(17) 116 #endif 117 #define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu)) 118 119 #define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON BIT(17) 120 #define CPC_MCUSYS_CPC_RESET_PWR_ON_EN BIT(20) 121 122 /* SPMC related registers */ 123 #define SPM_MCUSYS_PWR_CON (MCUCFG_BASE + 0xd200) 124 #define SPM_MP0_CPUTOP_PWR_CON (MCUCFG_BASE + 0xd204) 125 #define SPM_MP0_CPU0_PWR_CON (MCUCFG_BASE + 0xd208) 126 #define SPM_MP0_CPU1_PWR_CON (MCUCFG_BASE + 0xd20c) 127 #define SPM_MP0_CPU2_PWR_CON (MCUCFG_BASE + 0xd210) 128 #define SPM_MP0_CPU3_PWR_CON (MCUCFG_BASE + 0xd214) 129 #define SPM_MP0_CPU4_PWR_CON (MCUCFG_BASE + 0xd218) 130 #define SPM_MP0_CPU5_PWR_CON (MCUCFG_BASE + 0xd21c) 131 #define SPM_MP0_CPU6_PWR_CON (MCUCFG_BASE + 0xd220) 132 #define SPM_MP0_CPU7_PWR_CON (MCUCFG_BASE + 0xd224) 133 134 #define MCSIC_DCM0 (MCUCFG_BASE + 0xa440) 135 #define MCSIC_DCM1 (MCUCFG_BASE + 0xa444) 136 137 /* bit fields of SPM_*_PWR_CON */ 138 #define PWR_ON_ACK BIT(31) 139 #define VPROC_EXT_OFF BIT(7) 140 #define DORMANT_EN BIT(6) 141 #define RESETPWRON_CONFIG BIT(5) 142 #define PWR_CLK_DIS BIT(4) 143 #define PWR_ON BIT(2) 144 #define PWR_RST_B BIT(0) 145 146 #define SPARK2LDO (MCUCFG_BASE + 0x2700) 147 /* APB Module mcucfg */ 148 #define MP0_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x000) 149 #define MP0_AXI_CONFIG (MCUCFG_BASE + 0x02C) 150 #define MP0_MISC_CONFIG0 (MCUCFG_BASE + 0x030) 151 #define MP0_MISC_CONFIG1 (MCUCFG_BASE + 0x034) 152 #define MP0_MISC_CONFIG2 (MCUCFG_BASE + 0x038) 153 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x038 + (cpu) * 8) 154 #define MP0_MISC_CONFIG3 (MCUCFG_BASE + 0x03C) 155 #define MP0_MISC_CONFIG9 (MCUCFG_BASE + 0x054) 156 #define MP0_CA7_MISC_CONFIG (MCUCFG_BASE + 0x064) 157 158 #define MP0_RW_RSVD0 (MCUCFG_BASE + 0x06C) 159 160 #define MP1_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x200) 161 #define MP1_AXI_CONFIG (MCUCFG_BASE + 0x22C) 162 #define MP1_MISC_CONFIG0 (MCUCFG_BASE + 0x230) 163 #define MP1_MISC_CONFIG1 (MCUCFG_BASE + 0x234) 164 #define MP1_MISC_CONFIG2 (MCUCFG_BASE + 0x238) 165 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x238 + ((cpu) * 8)) 166 #define MP1_MISC_CONFIG3 (MCUCFG_BASE + 0x23C) 167 #define MP1_MISC_CONFIG9 (MCUCFG_BASE + 0x254) 168 #define MP1_CA7_MISC_CONFIG (MCUCFG_BASE + 0x264) 169 170 #define CCI_ADB400_DCM_CONFIG (MCUCFG_BASE + 0x740) 171 #define SYNC_DCM_CONFIG (MCUCFG_BASE + 0x744) 172 173 #define MP0_CLUSTER_CFG0 (MCUCFG_BASE + 0xC8D0) 174 175 #define MP0_SPMC (MCUCFG_BASE + 0x788) 176 #define MP1_SPMC (MCUCFG_BASE + 0x78C) 177 #define MP2_AXI_CONFIG (MCUCFG_BASE + 0x220C) 178 #define MP2_AXI_CONFIG_ACINACTM BIT(0) 179 #define MP2_AXI_CONFIG_AINACTS BIT(4) 180 181 #define MPx_AXI_CONFIG_ACINACTM BIT(4) 182 #define MPx_AXI_CONFIG_AINACTS BIT(5) 183 184 #define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28) 185 186 #define MP0_CPU0_STANDBYWFE BIT(20) 187 #define MP0_CPU1_STANDBYWFE BIT(21) 188 #define MP0_CPU2_STANDBYWFE BIT(22) 189 #define MP0_CPU3_STANDBYWFE BIT(23) 190 191 #define MP1_CPU0_STANDBYWFE BIT(20) 192 #define MP1_CPU1_STANDBYWFE BIT(21) 193 #define MP1_CPU2_STANDBYWFE BIT(22) 194 #define MP1_CPU3_STANDBYWFE BIT(23) 195 196 #define CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00) 197 #define CPUSYS0_SPARKEN (MCUCFG_BASE + 0x1c04) 198 #define CPUSYS0_AMUXSEL (MCUCFG_BASE + 0x1c08) 199 #define CPUSYS1_SPARKVRETCNTRL (MCUCFG_BASE + 0x3c00) 200 #define CPUSYS1_SPARKEN (MCUCFG_BASE + 0x3c04) 201 #define CPUSYS1_AMUXSEL (MCUCFG_BASE + 0x3c08) 202 203 #define MP2_PWR_RST_CTL (MCUCFG_BASE + 0x2008) 204 #define MP2_PTP3_CPUTOP_SPMC0 (MCUCFG_BASE + 0x22A0) 205 #define MP2_PTP3_CPUTOP_SPMC1 (MCUCFG_BASE + 0x22A4) 206 207 #define MP2_COQ (MCUCFG_BASE + 0x22BC) 208 #define MP2_COQ_SW_DIS BIT(0) 209 210 #define MP2_CA15M_MON_SEL (MCUCFG_BASE + 0x2400) 211 #define MP2_CA15M_MON_L (MCUCFG_BASE + 0x2404) 212 213 #define CPUSYS2_CPU0_SPMC_CTL (MCUCFG_BASE + 0x2430) 214 #define CPUSYS2_CPU1_SPMC_CTL (MCUCFG_BASE + 0x2438) 215 #define CPUSYS2_CPU0_SPMC_STA (MCUCFG_BASE + 0x2434) 216 #define CPUSYS2_CPU1_SPMC_STA (MCUCFG_BASE + 0x243C) 217 218 #define MP0_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x068) 219 #define MP1_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x268) 220 #define BIG_DBG_PWR_CTRL (MCUCFG_BASE + 0x75C) 221 222 #define MP2_SW_RST_B BIT(0) 223 #define MP2_TOPAON_APB_MASK BIT(1) 224 225 #define B_SW_HOT_PLUG_RESET BIT(30) 226 227 #define B_SW_PD_OFFSET (18) 228 #define B_SW_PD (0x3F << B_SW_PD_OFFSET) 229 230 #define B_SW_SRAM_SLEEPB_OFFSET (12) 231 #define B_SW_SRAM_SLEEPB (0x3f << B_SW_SRAM_SLEEPB_OFFSET) 232 233 #define B_SW_SRAM_ISOINTB BIT(9) 234 #define B_SW_ISO BIT(8) 235 #define B_SW_LOGIC_PDB BIT(7) 236 #define B_SW_LOGIC_PRE2_PDB BIT(6) 237 #define B_SW_LOGIC_PRE1_PDB BIT(5) 238 #define B_SW_FSM_OVERRIDE BIT(4) 239 #define B_SW_PWR_ON BIT(3) 240 #define B_SW_PWR_ON_OVERRIDE_EN BIT(2) 241 242 #define B_FSM_STATE_OUT_OFFSET (6) 243 #define B_FSM_STATE_OUT_MASK (0x1f << B_FSM_STATE_OUT_OFFSET) 244 #define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5) 245 #define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4) 246 #define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3) 247 #define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2) 248 249 #define B_FSM_OFF (0u << B_FSM_STATE_OUT_OFFSET) 250 #define B_FSM_ON (1u << B_FSM_STATE_OUT_OFFSET) 251 #define B_FSM_RET (2u << B_FSM_STATE_OUT_OFFSET) 252 253 #ifndef __ASSEMBLER__ 254 /* cpu boot mode */ 255 enum mp0_coucfg_64bit_ctrl { 256 MP0_CPUCFG_64BIT_SHIFT = 12, 257 MP1_CPUCFG_64BIT_SHIFT = 28, 258 MP0_CPUCFG_64BIT = 0xFU << MP0_CPUCFG_64BIT_SHIFT, 259 MP1_CPUCFG_64BIT = 0xFU << MP1_CPUCFG_64BIT_SHIFT 260 }; 261 262 enum mp1_dis_rgu0_ctrl { 263 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, 264 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, 265 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, 266 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, 267 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, 268 269 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = 270 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, 271 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = 272 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, 273 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = 274 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, 275 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = 276 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, 277 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = 278 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT 279 }; 280 281 enum mp1_ainacts_ctrl { 282 MP1_AINACTS_SHIFT = 4, 283 MP1_AINACTS = BIT(MP1_AINACTS_SHIFT) 284 }; 285 286 enum mp1_sw_cg_gen { 287 MP1_SW_CG_GEN_SHIFT = 12, 288 MP1_SW_CG_GEN = BIT(MP1_SW_CG_GEN_SHIFT) 289 }; 290 291 enum mp1_l2rstdisable { 292 MP1_L2RSTDISABLE_SHIFT = 14, 293 MP1_L2RSTDISABLE = BIT(MP1_L2RSTDISABLE_SHIFT) 294 }; 295 #endif /*__ASSEMBLER__*/ 296 297 #endif /* __MCUCFG_V1_H__ */ 298