1*f0dce796SKunlong Wang /* 2*f0dce796SKunlong Wang * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3*f0dce796SKunlong Wang * 4*f0dce796SKunlong Wang * SPDX-License-Identifier: BSD-3-Clause 5*f0dce796SKunlong Wang */ 6*f0dce796SKunlong Wang 7*f0dce796SKunlong Wang #ifndef DRAMC_H 8*f0dce796SKunlong Wang #define DRAMC_H 9*f0dce796SKunlong Wang 10*f0dce796SKunlong Wang #define DRAM_MAX_FREQ 16 11*f0dce796SKunlong Wang #define DRAM_MAX_MR_CNT 10 12*f0dce796SKunlong Wang #define DRAM_MAX_RK 2 13*f0dce796SKunlong Wang 14*f0dce796SKunlong Wang int init_dramc_info(void *tag_entry); 15*f0dce796SKunlong Wang int get_dram_step_freq(unsigned int step); 16*f0dce796SKunlong Wang unsigned int get_dram_type(void); 17*f0dce796SKunlong Wang 18*f0dce796SKunlong Wang enum dram_type { 19*f0dce796SKunlong Wang TYPE_DDR1 = 1, 20*f0dce796SKunlong Wang TYPE_LPDDR2, 21*f0dce796SKunlong Wang TYPE_LPDDR3, 22*f0dce796SKunlong Wang TYPE_PCDDR3, 23*f0dce796SKunlong Wang TYPE_LPDDR4, 24*f0dce796SKunlong Wang TYPE_LPDDR4X, 25*f0dce796SKunlong Wang TYPE_LPDDR4P, 26*f0dce796SKunlong Wang TYPE_LPDDR5, 27*f0dce796SKunlong Wang TYPE_LPDDR5X, 28*f0dce796SKunlong Wang }; 29*f0dce796SKunlong Wang #endif /* DRAMC_H */ 30