xref: /rk3399_ARM-atf/plat/mediatek/include/drivers/dbgtop.h (revision cf2df874cd09305ac7282fadb0fef6be597dfffb)
1*f0dce796SKunlong Wang /*
2*f0dce796SKunlong Wang  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3*f0dce796SKunlong Wang  *
4*f0dce796SKunlong Wang  * SPDX-License-Identifier: BSD-3-Clause
5*f0dce796SKunlong Wang  */
6*f0dce796SKunlong Wang 
7*f0dce796SKunlong Wang #ifndef DBGTOP_H
8*f0dce796SKunlong Wang #define DBGTOP_H
9*f0dce796SKunlong Wang 
10*f0dce796SKunlong Wang int mtk_dbgtop_dram_reserved(int enable);
11*f0dce796SKunlong Wang int mtk_dbgtop_cfg_dvfsrc(int enable);
12*f0dce796SKunlong Wang int mtk_dbgtop_dfd_count_en(int enable);
13*f0dce796SKunlong Wang int mtk_dbgtop_drm_latch_en(int enable);
14*f0dce796SKunlong Wang int mtk_dbgtop_dfd_pause_dvfsrc(int enable);
15*f0dce796SKunlong Wang 
16*f0dce796SKunlong Wang #endif /* DBGTOP_H */
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