1*a65fadfbSGavin Liu/* 2*a65fadfbSGavin Liu * Copyright (c) 2024, Mediatek Inc. All rights reserved. 3*a65fadfbSGavin Liu * 4*a65fadfbSGavin Liu * SPDX-License-Identifier: BSD-3-Clause 5*a65fadfbSGavin Liu */ 6*a65fadfbSGavin Liu 7*a65fadfbSGavin Liu#include <arch.h> 8*a65fadfbSGavin Liu#include <asm_macros.S> 9*a65fadfbSGavin Liu#include <assert_macros.S> 10*a65fadfbSGavin Liu#include <cpu_macros.S> 11*a65fadfbSGavin Liu#include <platform_def.h> 12*a65fadfbSGavin Liu#if CONFIG_MTK_MCUSYS 13*a65fadfbSGavin Liu#include <mcucfg.h> 14*a65fadfbSGavin Liu#endif 15*a65fadfbSGavin Liu 16*a65fadfbSGavin Liu /* 17*a65fadfbSGavin Liu * Declare as weak function so that can be 18*a65fadfbSGavin Liu * overwritten by platform helpers 19*a65fadfbSGavin Liu */ 20*a65fadfbSGavin Liu .weak platform_mem_init 21*a65fadfbSGavin Liu .weak plat_core_pos_by_mpidr 22*a65fadfbSGavin Liu .weak plat_my_core_pos 23*a65fadfbSGavin Liu .weak plat_mediatek_calc_core_pos 24*a65fadfbSGavin Liu .global plat_mpidr_by_core_pos 25*a65fadfbSGavin Liu .global plat_reset_handler 26*a65fadfbSGavin Liu 27*a65fadfbSGavin Liu /* ----------------------------------------------------- 28*a65fadfbSGavin Liu * unsigned long plat_mpidr_by_core_pos(uint32_t cpuid) 29*a65fadfbSGavin Liu * This function calcuate mpidr by cpu pos if cpu 30*a65fadfbSGavin Liu * topology is linear. 31*a65fadfbSGavin Liu * 32*a65fadfbSGavin Liu * Clobbers: x0-x1 33*a65fadfbSGavin Liu * ----------------------------------------------------- 34*a65fadfbSGavin Liu */ 35*a65fadfbSGavin Liufunc plat_mpidr_by_core_pos 36*a65fadfbSGavin Liu lsl x0, x0, #MPIDR_AFF1_SHIFT 37*a65fadfbSGavin Liu mrs x1, mpidr_el1 38*a65fadfbSGavin Liu and x1, x1, #MPIDR_MT_MASK 39*a65fadfbSGavin Liu orr x0, x0, x1 40*a65fadfbSGavin Liu ret 41*a65fadfbSGavin Liuendfunc plat_mpidr_by_core_pos 42*a65fadfbSGavin Liu 43*a65fadfbSGavin Liu /* ----------------------------------------------------- 44*a65fadfbSGavin Liu * unsigned int plat_my_core_pos(void) 45*a65fadfbSGavin Liu * This function uses the plat_arm_calc_core_pos() 46*a65fadfbSGavin Liu * definition to get the index of the calling CPU. 47*a65fadfbSGavin Liu * ----------------------------------------------------- 48*a65fadfbSGavin Liu */ 49*a65fadfbSGavin Liufunc plat_my_core_pos 50*a65fadfbSGavin Liu mrs x0, mpidr_el1 51*a65fadfbSGavin Liu b plat_mediatek_calc_core_pos 52*a65fadfbSGavin Liuendfunc plat_my_core_pos 53*a65fadfbSGavin Liu 54*a65fadfbSGavin Liu /* ----------------------------------------------------- 55*a65fadfbSGavin Liu * int plat_mediatek_calc_core_pos(u_register_t mpidr); 56*a65fadfbSGavin Liu * 57*a65fadfbSGavin Liu * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and 58*a65fadfbSGavin Liu * AFF0 is thread id. There is only one cluster in ARMv8.2 59*a65fadfbSGavin Liu * and one thread in current implementation. 60*a65fadfbSGavin Liu * 61*a65fadfbSGavin Liu * With this function: CorePos = CoreID (AFF1) 62*a65fadfbSGavin Liu * we do it with x0 = (x0 >> 8) & 0xff 63*a65fadfbSGavin Liu * ----------------------------------------------------- 64*a65fadfbSGavin Liu */ 65*a65fadfbSGavin Liufunc plat_mediatek_calc_core_pos 66*a65fadfbSGavin Liu b plat_core_pos_by_mpidr 67*a65fadfbSGavin Liuendfunc plat_mediatek_calc_core_pos 68*a65fadfbSGavin Liu 69*a65fadfbSGavin Liu /* ------------------------------------------------------ 70*a65fadfbSGavin Liu * int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 71*a65fadfbSGavin Liu * 72*a65fadfbSGavin Liu * This function implements a part of the critical 73*a65fadfbSGavin Liu * interface between the psci generic layer and the 74*a65fadfbSGavin Liu * platform that allows the former to query the platform 75*a65fadfbSGavin Liu * to convert an MPIDR to a unique linear index. 76*a65fadfbSGavin Liu * 77*a65fadfbSGavin Liu * Clobbers: x0-x1 78*a65fadfbSGavin Liu * ------------------------------------------------------ 79*a65fadfbSGavin Liu */ 80*a65fadfbSGavin Liufunc plat_core_pos_by_mpidr 81*a65fadfbSGavin Liu mov x1, #MPIDR_AFFLVL_MASK 82*a65fadfbSGavin Liu and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT 83*a65fadfbSGavin Liu ret 84*a65fadfbSGavin Liuendfunc plat_core_pos_by_mpidr 85*a65fadfbSGavin Liu 86*a65fadfbSGavin Liu /* -------------------------------------------------------- 87*a65fadfbSGavin Liu * void platform_mem_init (void); 88*a65fadfbSGavin Liu * 89*a65fadfbSGavin Liu * Any memory init, relocation to be done before the 90*a65fadfbSGavin Liu * platform boots. Called very early in the boot process. 91*a65fadfbSGavin Liu * -------------------------------------------------------- 92*a65fadfbSGavin Liu */ 93*a65fadfbSGavin Liufunc platform_mem_init 94*a65fadfbSGavin Liu ret 95*a65fadfbSGavin Liuendfunc platform_mem_init 96*a65fadfbSGavin Liu 97*a65fadfbSGavin Liufunc plat_reset_handler 98*a65fadfbSGavin Liu#if CONFIG_MTK_MCUSYS 99*a65fadfbSGavin Liu mov x10, x30 100*a65fadfbSGavin Liu bl plat_my_core_pos 101*a65fadfbSGavin Liu mov x30, x10 102*a65fadfbSGavin Liu mov w1, #0x1 103*a65fadfbSGavin Liu lsl w1, w1, w0 104*a65fadfbSGavin Liu ldr x0, =CPC_MCUSYS_CPU_ON_SW_HINT_SET 105*a65fadfbSGavin Liu str w1, [x0] 106*a65fadfbSGavin Liu dsb sy 107*a65fadfbSGavin Liu#endif 108*a65fadfbSGavin Liu 109*a65fadfbSGavin Liu ret 110*a65fadfbSGavin Liuendfunc plat_reset_handler 111