xref: /rk3399_ARM-atf/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c (revision 02309a84fbfb8b3469aa7dba52ea15c9bf2a768d)
1*31a69d9aSYidi Lin /*
2*31a69d9aSYidi Lin  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3*31a69d9aSYidi Lin  *
4*31a69d9aSYidi Lin  * SPDX-License-Identifier: BSD-3-Clause
5*31a69d9aSYidi Lin  */
6*31a69d9aSYidi Lin 
7*31a69d9aSYidi Lin #include <drivers/pmic/pmic_set_lowpower.h>
8*31a69d9aSYidi Lin #if defined(CONFIG_MTK_MTCMOS)
9*31a69d9aSYidi Lin #include <mtcmos.h>
10*31a69d9aSYidi Lin #endif
11*31a69d9aSYidi Lin #include <mtk_bl31_interface.h>
12*31a69d9aSYidi Lin 
ufs_vsx_lpm(bool lpm,uint64_t ufs_version)13*31a69d9aSYidi Lin static void ufs_vsx_lpm(bool lpm, uint64_t ufs_version)
14*31a69d9aSYidi Lin {
15*31a69d9aSYidi Lin 	if (lpm) {
16*31a69d9aSYidi Lin 		/* MT6363 VS2 voter LOW byte BIT6 vote reduce VS2 voltage */
17*31a69d9aSYidi Lin 		PMIC_BUCK_VOTER_EN(MT6363, VS2, VOTER_EN_LO_BIT6, VOTER_EN_CLR);
18*31a69d9aSYidi Lin 
19*31a69d9aSYidi Lin 		/* VS2 buck can enter LPM */
20*31a69d9aSYidi Lin 		PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_LP);
21*31a69d9aSYidi Lin 	} else {
22*31a69d9aSYidi Lin 		/* MT6363 VS2 voter LOW byte BIT6 vote raise VS2 voltage */
23*31a69d9aSYidi Lin 		PMIC_BUCK_VOTER_EN(MT6363, VS2, VOTER_EN_LO_BIT6, VOTER_EN_SET);
24*31a69d9aSYidi Lin 
25*31a69d9aSYidi Lin 		/* VS2 buck can not enter LPM */
26*31a69d9aSYidi Lin 		PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_ONLV);
27*31a69d9aSYidi Lin 	}
28*31a69d9aSYidi Lin }
29*31a69d9aSYidi Lin 
ufs_device_pwr_ctrl_soc(bool vcc_on,uint64_t ufs_version)30*31a69d9aSYidi Lin void ufs_device_pwr_ctrl_soc(bool vcc_on, uint64_t ufs_version)
31*31a69d9aSYidi Lin {
32*31a69d9aSYidi Lin 	if (vcc_on)
33*31a69d9aSYidi Lin 		ufs_vsx_lpm(false, ufs_version);
34*31a69d9aSYidi Lin 	else
35*31a69d9aSYidi Lin 		ufs_vsx_lpm(true, ufs_version);
36*31a69d9aSYidi Lin }
37*31a69d9aSYidi Lin 
ufs_spm_mtcmos_power(bool on)38*31a69d9aSYidi Lin int ufs_spm_mtcmos_power(bool on)
39*31a69d9aSYidi Lin {
40*31a69d9aSYidi Lin #if defined(CONFIG_MTK_MTCMOS)
41*31a69d9aSYidi Lin 	return spm_mtcmos_ctrl_ufs0(on ? STA_POWER_ON : STA_POWER_DOWN);
42*31a69d9aSYidi Lin #else
43*31a69d9aSYidi Lin 	return 0;
44*31a69d9aSYidi Lin #endif
45*31a69d9aSYidi Lin }
46*31a69d9aSYidi Lin 
ufs_phy_spm_mtcmos_power(bool on)47*31a69d9aSYidi Lin int ufs_phy_spm_mtcmos_power(bool on)
48*31a69d9aSYidi Lin {
49*31a69d9aSYidi Lin #if defined(CONFIG_MTK_MTCMOS)
50*31a69d9aSYidi Lin 	return spm_mtcmos_ctrl_ufs0_phy(on ? STA_POWER_ON : STA_POWER_DOWN);
51*31a69d9aSYidi Lin #else
52*31a69d9aSYidi Lin 	return 0;
53*31a69d9aSYidi Lin #endif
54*31a69d9aSYidi Lin }
55