xref: /rk3399_ARM-atf/plat/mediatek/drivers/ufs/mt8189/ufs_ctrl_soc.c (revision e079d66e812f4fd63a58e3409b42c4293c2b28a1)
1*260e18b1SCloud Zhang /*
2*260e18b1SCloud Zhang  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3*260e18b1SCloud Zhang  *
4*260e18b1SCloud Zhang  * SPDX-License-Identifier: BSD-3-Clause
5*260e18b1SCloud Zhang  */
6*260e18b1SCloud Zhang 
7*260e18b1SCloud Zhang #if defined(CONFIG_MTK_MTCMOS)
8*260e18b1SCloud Zhang #include <mtcmos.h>
9*260e18b1SCloud Zhang #endif
10*260e18b1SCloud Zhang #include <mtk_bl31_interface.h>
11*260e18b1SCloud Zhang 
ufs_device_pwr_ctrl_soc(bool vcc_on,uint64_t ufs_version)12*260e18b1SCloud Zhang void ufs_device_pwr_ctrl_soc(bool vcc_on, uint64_t ufs_version) {}
13*260e18b1SCloud Zhang 
ufs_spm_mtcmos_power(bool on)14*260e18b1SCloud Zhang int ufs_spm_mtcmos_power(bool on)
15*260e18b1SCloud Zhang {
16*260e18b1SCloud Zhang #if defined(CONFIG_MTK_MTCMOS)
17*260e18b1SCloud Zhang 	return spm_mtcmos_ctrl_ufs0(on ? STA_POWER_ON : STA_POWER_DOWN);
18*260e18b1SCloud Zhang #else
19*260e18b1SCloud Zhang 	return 0;
20*260e18b1SCloud Zhang #endif
21*260e18b1SCloud Zhang }
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