1*3374752fSBo-Chen Chen /* 2*3374752fSBo-Chen Chen * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3*3374752fSBo-Chen Chen * 4*3374752fSBo-Chen Chen * SPDX-License-Identifier: BSD-3-Clause 5*3374752fSBo-Chen Chen */ 6*3374752fSBo-Chen Chen #ifndef UART8250_H 7*3374752fSBo-Chen Chen #define UART8250_H 8*3374752fSBo-Chen Chen 9*3374752fSBo-Chen Chen /* UART register */ 10*3374752fSBo-Chen Chen #define UART_RBR 0x00 /* Receive buffer register */ 11*3374752fSBo-Chen Chen #define UART_DLL 0x00 /* Divisor latch lsb */ 12*3374752fSBo-Chen Chen #define UART_THR 0x00 /* Transmit holding register */ 13*3374752fSBo-Chen Chen #define UART_DLH 0x04 /* Divisor latch msb */ 14*3374752fSBo-Chen Chen #define UART_IER 0x04 /* Interrupt enable register */ 15*3374752fSBo-Chen Chen #define UART_FCR 0x08 /* FIFO control register */ 16*3374752fSBo-Chen Chen #define UART_LCR 0x0c /* Line control register */ 17*3374752fSBo-Chen Chen #define UART_MCR 0x10 /* Modem control register */ 18*3374752fSBo-Chen Chen #define UART_LSR 0x14 /* Line status register */ 19*3374752fSBo-Chen Chen #define UART_HIGHSPEED 0x24 /* High speed UART */ 20*3374752fSBo-Chen Chen 21*3374752fSBo-Chen Chen /* FCR */ 22*3374752fSBo-Chen Chen #define UART_FCR_FIFO_EN 0x01 /* enable FIFO */ 23*3374752fSBo-Chen Chen #define UART_FCR_CLEAR_RCVR 0x02 /* clear the RCVR FIFO */ 24*3374752fSBo-Chen Chen #define UART_FCR_CLEAR_XMIT 0x04 /* clear the XMIT FIFO */ 25*3374752fSBo-Chen Chen 26*3374752fSBo-Chen Chen /* LCR */ 27*3374752fSBo-Chen Chen #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ 28*3374752fSBo-Chen Chen #define UART_LCR_DLAB 0x80 /* divisor latch access bit */ 29*3374752fSBo-Chen Chen 30*3374752fSBo-Chen Chen /* MCR */ 31*3374752fSBo-Chen Chen #define UART_MCR_DTR 0x01 32*3374752fSBo-Chen Chen #define UART_MCR_RTS 0x02 33*3374752fSBo-Chen Chen 34*3374752fSBo-Chen Chen /* LSR */ 35*3374752fSBo-Chen Chen #define UART_LSR_DR 0x01 /* Data ready */ 36*3374752fSBo-Chen Chen #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ 37*3374752fSBo-Chen Chen 38*3374752fSBo-Chen Chen #endif /* UART8250_H */ 39