1*3374752fSBo-Chen Chen /* 2*3374752fSBo-Chen Chen * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. 3*3374752fSBo-Chen Chen * 4*3374752fSBo-Chen Chen * SPDX-License-Identifier: BSD-3-Clause 5*3374752fSBo-Chen Chen */ 6*3374752fSBo-Chen Chen 7*3374752fSBo-Chen Chen #ifndef MT_TIMER_H 8*3374752fSBo-Chen Chen #define MT_TIMER_H 9*3374752fSBo-Chen Chen 10*3374752fSBo-Chen Chen #define SYSTIMER_BASE (0x10017000) 11*3374752fSBo-Chen Chen #define CNTCR_REG (SYSTIMER_BASE + 0x0) 12*3374752fSBo-Chen Chen #define CNTSR_REG (SYSTIMER_BASE + 0x4) 13*3374752fSBo-Chen Chen #define CNTSYS_L_REG (SYSTIMER_BASE + 0x8) 14*3374752fSBo-Chen Chen #define CNTSYS_H_REG (SYSTIMER_BASE + 0xc) 15*3374752fSBo-Chen Chen #define CNTWACR_REG (SYSTIMER_BASE + 0x10) 16*3374752fSBo-Chen Chen #define CNTRACR_REG (SYSTIMER_BASE + 0x14) 17*3374752fSBo-Chen Chen 18*3374752fSBo-Chen Chen #define TIEO_EN (1 << 3) 19*3374752fSBo-Chen Chen #define COMP_15_EN (1 << 10) 20*3374752fSBo-Chen Chen #define COMP_20_EN (1 << 11) 21*3374752fSBo-Chen Chen #define COMP_25_EN (1 << 12) 22*3374752fSBo-Chen Chen 23*3374752fSBo-Chen Chen #define COMP_FEATURE_MASK (COMP_15_EN | COMP_20_EN | COMP_25_EN | TIEO_EN) 24*3374752fSBo-Chen Chen #define COMP_15_MASK (COMP_15_EN) 25*3374752fSBo-Chen Chen #define COMP_20_MASK (COMP_20_EN | TIEO_EN) 26*3374752fSBo-Chen Chen #define COMP_25_MASK (COMP_20_EN | COMP_25_EN) 27*3374752fSBo-Chen Chen 28*3374752fSBo-Chen Chen #define CNT_WRITE_ACCESS_CTL_MASK (0x3FFFFF0U) 29*3374752fSBo-Chen Chen #define CNT_READ_ACCESS_CTL_MASK (0x3FFFFFFU) 30*3374752fSBo-Chen Chen 31*3374752fSBo-Chen Chen void sched_clock_init(uint64_t normal_base, uint64_t atf_base); 32*3374752fSBo-Chen Chen uint64_t sched_clock(void); 33*3374752fSBo-Chen Chen void mt_systimer_init(void); 34*3374752fSBo-Chen Chen 35*3374752fSBo-Chen Chen #endif /* MT_TIMER_H */ 36