1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef THERMAL_LVTS_H 8 #define THERMAL_LVTS_H 9 10 /* Definition or macro function */ 11 #define LK_LVTS_MAGIC (0x0000555) 12 #define TFA_LVTS_MAGIC (0x0000777) 13 14 #define THERMAL_TEMP_INVALID (-274000) 15 16 #define DEVICE_ACCESS_START_BIT (24) 17 18 #define DISABLE_THERMAL_HW_REBOOT (-274000) 19 20 #define CLOCK_26MHZ_CYCLE_NS (38) 21 22 #define FEATURE_DEVICE_AUTO_RCK (BIT(0)) 23 24 #define IS_ENABLE(lvts_data, feature) \ 25 (lvts_data->feature_bitmap & feature) 26 27 #define GET_BASE_ADDR(lvts_data, tc_id) \ 28 (lvts_data->domain[lvts_data->tc[tc_id].domain_index].base \ 29 + lvts_data->tc[tc_id].addr_offset) 30 31 #define SET_TC_SPEED_IN_US(pu, gd, fd, sd) \ 32 { \ 33 .period_unit = ((pu * 1000) / (256 * CLOCK_26MHZ_CYCLE_NS)), \ 34 .group_interval_delay = (gd / pu), \ 35 .filter_interval_delay = (fd / pu), \ 36 .sensor_interval_delay = (sd / pu), \ 37 } 38 39 #define GET_CAL_BITMASK(lvts_data, index, h, l) \ 40 ((index < lvts_data->num_efuse_addr) \ 41 ? ((lvts_data->efuse[index] & GENMASK(h, l)) >> l) \ 42 : 0) 43 44 45 /* LVTS HW filter settings 46 * 000: Get one sample 47 * 001: Get 2 samples and average them 48 * 010: Get 4 samples, drop max and min, then average the rest of 2 samples 49 * 011: Get 6 samples, drop max and min, then average the rest of 4 samples 50 * 100: Get 10 samples, drop max and min, then average the rest of 8 samples 51 * 101: Get 18 samples, drop max and min, then average the rest of 16 samples 52 */ 53 enum lvts_hw_filter { 54 LVTS_FILTER_1, 55 LVTS_FILTER_2, 56 LVTS_FILTER_2_OF_4, 57 LVTS_FILTER_4_OF_6, 58 LVTS_FILTER_8_OF_10, 59 LVTS_FILTER_16_OF_18 60 }; 61 62 enum lvts_sensing_point { 63 SENSING_POINT0, 64 SENSING_POINT1, 65 SENSING_POINT2, 66 SENSING_POINT3, 67 ALL_SENSING_POINTS 68 }; 69 70 enum calibration_mode { 71 CALI_NT, 72 CALI_HT, 73 ALL_CALI_MODES 74 }; 75 76 /* Data structure */ 77 struct lvts_data; 78 79 struct speed_settings { 80 unsigned int period_unit; 81 unsigned int group_interval_delay; 82 unsigned int filter_interval_delay; 83 unsigned int sensor_interval_delay; 84 }; 85 86 struct formula_coeff { 87 int a[ALL_SENSING_POINTS]; 88 unsigned int golden_temp; 89 enum calibration_mode cali_mode; 90 }; 91 92 enum sensor_switch_status { 93 SEN_OFF, 94 SEN_ON 95 }; 96 97 enum controller_switch_status { 98 CTRL_OFF, 99 CTRL_ON 100 }; 101 102 struct tc_settings { 103 unsigned int domain_index; 104 uintptr_t addr_offset; 105 unsigned int num_sensor; 106 unsigned int sensor_map[ALL_SENSING_POINTS]; /* In sensor ID */ 107 enum controller_switch_status ctrl_on_off; 108 enum sensor_switch_status sensor_on_off[ALL_SENSING_POINTS]; 109 struct speed_settings tc_speed; 110 /* HW filter setting 111 * 000: Get one sample 112 * 001: Get 2 samples and average them 113 * 010: Get 4 samples, drop max&min and average the rest of 2 samples 114 * 011: Get 6 samples, drop max&min and average the rest of 4 samples 115 * 100: Get 10 samples, drop max&min and average the rest of 8 samples 116 * 101: Get 18 samples, drop max&min and average the rest of 16 samples 117 */ 118 uint32_t hw_filter; 119 /* Dominator_sensing point is used to select a sensing point 120 * and reference its temperature to trigger Thermal HW Reboot 121 * When it is ALL_SENSING_POINTS, it will select all sensing points 122 */ 123 enum lvts_sensing_point dominator_sensing_point; 124 int hw_reboot_trip_point; /* -274000: Disable HW reboot */ 125 uint32_t irq_bit; 126 struct formula_coeff coeff; 127 }; 128 129 struct sensor_cal_data { 130 unsigned int golden_temp; 131 unsigned int golden_temp_ht; 132 uint32_t cali_mode; 133 uint32_t *count_r; 134 uint32_t *count_rc; 135 uint32_t *count_rc_now; 136 uint32_t *efuse_data; 137 138 unsigned int default_golden_temp; 139 unsigned int default_golden_temp_ht; 140 uint32_t default_count_r; 141 uint32_t default_count_rc; 142 }; 143 144 struct platform_ops { 145 void (*lvts_reset)(struct lvts_data *lvts_data); 146 void (*device_identification)(struct lvts_data *lvts_data); 147 void (*get_calibration_data)(struct lvts_data *lvts_data); 148 void (*efuse_to_cal_data)(struct lvts_data *lvts_data); 149 void (*device_enable_and_init)(struct lvts_data *lvts_data); 150 void (*device_enable_auto_rck)(struct lvts_data *lvts_data); 151 int (*device_read_count_rc_n)(struct lvts_data *lvts_data); 152 void (*set_cal_data)(struct lvts_data *lvts_data); 153 void (*init_controller)(struct lvts_data *lvts_data); 154 int (*lvts_raw_to_temp)(const struct formula_coeff *co, 155 unsigned int id, unsigned int msr_raw); 156 unsigned int (*lvts_temp_to_raw)(const struct formula_coeff *co, 157 unsigned int id, int temp); 158 void (*check_cal_data)(struct lvts_data *lvts_data); 159 void (*update_coef_data)(struct lvts_data *lvts_data); 160 }; 161 162 struct power_domain { 163 uintptr_t base; /* LVTS base addresses */ 164 uintptr_t reset_base; 165 uintptr_t reset_set_offset; 166 uintptr_t reset_clr_offset; 167 uint32_t reset_set_bitnum; 168 uint32_t reset_clr_bitnum; 169 }; 170 171 struct sensor_data { 172 int temp; /* Current temperature */ 173 unsigned int msr_raw; /* MSR raw data from LVTS */ 174 }; 175 176 struct lvts_data { 177 unsigned int num_domain; 178 struct power_domain *domain; 179 180 unsigned int num_tc; /* Number of LVTS thermal controllers */ 181 struct tc_settings *tc; 182 int counting_window_us; /* LVTS device counting window */ 183 184 unsigned int num_sensor; /* Number of sensors in this platform */ 185 struct sensor_data *sen_data; 186 187 struct platform_ops ops; 188 int feature_bitmap; /* Show what features are enabled */ 189 190 unsigned int num_efuse_addr; 191 uint32_t *efuse; 192 193 uint32_t *irq_bitmap; 194 195 struct sensor_cal_data cal_data; 196 int enable_dump_log; 197 bool init_done; 198 }; 199 200 /* LVTS device register */ 201 #define RG_TSFM_CTRL_0 0x03 202 #define RG_TSFM_CTRL_3 0x06 203 #define RG_TSV2F_CTRL_0 0x08 204 #define RG_TSV2F_CTRL_1 0x09 205 #define RG_TSV2F_CTRL_2 0x0A 206 #define RG_TSV2F_CTRL_3 0x0B 207 #define RG_TSV2F_CTRL_4 0x0C 208 #define RG_TSV2F_CTRL_5 0x0D 209 #define RG_TSV2F_CTRL_6 0x0E 210 #define RG_DID_LVTS 0xFC 211 #define RG_TSFM_RST 0xFF 212 213 /* LVTS controller register */ 214 #define LVTSMONCTL0_0 0x000 215 #define LVTS_SINGLE_SENSE (1UL << 9) 216 #define DISABLE_SENSING_POINT (LVTS_SINGLE_SENSE | 0x0) 217 #define LVTSMONCTL1_0 0x004 218 #define LVTSMONCTL2_0 0x008 219 #define LVTSMONINT_0 0x00C 220 #define STAGE3_INT_EN (1UL << 31) 221 222 #define HIGH_OFFSET3_INT_EN (1UL << 25) 223 #define HIGH_OFFSET2_INT_EN (1UL << 13) 224 #define HIGH_OFFSET1_INT_EN (1UL << 8) 225 #define HIGH_OFFSET0_INT_EN (1UL << 3) 226 227 #define LOW_OFFSET3_INT_EN (1UL << 24) 228 #define LOW_OFFSET2_INT_EN (1UL << 12) 229 #define LOW_OFFSET1_INT_EN (1UL << 7) 230 #define LOW_OFFSET0_INT_EN (1UL << 2) 231 232 #define LVTSOFFSETH_0 0x030 233 #define LVTSOFFSETL_0 0x034 234 #define LVTSMSRCTL0_0 0x038 235 #define LVTSMSRCTL1_0 0x03C 236 #define LVTSTSSEL_0 0x040 237 #define LVTSCALSCALE_0 0x048 238 #define SET_CALC_SCALE_RULES 0x00000300 239 #define LVTS_ID_0 0x04C 240 #define LVTS_CONFIG_0 0x050 241 #define LVTSEDATA00_0 0x054 242 #define MRS_RAW_MASK GENMASK(15, 0) 243 #define LVTSRDATA0_0 0x0B0 244 #define LVTSPROTCTL_0 0x0C0 245 #define PROTOFFSET GENMASK(15, 0) 246 #define LVTSPROTTC_0 0x0CC 247 #define LVTSCLKEN_0 0x0E4 248 #define ENABLE_LVTS_CTRL_CLK (1) 249 #define LVTSSPARE0_0 0x0F0 250 251 #define BROADCAST_ID_UPDATE (1UL << 26) 252 #define DEVICE_SENSING_STATUS (1UL << 25) 253 #define DEVICE_ACCESS_STARTUS (1UL << 24) 254 #define WRITE_ACCESS (1UL << 16) 255 256 #define DEVICE_WRITE (1UL << 31 | 1UL << 30 | DEVICE_ACCESS_STARTUS \ 257 | 1UL << 17 | WRITE_ACCESS) 258 259 260 #define DEVICE_READ (1UL << 31 | 1UL << 30 | DEVICE_ACCESS_STARTUS \ 261 | 1UL << 17) 262 #define RESET_ALL_DEVICES (DEVICE_WRITE | RG_TSFM_RST << 8 | 0xFF) 263 #define READ_BACK_DEVICE_ID (1UL << 31 | 1UL << 30 | BROADCAST_ID_UPDATE \ 264 | DEVICE_ACCESS_STARTUS | 1UL << 17 \ 265 | RG_DID_LVTS << 8) 266 267 #define READ_DEVICE_REG(reg_idx) (DEVICE_READ | reg_idx << 8 | 0x00) 268 269 /* LVTS register mask */ 270 #define INIT_FOOTPRINT_ADDR_OFFSET (0x1F8) 271 #define CLOSE_FOOTPRINT_ADDR_OFFSET (0x1FC) 272 #define NO_IDLE_COUNT_ADDR_OFFSET (0x1E4) 273 274 void thermal_clock_open(void); 275 void thermal_clock_close(void); 276 void set_polling_speed(struct lvts_data *lvts_data, unsigned int tc_id); 277 void set_hw_filter(struct lvts_data *lvts_data, unsigned int tc_id); 278 void lvts_write_all_device(struct lvts_data *lvts_data, uint32_t data); 279 void lvts_write_device(struct lvts_data *lvts_data, uint32_t data, 280 unsigned int tc_id); 281 uint32_t lvts_read_device(struct lvts_data *lvts_data, uint32_t reg_idx, 282 unsigned int tc_id); 283 void set_calibration_data_v1(struct lvts_data *lvts_data); 284 unsigned int get_dominator_index(struct lvts_data *lvts_data, 285 unsigned int tc_id); 286 void disable_hw_reboot_interrupt(struct lvts_data *lvts_data, 287 unsigned int tc_id); 288 void enable_hw_reboot_interrupt(struct lvts_data *lvts_data, 289 unsigned int tc_id); 290 void set_tc_hw_reboot_threshold(struct lvts_data *lvts_data, int trip_point, 291 unsigned int tc_id); 292 293 extern struct lvts_data lvts_data_instance; 294 295 #endif /* THERMAL_LVTS_H */ 296