1*adf73ae2SHope Wang /* 2*adf73ae2SHope Wang * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3*adf73ae2SHope Wang * 4*adf73ae2SHope Wang * SPDX-License-Identifier: BSD-3-Clause 5*adf73ae2SHope Wang */ 6*adf73ae2SHope Wang 7*adf73ae2SHope Wang #ifndef SPMI_COMMON_H 8*adf73ae2SHope Wang #define SPMI_COMMON_H 9*adf73ae2SHope Wang 10*adf73ae2SHope Wang #include <stdint.h> 11*adf73ae2SHope Wang 12*adf73ae2SHope Wang #include <platform_def.h> 13*adf73ae2SHope Wang #include "pmif_common.h" 14*adf73ae2SHope Wang 15*adf73ae2SHope Wang /* Read/write byte limitation */ 16*adf73ae2SHope Wang #define PMIF_BYTECNT_MAX 2 17*adf73ae2SHope Wang 18*adf73ae2SHope Wang #define SPMI_GROUP_ID 0xB 19*adf73ae2SHope Wang 20*adf73ae2SHope Wang /* enum marco for cmd/channel */ 21*adf73ae2SHope Wang enum spmi_master { 22*adf73ae2SHope Wang SPMI_MASTER_0 = 0, 23*adf73ae2SHope Wang SPMI_MASTER_1, 24*adf73ae2SHope Wang SPMI_MASTER_P_1, 25*adf73ae2SHope Wang SPMI_MASTER_MAX 26*adf73ae2SHope Wang }; 27*adf73ae2SHope Wang 28*adf73ae2SHope Wang enum spmi_slave { 29*adf73ae2SHope Wang SPMI_SLAVE_0 = 0, 30*adf73ae2SHope Wang SPMI_SLAVE_1, 31*adf73ae2SHope Wang SPMI_SLAVE_2, 32*adf73ae2SHope Wang SPMI_SLAVE_3, 33*adf73ae2SHope Wang SPMI_SLAVE_4, 34*adf73ae2SHope Wang SPMI_SLAVE_5, 35*adf73ae2SHope Wang SPMI_SLAVE_6, 36*adf73ae2SHope Wang SPMI_SLAVE_7, 37*adf73ae2SHope Wang SPMI_SLAVE_8, 38*adf73ae2SHope Wang SPMI_SLAVE_9, 39*adf73ae2SHope Wang SPMI_SLAVE_10, 40*adf73ae2SHope Wang SPMI_SLAVE_11, 41*adf73ae2SHope Wang SPMI_SLAVE_12, 42*adf73ae2SHope Wang SPMI_SLAVE_13, 43*adf73ae2SHope Wang SPMI_SLAVE_14, 44*adf73ae2SHope Wang SPMI_SLAVE_15, 45*adf73ae2SHope Wang SPMI_MAX_SLAVE_ID 46*adf73ae2SHope Wang }; 47*adf73ae2SHope Wang 48*adf73ae2SHope Wang enum slv_type { 49*adf73ae2SHope Wang BUCK_CPU, 50*adf73ae2SHope Wang BUCK_GPU, 51*adf73ae2SHope Wang BUCK_MD, 52*adf73ae2SHope Wang BUCK_RF, 53*adf73ae2SHope Wang MAIN_PMIC, 54*adf73ae2SHope Wang BUCK_VPU, 55*adf73ae2SHope Wang SUB_PMIC, 56*adf73ae2SHope Wang CLOCK_PMIC, 57*adf73ae2SHope Wang SECOND_PMIC, 58*adf73ae2SHope Wang SLV_TYPE_MAX 59*adf73ae2SHope Wang }; 60*adf73ae2SHope Wang 61*adf73ae2SHope Wang enum slv_type_id { 62*adf73ae2SHope Wang BUCK_RF_ID = 1, 63*adf73ae2SHope Wang BUCK_MD_ID = 3, 64*adf73ae2SHope Wang MAIN_PMIC_ID = 5, 65*adf73ae2SHope Wang BUCK_CPU_ID = 6, 66*adf73ae2SHope Wang BUCK_GPU_ID = 7, 67*adf73ae2SHope Wang BUCK_VPU_ID, 68*adf73ae2SHope Wang SUB_PMIC_ID = 10, 69*adf73ae2SHope Wang CLOCK_PMIC_ID = 11, 70*adf73ae2SHope Wang SECOND_PMIC_ID = 12, 71*adf73ae2SHope Wang SLV_TYPE_ID_MAX 72*adf73ae2SHope Wang }; 73*adf73ae2SHope Wang 74*adf73ae2SHope Wang enum { 75*adf73ae2SHope Wang SPMI_OP_ST_BUSY = 1, 76*adf73ae2SHope Wang SPMI_OP_ST_ACK = 0, 77*adf73ae2SHope Wang SPMI_OP_ST_NACK = 1 78*adf73ae2SHope Wang }; 79*adf73ae2SHope Wang 80*adf73ae2SHope Wang struct spmi_device { 81*adf73ae2SHope Wang int slvid; 82*adf73ae2SHope Wang int grpiden; 83*adf73ae2SHope Wang enum slv_type type; 84*adf73ae2SHope Wang enum slv_type_id type_id; 85*adf73ae2SHope Wang int mstid; 86*adf73ae2SHope Wang uint16_t hwcid_addr; 87*adf73ae2SHope Wang uint8_t hwcid_val; 88*adf73ae2SHope Wang uint16_t hwcid_mask; 89*adf73ae2SHope Wang uint16_t swcid_addr; 90*adf73ae2SHope Wang uint8_t swcid_val; 91*adf73ae2SHope Wang uint16_t wpk_key_addr; 92*adf73ae2SHope Wang uint16_t wpk_key_val; 93*adf73ae2SHope Wang uint16_t wpk_key_h_val; 94*adf73ae2SHope Wang uint16_t tma_key_addr; 95*adf73ae2SHope Wang uint16_t tma_key_val; 96*adf73ae2SHope Wang uint16_t tma_key_h_val; 97*adf73ae2SHope Wang uint16_t rcs_en_addr; 98*adf73ae2SHope Wang uint16_t rcs_slvid_addr; 99*adf73ae2SHope Wang struct pmif *pmif_arb; 100*adf73ae2SHope Wang }; 101*adf73ae2SHope Wang 102*adf73ae2SHope Wang int spmi_command_shutdown(int mstid, struct spmi_device *dev, unsigned int grpiden); 103*adf73ae2SHope Wang #endif 104