1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 #include <lib/utils_def.h> 9 10 #include <drivers/spmi/pmif_common.h> 11 #include <drivers/spmi/pmif_v1/pmif.h> 12 #include <drivers/spmi/spmi_common.h> 13 #include <drivers/spmi/spmi_sw.h> 14 #include <drivers/spmi_api.h> 15 #include <lib/mtk_init/mtk_init.h> 16 #include <mtk_mmap_pool.h> 17 18 #define SPMI_GROUP_ID 0xB 19 #define SPMI_DEBUG 0 20 21 static uint16_t mt6xxx_regs[] = { 22 [PMIF_INIT_DONE] = 0x0000, 23 [PMIF_INF_EN] = 0x0024, 24 [PMIF_ARB_EN] = 0x0150, 25 [PMIF_IRQ_EVENT_EN_0] = 0x0420, 26 [PMIF_IRQ_FLAG_0] = 0x0428, 27 [PMIF_IRQ_CLR_0] = 0x042C, 28 [PMIF_IRQ_EVENT_EN_2] = 0x0440, 29 [PMIF_IRQ_FLAG_2] = 0x0448, 30 [PMIF_IRQ_CLR_2] = 0x044C, 31 [PMIF_WDT_CTRL] = 0x0470, 32 [PMIF_WDT_EVENT_EN_1] = 0x047C, 33 [PMIF_WDT_FLAG_1] = 0x0480, 34 [PMIF_SWINF_2_ACC] = 0x0880, 35 [PMIF_SWINF_2_WDATA_31_0] = 0x0884, 36 [PMIF_SWINF_2_WDATA_63_32] = 0x0888, 37 [PMIF_SWINF_2_RDATA_31_0] = 0x0894, 38 [PMIF_SWINF_2_RDATA_63_32] = 0x0898, 39 [PMIF_SWINF_2_VLD_CLR] = 0x08A4, 40 [PMIF_SWINF_2_STA] = 0x08A8, 41 [PMIF_SWINF_3_ACC] = 0x08C0, 42 [PMIF_SWINF_3_WDATA_31_0] = 0x08C4, 43 [PMIF_SWINF_3_WDATA_63_32] = 0x08C8, 44 [PMIF_SWINF_3_RDATA_31_0] = 0x08D4, 45 [PMIF_SWINF_3_RDATA_63_32] = 0x08D8, 46 [PMIF_SWINF_3_VLD_CLR] = 0x08E4, 47 [PMIF_SWINF_3_STA] = 0x08E8, 48 /* hw mpu */ 49 [PMIF_PMIC_ALL_RGN_EN_1] = 0x09B0, 50 [PMIF_PMIC_ALL_RGN_EN_2] = 0x0D30, 51 [PMIF_PMIC_ALL_RGN_0_START] = 0x09B4, 52 [PMIF_PMIC_ALL_RGN_0_END] = 0x09B8, 53 [PMIF_PMIC_ALL_RGN_1_START] = 0x09BC, 54 [PMIF_PMIC_ALL_RGN_1_END] = 0x09C0, 55 [PMIF_PMIC_ALL_RGN_2_START] = 0x09C4, 56 [PMIF_PMIC_ALL_RGN_2_END] = 0x09C8, 57 [PMIF_PMIC_ALL_RGN_3_START] = 0x09CC, 58 [PMIF_PMIC_ALL_RGN_3_END] = 0x09D0, 59 [PMIF_PMIC_ALL_RGN_31_START] = 0x0D34, 60 [PMIF_PMIC_ALL_RGN_31_END] = 0x0D38, 61 [PMIF_PMIC_ALL_INVLD_SLVID] = 0x0AAC, 62 [PMIF_PMIC_ALL_RGN_0_PER0] = 0x0AB0, 63 [PMIF_PMIC_ALL_RGN_0_PER1] = 0x0AB4, 64 [PMIF_PMIC_ALL_RGN_1_PER0] = 0x0AB8, 65 [PMIF_PMIC_ALL_RGN_2_PER0] = 0x0AC0, 66 [PMIF_PMIC_ALL_RGN_3_PER0] = 0x0AC8, 67 [PMIF_PMIC_ALL_RGN_31_PER0] = 0x0E34, 68 [PMIF_PMIC_ALL_RGN_31_PER1] = 0x0E38, 69 [PMIF_PMIC_ALL_RGN_OTHERS_PER0] = 0x0BA8, 70 [PMIF_PMIC_ALL_RGN_OTHERS_PER1] = 0x0BAC, 71 }; 72 73 static uint16_t mt6xxx_spmi_regs[] = { 74 [SPMI_OP_ST_CTRL] = 0x0000, 75 [SPMI_GRP_ID_EN] = 0x0004, 76 [SPMI_OP_ST_STA] = 0x0008, 77 [SPMI_MST_SAMPL] = 0x000c, 78 [SPMI_MST_REQ_EN] = 0x0010, 79 [SPMI_RCS_CTRL] = 0x0014, 80 [SPMI_SLV_3_0_EINT] = 0x0020, 81 [SPMI_SLV_7_4_EINT] = 0x0024, 82 [SPMI_SLV_B_8_EINT] = 0x0028, 83 [SPMI_SLV_F_C_EINT] = 0x002c, 84 [SPMI_REC_CTRL] = 0x0040, 85 [SPMI_REC0] = 0x0044, 86 [SPMI_REC1] = 0x0048, 87 [SPMI_REC2] = 0x004c, 88 [SPMI_REC3] = 0x0050, 89 [SPMI_REC4] = 0x0054, 90 [SPMI_REC_CMD_DEC] = 0x005c, 91 [SPMI_DEC_DBG] = 0x00f8, 92 [SPMI_MST_DBG] = 0x00fc, 93 }; 94 95 struct pmif pmif_spmi_arb[] = { 96 { 97 .regs = mt6xxx_regs, 98 .spmimst_regs = mt6xxx_spmi_regs, 99 .mstid = SPMI_MASTER_0, 100 .read_cmd = pmif_spmi_read_cmd, 101 .write_cmd = pmif_spmi_write_cmd, 102 }, 103 { 104 .regs = mt6xxx_regs, 105 .spmimst_regs = mt6xxx_spmi_regs, 106 .mstid = SPMI_MASTER_1, 107 .read_cmd = pmif_spmi_read_cmd, 108 .write_cmd = pmif_spmi_write_cmd, 109 }, 110 { 111 .base = (unsigned int *)PMIF_SPMI_P_BASE, 112 .regs = mt6xxx_regs, 113 .spmimst_base = (unsigned int *)SPMI_MST_P_BASE, 114 .spmimst_regs = mt6xxx_spmi_regs, 115 .mstid = SPMI_MASTER_P_1, 116 .read_cmd = pmif_spmi_read_cmd, 117 .write_cmd = pmif_spmi_write_cmd, 118 }, 119 }; 120 121 static struct spmi_device spmi_dev[] = { 122 { 123 .slvid = SPMI_SLAVE_7, /* MT6319 */ 124 .grpiden = 0x800, 125 .type = BUCK_CPU, 126 .type_id = BUCK_CPU_ID, 127 .mstid = SPMI_MASTER_P_1,/* spmi-p */ 128 .hwcid_addr = 0x09, 129 .hwcid_val = 0x15, 130 .swcid_addr = 0x0B, 131 .swcid_val = 0x15, 132 .wpk_key_addr = 0x3A8, 133 .wpk_key_val = 0x6315, 134 .tma_key_addr = 0x39F, 135 .tma_key_val = 0x9CEA, 136 .pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1], 137 }, 138 { 139 .slvid = SPMI_SLAVE_8, /* MT6319 */ 140 .grpiden = 0x800, 141 .type = BUCK_CPU, 142 .type_id = BUCK_CPU_ID, 143 .mstid = SPMI_MASTER_P_1,/* spmi-p */ 144 .hwcid_addr = 0x09, 145 .hwcid_val = 0x15, 146 .swcid_addr = 0x0B, 147 .swcid_val = 0x15, 148 .wpk_key_addr = 0x3A8, 149 .wpk_key_val = 0x6315, 150 .tma_key_addr = 0x39F, 151 .tma_key_val = 0x9CEA, 152 .pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1], 153 }, 154 }; 155 156 int platform_pmif_spmi_init(void) 157 { 158 /* 159 * The MT8189 chipset comes in two variants: MT8189G and MT8189H. The 160 * MT8189G variant uses a single PMIC IC (MT6319), whereas the MT8189H 161 * variant uses two PMIC ICs. To ensure driver compatibility, we utilize 162 * the CPU ID and segment ID to accurately determine the required number 163 * of SPMIF instances. 164 */ 165 if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 && 166 mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189G) 167 spmi_device_register(spmi_dev, 1); 168 else 169 spmi_device_register(spmi_dev, ARRAY_SIZE(spmi_dev)); 170 171 return 0; 172 } 173 MTK_ARCH_INIT(platform_pmif_spmi_init); 174