1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_COMMON_V1_H 8 #define MT_SPM_COMMON_V1_H 9 10 #include <common/debug.h> 11 12 struct spm_hwcg_info { 13 uint32_t pwr; 14 uint32_t pwr_msb; 15 uint32_t module_busy; 16 }; 17 18 #define HWCG_INFO_INIT(_info) \ 19 ({ _info.pwr = _info.pwr_msb = _info.module_busy = 0; }) 20 21 #define DECLARE_HWCG_REG(_name_, _info) ({ \ 22 _info.pwr = REG_PWR_STATUS_##_name_##_REQ_MASK; \ 23 _info.pwr_msb = REG_PWR_STATUS_MSB_##_name_##_REQ_MASK; \ 24 _info.module_busy = REG_MODULE_BUSY_##_name_##_REQ_MASK; }) 25 26 #define DECLARE_HWCG_DEFAULT(_name_, _info) ({ \ 27 _info.pwr = SPM_HWCG_##_name_##_PWR_MB; \ 28 _info.pwr_msb = SPM_HWCG_##_name_##_PWR_MSB_MB; \ 29 _info.module_busy = SPM_HWCG_##_name_##_MODULE_BUSY_MB; }) 30 31 #define PERI_REQ_EN_INFO_INIT(_info) ({ _info.req_en = 0; }) 32 33 #define PERI_REQ_STA_INFO_INIT(_info) ({ _info.req_sta = 0; }) 34 35 #define DECLARE_PERI_REQ_EN_REG(_offset, _info) \ 36 ({ _info.req_en = REG_PERI_REQ_EN(_offset); }) 37 38 #define DECLARE_PERI_REQ_STA_REG(_offset, _info) \ 39 ({ _info.req_sta = REG_PERI_REQ_STA(_offset); }) 40 41 #define DECLARE_PERI_REQ_DEFAULT(_name_, _info) \ 42 ({ _info.req_en = PERI_REQ_##_name_##_MB; }) 43 44 #define CTRL0_SC_26M_CK_OFF BIT(0) 45 #define CTRL0_SC_VLP_BUS_CK_OFF BIT(1) 46 #define CTRL0_SC_PMIF_CK_OFF BIT(2) 47 #define CTRL0_SC_AXI_CK_OFF BIT(3) 48 #define CTRL0_SC_AXI_MEM_CK_OFF BIT(4) 49 #define CTRL0_SC_MD26M_CK_OFF BIT(5) 50 #define CTRL0_SC_MD32K_CK_OFF BIT(6) 51 #define CTRL0_SC_VLP_26M_CLK_SEL BIT(7) 52 #define CTRL0_SC_26M_CK_SEL BIT(8) 53 #define CTRL0_SC_TOP_26M_CLK_SEL BIT(9) 54 #define CTRL0_SC_SYS_TIMER_CLK_32K_SEL BIT(10) 55 #define CTRL0_SC_CIRQ_CLK_32K_SEL BIT(11) 56 #define CTRL0_SC_AXI_DCM_DIS BIT(12) 57 #define CTRL0_SC_CKSQ0_OFF BIT(13) 58 #define CTRL0_SC_CKSQ1_OFF BIT(14) 59 #define CTRL0_VCORE_PWR_ISO BIT(15) 60 #define CTRL0_VCORE_PWR_ISO_PRE BIT(16) 61 #define CTRL0_VCORE_PWR_RST_B BIT(17) 62 #define CTRL0_VCORE_RESTORE_ENABLE BIT(18) 63 #define CTRL0_SC_TOP_RESTORE_26M_CLK_SEL BIT(19) 64 #define CTRL0_AOC_VCORE_SRAM_ISO_DIN BIT(20) 65 #define CTRL0_AOC_VCORE_SRAM_LATCH_ENB BIT(21) 66 #define CTRL0_AOC_VCORE_ANA_ISO BIT(22) 67 #define CTRL0_AOC_VCORE_ANA_ISO_PRE BIT(23) 68 #define CTRL0_AOC_VLPTOP_SRAM_ISO_DIN BIT(24) 69 #define CTRL0_AOC_VLPTOP_SRAM_LATCH_ENB BIT(25) 70 #define CTRL0_AOC_VCORE_IO_ISO BIT(26) 71 #define CTRL0_AOC_VCORE_IO_LATCH_ENB BIT(27) 72 #define CTRL0_RTFF_VCORE_SAVE BIT(28) 73 #define CTRL0_RTFF_VCORE_NRESTORE BIT(29) 74 #define CTRL0_RTFF_VCORE_CLK_DIS BIT(30) 75 76 /* MD32PCM_CTRL1 define */ 77 #define CTRL1_PWRAP_SLEEP_REQ BIT(0) 78 #define CTRL1_IM_SLP_EN BIT(1) 79 #define CTRL1_SPM_LEAVE_VCORE_OFF_REQ BIT(2) 80 #define CTRL1_SPM_CK_SEL0 BIT(4) 81 #define CTRL1_SPM_CK_SEL1 BIT(5) 82 #define CTRL1_TIMER_SET BIT(6) 83 #define CTRL1_TIMER_CLR BIT(7) 84 #define CTRL1_SPM_LEAVE_DEEPIDLE_REQ BIT(8) 85 #define CTRL1_SPM_LEAVE_SUSPEND_REQ BIT(9) 86 #define CTRL1_CSYSPWRUPACK BIT(10) 87 #define CTRL1_SRCCLKENO0 BIT(11) 88 #define CTRL1_SRCCLKENO1 BIT(12) 89 #define CTRL1_SRCCLKENO2 BIT(13) 90 #define CTRL1_SPM_APSRC_INTERNAL_ACK BIT(14) 91 #define CTRL1_SPM_EMI_INTERNAL_ACK BIT(15) 92 #define CTRL1_SPM_DDREN_INTERNAL_ACK BIT(16) 93 #define CTRL1_SPM_INFRA_INTERNAL_ACK BIT(17) 94 #define CTRL1_SPM_VRF18_INTERNAL_ACK BIT(18) 95 #define CTRL1_SPM_VCORE_INTERNAL_ACK BIT(19) 96 #define CTRL1_SPM_VCORE_RESTORE_ACK BIT(20) 97 #define CTRL1_SPM_PMIC_INTERNAL_ACK BIT(21) 98 #define CTRL1_PMIC_IRQ_REQ_EN BIT(22) 99 #define CTRL1_WDT_KICK_P BIT(23) 100 #define CTRL1_FORCE_DDREN_WAKE BIT(24) 101 #define CTRL1_FORCE_F26M_WAKE BIT(25) 102 #define CTRL1_FORCE_APSRC_WAKE BIT(26) 103 #define CTRL1_FORCE_INFRA_WAKE BIT(27) 104 #define CTRL1_FORCE_VRF18_WAKE BIT(28) 105 #define CTRL1_FORCE_VCORE_WAKE BIT(29) 106 #define CTRL1_FORCE_EMI_WAKE BIT(30) 107 #define CTRL1_FORCE_PMIC_WAKE BIT(31) 108 109 /* MD32PCM_CTRL2 define (PCM_REG2_DATA) */ 110 #define CTRL2_MD32PCM_IRQ_TRIG_BIT BIT(31) 111 112 /* MD32PCM_STA0 define */ 113 #define STA0_SRCCLKENI0 BIT(0) 114 #define STA0_SRCCLKENI1 BIT(1) 115 #define STA0_MD_SRCCLKENA BIT(2) 116 #define STA0_MD_SRCCLKENA1 BIT(3) 117 #define STA0_MD_DDREN_REQ BIT(4) 118 #define STA0_CONN_DDREN_REQ BIT(5) 119 #define STA0_SSPM_SRCCLKENA BIT(6) 120 #define STA0_SSPM_APSRC_REQ BIT(7) 121 #define STA0_MD_STATE BIT(8) 122 #define STA0_RC2SPM_SRCCLKENO_0_ACK BIT(9) 123 #define STA0_MM_STATE BIT(10) 124 #define STA0_SSPM_STATE BIT(11) 125 #define STA0_CPUEB_STATE BIT(12) 126 #define STA0_CONN_STATE BIT(13) 127 #define STA0_CONN_VCORE_REQ BIT(14) 128 #define STA0_CONN_SRCCLKENA BIT(15) 129 #define STA0_CONN_SRCCLKENB BIT(16) 130 #define STA0_CONN_APSRC_REQ BIT(17) 131 #define STA0_SCP_STATE BIT(18) 132 #define STA0_CSYSPWRUPREQ BIT(19) 133 #define STA0_PWRAP_SLEEP_ACK BIT(20) 134 #define STA0_DPM_STATE BIT(21) 135 #define STA0_AUDIO_DSP_STATE BIT(22) 136 #define STA0_PMIC_IRQ_ACK BIT(23) 137 #define STA0_RESERVED_BIT_24 BIT(24) 138 #define STA0_RESERVED_BIT_25 BIT(25) 139 #define STA0_RESERVED_BIT_26 BIT(26) 140 #define STA0_DVFS_STATE BIT(27) 141 #define STA0_RESERVED_BIT_28 BIT(28) 142 #define STA0_RESERVED_BIT_29 BIT(29) 143 #define STA0_SC_HW_S1_ACK_ALL BIT(30) 144 #define STA0_DDREN_STATE BIT(31) 145 146 #define R12_PCM_TIMER_B BIT(0) 147 #define R12_TWAM_PMSR_DVFSRC_ALCO BIT(1) 148 #define R12_KP_IRQ_B BIT(2) 149 #define R12_APWDT_EVENT_B BIT(3) 150 #define R12_APXGPT_EVENT_B BIT(4) 151 #define R12_CONN2AP_WAKEUP_B BIT(5) 152 #define R12_EINT_EVENT_B BIT(6) 153 #define R12_CONN_WDT_IRQ_B BIT(7) 154 #define R12_CCIF0_EVENT_B BIT(8) 155 #define R12_CCIF1_EVENT_B BIT(9) 156 #define R12_SSPM2SPM_WAKEUP_B BIT(10) 157 #define R12_SCP2SPM_WAKEUP_B BIT(11) 158 #define R12_ADSP2SPM_WAKEUP_B BIT(12) 159 #define R12_PCM_WDT_WAKEUP_B BIT(13) 160 #define R12_USB0_CDSC_B BIT(14) 161 #define R12_USB0_POWERDWN_B BIT(15) 162 #define R12_UART_EVENT_B BIT(16) 163 #define R12_DEBUGTOP_FLAG_IRQ_B BIT(17) 164 #define R12_SYS_TIMER_EVENT_B BIT(18) 165 #define R12_EINT_EVENT_SECURE_B BIT(19) 166 #define R12_AFE_IRQ_MCU_B BIT(20) 167 #define R12_THERM_CTRL_EVENT_B BIT(21) 168 #define R12_SYS_CIRQ_IRQ_B BIT(22) 169 #define R12_PBUS_EVENT_B BIT(23) 170 #define R12_CSYSPWREQ_B BIT(24) 171 #define R12_MD_WDT_B BIT(25) 172 #define R12_AP2AP_PEER_WAKEUP_B BIT(26) 173 #define R12_SEJ_B BIT(27) 174 #define R12_CPU_WAKEUP BIT(28) 175 #define R12_APUSYS_WAKE_HOST_B BIT(29) 176 #define R12_PCIE_WAKE_B BIT(30) 177 #define R12_MSDC_WAKE_B BIT(31) 178 179 /* PCM_PWR_IO_EN */ 180 #define PCM_PWRIO_EN_R0 BIT(0) 181 #define PCM_PWRIO_EN_R7 BIT(7) 182 #define PCM_RF_SYNC_R0 BIT(16) 183 #define PCM_RF_SYNC_R6 BIT(22) 184 #define PCM_RF_SYNC_R7 BIT(23) 185 186 /* SPM_SWINT */ 187 #define PCM_SW_INT0 BIT(0) 188 #define PCM_SW_INT1 BIT(1) 189 #define PCM_SW_INT2 BIT(2) 190 #define PCM_SW_INT3 BIT(3) 191 #define PCM_SW_INT4 BIT(4) 192 #define PCM_SW_INT5 BIT(5) 193 #define PCM_SW_INT6 BIT(6) 194 #define PCM_SW_INT7 BIT(7) 195 #define PCM_SW_INT8 BIT(8) 196 #define PCM_SW_INT9 BIT(9) 197 198 #define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ 199 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ 200 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ 201 PCM_SW_INT0) 202 203 /* SPM_AP_STANDBY_CON */ 204 #define WFI_OP_AND 1 205 #define WFI_OP_OR 0 206 207 /* SPM_IRQ_MASK */ 208 #define ISRM_TWAM BIT(2) 209 #define ISRM_PCM_RETURN BIT(3) 210 #define ISRM_RET_IRQ0 BIT(8) 211 #define ISRM_RET_IRQ1 BIT(9) 212 #define ISRM_RET_IRQ2 BIT(10) 213 #define ISRM_RET_IRQ3 BIT(11) 214 #define ISRM_RET_IRQ4 BIT(12) 215 #define ISRM_RET_IRQ5 BIT(13) 216 #define ISRM_RET_IRQ6 BIT(14) 217 #define ISRM_RET_IRQ7 BIT(15) 218 #define ISRM_RET_IRQ8 BIT(16) 219 #define ISRM_RET_IRQ9 BIT(17) 220 #define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \ 221 (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \ 222 (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \ 223 (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \ 224 (ISRM_RET_IRQ1)) 225 #define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) 226 #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) 227 228 /* SPM_IRQ_STA */ 229 #define ISRS_TWAM BIT(2) 230 #define ISRS_PCM_RETURN BIT(3) 231 #define ISRC_TWAM ISRS_TWAM 232 #define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN 233 #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) 234 235 /* SPM_WAKEUP_MISC */ 236 #define WAKE_MISC_GIC_WAKEUP 0x3FF /* bit0 ~ bit9 */ 237 #define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB 238 #define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB 239 #define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB 240 #define WAKE_MISC_PMIC_OUT_B (BIT(19) | BIT(20)) 241 #define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB 242 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB 243 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB 244 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB 245 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB 246 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB 247 #define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB 248 #define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB 249 250 #define SPM_INTERNAL_STATUS_HW_S1 BIT(0) 251 252 /* Signal that monitor by HW CG */ 253 enum spm_hwcg_setting { 254 HWCG_PWR, 255 HWCG_PWR_MSB, 256 HWCG_MODULE_BUSY, 257 HWCG_SETTING_MAX 258 }; 259 260 enum spm_hwcg_sta_type { 261 HWCG_STA_DEFAULT_MASK, 262 HWCG_STA_MASK 263 }; 264 265 enum spm_peri_req_setting { 266 PERI_REQ_EN = 0, 267 PERI_REQ_SETTING_MAX 268 }; 269 270 enum spm_peri_req_sta_type { 271 PERI_REQ_STA_DEFAULT_MASK, 272 PERI_REQ_STA_MASK, 273 PERI_REQ_STA_MAX 274 }; 275 276 enum spm_peri_req_status { 277 PERI_RES_REQ_EN, 278 PERI_REQ_STATUS_MAX 279 }; 280 281 enum spm_peri_req_status_raw { 282 PERI_REQ_STATUS_RAW_NUM, 283 PERI_REQ_STATUS_RAW_NAME, 284 PERI_REQ_STATUS_RAW_STA, 285 PERI_REQ_STATUS_RAW_MAX 286 }; 287 288 #define MT_SPM_HW_CG_STA_INIT(_x) ({ if (_x) _x->sta = 0; }) 289 290 struct spm_peri_req_sta { 291 uint32_t sta; 292 }; 293 294 struct spm_peri_req_info { 295 uint32_t req_en; 296 uint32_t req_sta; 297 }; 298 299 struct spm_hwcg_sta { 300 uint32_t sta; 301 }; 302 303 void spm_hwreq_init(void); 304 305 /* Res: 306 * Please refer the mt_spm_resource_req.h. 307 * Section of SPM resource request internal bit_mask. 308 */ 309 void spm_hwcg_ctrl(uint32_t res, enum spm_hwcg_setting type, 310 uint32_t is_set, uint32_t val); 311 312 /* Idx: 313 * index of HWCG setting. 314 */ 315 void spm_hwcg_ctrl_by_index(uint32_t idx, enum spm_hwcg_setting type, 316 uint32_t is_set, uint32_t val); 317 318 /* Res: 319 * Please refer the mt_spm_resource_req.h. 320 * Section of SPM resource request internal bit_mask. 321 */ 322 int spm_hwcg_get_setting(uint32_t res, enum spm_hwcg_sta_type sta_type, 323 enum spm_hwcg_setting type, 324 struct spm_hwcg_sta *sta); 325 326 /* Idx: 327 * index of HWCG setting. 328 */ 329 int spm_hwcg_get_setting_by_index(uint32_t idx, 330 enum spm_hwcg_sta_type sta_type, 331 enum spm_hwcg_setting type, 332 struct spm_hwcg_sta *sta); 333 334 uint32_t spm_hwcg_get_status(uint32_t idx, enum spm_hwcg_setting type); 335 336 static inline uint32_t spm_hwcg_setting_num(void) 337 { 338 return HWCG_SETTING_MAX; 339 } 340 341 uint32_t spm_peri_req_get_status(uint32_t idx, enum spm_peri_req_status type); 342 uint32_t spm_peri_req_get_status_raw(enum spm_peri_req_status_raw type, 343 uint32_t idx, 344 char *name, size_t sz); 345 346 static inline uint32_t spm_peri_req_setting_num(void) 347 { 348 return PERI_REQ_SETTING_MAX; 349 } 350 351 int spm_peri_req_get_setting_by_index(uint32_t idx, 352 enum spm_peri_req_sta_type sta_type, 353 struct spm_peri_req_sta *sta); 354 355 void spm_peri_req_ctrl_by_index(uint32_t idx, 356 uint32_t is_set, uint32_t val); 357 358 int spm_peri_req_name(uint32_t idex, char *name, size_t sz); 359 360 #ifdef __GNUC__ 361 #define spm_likely(x) __builtin_expect(!!(x), 1) 362 #define spm_unlikely(x) __builtin_expect(!!(x), 0) 363 #else 364 #define spm_likely(x) (x) 365 #define spm_unlikely(x) (x) 366 #endif 367 368 /* AP_MDSRC_REQ MD 26M ON settle time (3ms) */ 369 #define AP_MDSRC_REQ_MD_26M_SETTLE 3 370 371 /* Setting the SPM settle time*/ 372 #define SPM_SYSCLK_SETTLE 0x60FE /* 1685us */ 373 374 /* Setting the SPM req/ack time*/ 375 #define SPM_ACK_TIMEOUT_US 1000 376 377 /* Settine the firmware status check for SPM PC */ 378 #define SPM_PC_CHECKABLE 379 380 enum { 381 SPM_ARGS_SPMFW_IDX_KICK = 0, 382 SPM_ARGS_SPMFW_INIT, 383 SPM_ARGS_SUSPEND, 384 SPM_ARGS_SUSPEND_FINISH, 385 SPM_ARGS_SODI, 386 SPM_ARGS_SODI_FINISH, 387 SPM_ARGS_DPIDLE, 388 SPM_ARGS_DPIDLE_FINISH, 389 SPM_ARGS_PCM_WDT, 390 SPM_ARGS_SUSPEND_CALLBACK, 391 SPM_ARGS_HARDWARE_CG_CHECK, 392 SPM_ARGS_NUM, 393 }; 394 395 typedef enum { 396 WR_NONE = 0, 397 WR_UART_BUSY, 398 WR_ABORT, 399 WR_PCM_TIMER, 400 WR_WAKE_SRC, 401 WR_DVFSRC, 402 WR_TWAM, 403 WR_PMSR, 404 WR_SPM_ACK_CHK, 405 WR_UNKNOWN, 406 } wake_reason_t; 407 408 struct pwr_ctrl; 409 410 void spm_set_irq_num(uint32_t num); 411 struct mt_lp_resource_user *get_spm_res_user(void); 412 int spm_boot_init(void); 413 void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue); 414 /* Support by bl31_plat_setup.c */ 415 uint32_t is_abnormal_boot(void); 416 417 #endif 418