xref: /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/pcm_def.h (revision b47dddd061e92054c3b2096fc8aa9688bfef68d6) 
1 /*
2  * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PCM_DEF_H
8 #define PCM_DEF_H
9 
10 #define CTRL0_SC_26M_CK_OFF			BIT(0)
11 #define CTRL0_SC_VLP_BUS_CK_OFF			BIT(1)
12 #define CTRL0_SC_PMIF_CK_OFF			BIT(2)
13 #define CTRL0_SC_AXI_CK_OFF			BIT(3)
14 #define CTRL0_SC_AXI_MEM_CK_OFF			BIT(4)
15 #define CTRL0_SC_MD26M_CK_OFF			BIT(5)
16 #define CTRL0_SC_MD32K_CK_OFF			BIT(6)
17 #define CTRL0_SC_VLP_26M_CLK_SEL		BIT(7)
18 #define CTRL0_SC_26M_CK_SEL			BIT(8)
19 #define CTRL0_SC_TOP_26M_CLK_SEL		BIT(9)
20 #define CTRL0_SC_SYS_TIMER_CLK_32K_SEL		BIT(10)
21 #define CTRL0_SC_CIRQ_CLK_32K_SEL		BIT(11)
22 #define CTRL0_SC_AXI_DCM_DIS			BIT(12)
23 #define CTRL0_SC_CKSQ0_OFF			BIT(13)
24 #define CTRL0_SC_CKSQ1_OFF			BIT(14)
25 #define CTRL0_VCORE_PWR_ISO			BIT(15)
26 #define CTRL0_VCORE_PWR_ISO_PRE			BIT(16)
27 #define CTRL0_VCORE_PWR_RST_B			BIT(17)
28 #define CTRL0_VCORE_RESTORE_ENABLE		BIT(18)
29 #define CTRL0_SC_TOP_RESTORE_26M_CLK_SEL	BIT(19)
30 #define CTRL0_AOC_VCORE_SRAM_ISO_DIN		BIT(20)
31 #define CTRL0_AOC_VCORE_SRAM_LATCH_ENB		BIT(21)
32 #define CTRL0_AOC_VCORE_ANA_ISO			BIT(22)
33 #define CTRL0_AOC_VCORE_ANA_ISO_PRE		BIT(23)
34 #define CTRL0_AOC_VLPTOP_SRAM_ISO_DIN		BIT(24)
35 #define CTRL0_AOC_VLPTOP_SRAM_LATCH_ENB		BIT(25)
36 #define CTRL0_AOC_VCORE_IO_ISO			BIT(26)
37 #define CTRL0_AOC_VCORE_IO_LATCH_ENB		BIT(27)
38 #define CTRL0_RTFF_VCORE_SAVE			BIT(28)
39 #define CTRL0_RTFF_VCORE_NRESTORE		BIT(29)
40 #define CTRL0_RTFF_VCORE_CLK_DIS		BIT(30)
41 
42 #define CTRL1_PWRAP_SLEEP_REQ			BIT(0)
43 #define CTRL1_IM_SLP_EN				BIT(1)
44 #define CTRL1_SPM_LEAVE_VCORE_OFF_REQ		BIT(2)
45 #define CTRL1_SPM_CK_SEL0			BIT(4)
46 #define CTRL1_SPM_CK_SEL1			BIT(5)
47 #define CTRL1_TIMER_SET				BIT(6)
48 #define CTRL1_TIMER_CLR				BIT(7)
49 #define CTRL1_SPM_LEAVE_DEEPIDLE_REQ		BIT(8)
50 #define CTRL1_SPM_LEAVE_SUSPEND_REQ		BIT(9)
51 #define CTRL1_CSYSPWRUPACK			BIT(10)
52 #define CTRL1_SRCCLKENO0			BIT(11)
53 #define CTRL1_SRCCLKENO1			BIT(12)
54 #define CTRL1_SRCCLKENO2			BIT(13)
55 #define CTRL1_SPM_APSRC_INTERNAL_ACK		BIT(14)
56 #define CTRL1_SPM_EMI_INTERNAL_ACK		BIT(15)
57 #define CTRL1_SPM_DDREN_INTERNAL_ACK		BIT(16)
58 #define CTRL1_SPM_INFRA_INTERNAL_ACK		BIT(17)
59 #define CTRL1_SPM_VRF18_INTERNAL_ACK		BIT(18)
60 #define CTRL1_SPM_VCORE_INTERNAL_ACK		BIT(19)
61 #define CTRL1_SPM_VCORE_RESTORE_ACK		BIT(20)
62 #define CTRL1_SPM_PMIC_INTERNAL_ACK		BIT(21)
63 #define CTRL1_PMIC_IRQ_REQ_EN			BIT(22)
64 #define CTRL1_WDT_KICK_P			BIT(23)
65 #define CTRL1_FORCE_DDREN_WAKE			BIT(24)
66 #define CTRL1_FORCE_F26M_WAKE			BIT(25)
67 #define CTRL1_FORCE_APSRC_WAKE			BIT(26)
68 #define CTRL1_FORCE_INFRA_WAKE			BIT(27)
69 #define CTRL1_FORCE_VRF18_WAKE			BIT(28)
70 #define CTRL1_FORCE_VCORE_WAKE			BIT(29)
71 #define CTRL1_FORCE_EMI_WAKE			BIT(30)
72 #define CTRL1_FORCE_PMIC_WAKE			BIT(31)
73 
74 
75 #define CTRL2_MD32PCM_IRQ_TRIG_BIT		BIT(31)
76 
77 #define STA0_SRCCLKENI0				BIT(0)
78 #define STA0_SRCCLKENI1				BIT(1)
79 #define STA0_MD_SRCCLKENA			BIT(2)
80 #define STA0_MD_SRCCLKENA1			BIT(3)
81 #define STA0_MD_DDREN_REQ			BIT(4)
82 #define STA0_CONN_DDREN_REQ			BIT(5)
83 #define STA0_SSPM_SRCCLKENA			BIT(6)
84 #define STA0_SSPM_APSRC_REQ			BIT(7)
85 #define STA0_MD_STATE				BIT(8)
86 #define STA0_RC2SPM_SRCCLKENO_0_ACK		BIT(9)
87 #define STA0_MM_STATE				BIT(10)
88 #define STA0_SSPM_STATE				BIT(11)
89 #define STA0_CPUEB_STATE			BIT(12)
90 #define STA0_CONN_STATE				BIT(13)
91 #define STA0_CONN_VCORE_REQ			BIT(14)
92 #define STA0_CONN_SRCCLKENA			BIT(15)
93 #define STA0_CONN_SRCCLKENB			BIT(16)
94 #define STA0_CONN_APSRC_REQ			BIT(17)
95 #define STA0_SCP_STATE				BIT(18)
96 #define STA0_CSYSPWRUPREQ			BIT(19)
97 #define STA0_PWRAP_SLEEP_ACK			BIT(20)
98 #define STA0_DPM_STATE				BIT(21)
99 #define STA0_AUDIO_DSP_STATE			BIT(22)
100 #define STA0_PMIC_IRQ_ACK			BIT(23)
101 #define STA0_RESERVED_BIT_24			BIT(24)
102 #define STA0_RESERVED_BIT_25			BIT(25)
103 #define STA0_RESERVED_BIT_26			BIT(26)
104 #define STA0_DVFS_STATE				BIT(27)
105 #define STA0_RESERVED_BIT_28			BIT(28)
106 #define STA0_RESERVED_BIT_29			BIT(29)
107 #define STA0_SC_HW_S1_ACK_ALL			BIT(30)
108 #define STA0_DDREN_STATE			BIT(31)
109 
110 #define R12_PCM_TIMER_B				BIT(0)
111 #define R12_TWAM_PMSR_DVFSRC_ALCO		BIT(1)
112 #define R12_KP_IRQ_B				BIT(2)
113 #define R12_APWDT_EVENT_B			BIT(3)
114 #define R12_APXGPT_EVENT_B			BIT(4)
115 #define R12_CONN2AP_WAKEUP_B			BIT(5)
116 #define R12_EINT_EVENT_B			BIT(6)
117 #define R12_CONN_WDT_IRQ_B			BIT(7)
118 #define R12_CCIF0_EVENT_B			BIT(8)
119 #define R12_CCIF1_EVENT_B			BIT(9)
120 #define R12_SSPM2SPM_WAKEUP_B			BIT(10)
121 #define R12_SCP2SPM_WAKEUP_B			BIT(11)
122 #define R12_ADSP2SPM_WAKEUP_B			BIT(12)
123 #define R12_PCM_WDT_WAKEUP_B			BIT(13)
124 #define R12_USB0_CDSC_B				BIT(14)
125 #define R12_USB0_POWERDWN_B			BIT(15)
126 #define R12_UART_EVENT_B			BIT(16)
127 #define R12_DEBUGTOP_FLAG_IRQ_B			BIT(17)
128 #define R12_SYS_TIMER_EVENT_B			BIT(18)
129 #define R12_EINT_EVENT_SECURE_B			BIT(19)
130 #define R12_AFE_IRQ_MCU_B			BIT(20)
131 #define R12_THERM_CTRL_EVENT_B			BIT(21)
132 #define R12_SYS_CIRQ_IRQ_B			BIT(22)
133 #define R12_PBUS_EVENT_B			BIT(23)
134 #define R12_CSYSPWREQ_B				BIT(24)
135 #define R12_MD_WDT_B				BIT(25)
136 #define R12_AP2AP_PEER_WAKEUP_B			BIT(26)
137 #define R12_SEJ_B				BIT(27)
138 #define R12_CPU_WAKEUP				BIT(28)
139 #define R12_APUSYS_WAKE_HOST_B			BIT(29)
140 #define R12_PCIE_WAKE_B				BIT(30)
141 #define R12_MSDC_WAKE_B				BIT(31)
142 
143 #define EVENT_F26M_WAKE				BIT(0)
144 #define EVENT_F26M_SLEEP			BIT(1)
145 #define EVENT_INFRA_WAKE			BIT(2)
146 #define EVENT_INFRA_SLEEP			BIT(3)
147 #define EVENT_EMI_WAKE				BIT(4)
148 #define EVENT_EMI_SLEEP				BIT(5)
149 #define EVENT_APSRC_WAKE			BIT(6)
150 #define EVENT_APSRC_SLEEP			BIT(7)
151 #define EVENT_VRF18_WAKE			BIT(8)
152 #define EVENT_VRF18_SLEEP			BIT(9)
153 #define EVENT_DVFS_WAKE				BIT(10)
154 #define EVENT_DDREN_WAKE			BIT(11)
155 #define EVENT_DDREN_SLEEP			BIT(12)
156 #define EVENT_VCORE_WAKE			BIT(13)
157 #define EVENT_VCORE_SLEEP			BIT(14)
158 #define EVENT_PMIC_WAKE				BIT(15)
159 #define EVENT_PMIC_SLEEP			BIT(16)
160 #define EVENT_CPUEB_STATE			BIT(17)
161 #define EVENT_SSPM_STATE			BIT(18)
162 #define EVENT_DPM_STATE				BIT(19)
163 #define EVENT_SPM_LEAVE_VCORE_OFF_ACK		BIT(20)
164 #define EVENT_SW_SSPM_ADSP_SCP_MAILBOX_WAKE	BIT(21)
165 #define EVENT_SPM_LEAVE_SUSPEND_ACK		BIT(22)
166 #define EVENT_SPM_LEAVE_DEEPIDLE_ACK		BIT(23)
167 #define EVENT_CROSS_REQ_APU_l3			BIT(24)
168 #define EVENT_DFD_SOC_MTCMOS_REQ_IPIC_WAKE	BIT(25)
169 #define EVENT_AOVBUS_WAKE			BIT(26)
170 #define EVENT_AOVBUS_SLEEP			BIT(27)
171 
172 enum SPM_WAKE_SRC_LIST {
173 	WAKE_SRC_STA1_PCM_TIMER = BIT(0),
174 	WAKE_SRC_STA1_TWAM_PMSR_DVFSRC = BIT(1),
175 	WAKE_SRC_STA1_KP_IRQ_B = BIT(2),
176 	WAKE_SRC_STA1_APWDT_EVENT_B = BIT(3),
177 	WAKE_SRC_STA1_APXGPT1_EVENT_B = BIT(4),
178 	WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B = BIT(5),
179 	WAKE_SRC_STA1_EINT_EVENT_B = BIT(6),
180 	WAKE_SRC_STA1_CONN_WDT_IRQ_B = BIT(7),
181 	WAKE_SRC_STA1_CCIF0_EVENT_B = BIT(8),
182 	WAKE_SRC_STA1_CCIF1_EVENT_B = BIT(9),
183 	WAKE_SRC_STA1_SC_SSPM2SPM_WAKEUP_B = BIT(10),
184 	WAKE_SRC_STA1_SC_SCP2SPM_WAKEUP_B = BIT(11),
185 	WAKE_SRC_STA1_SC_ADSP2SPM_WAKEUP_B = BIT(12),
186 	WAKE_SRC_STA1_PCM_WDT_WAKEUP_B = BIT(13),
187 	WAKE_SRC_STA1_USB_CDSC_B = BIT(14),
188 	WAKE_SRC_STA1_USB_POWERDWN_B = BIT(15),
189 	WAKE_SRC_STA1_AP_UART_B = BIT(16),
190 	WAKE_SRC_STA1_DEBUGTOP_FLAG_IRQ_B = BIT(17),
191 	WAKE_SRC_STA1_SYS_TIMER_EVENT_B = BIT(18),
192 	WAKE_SRC_STA1_EINT_EVENT_SECURE_B = BIT(19),
193 	WAKE_SRC_STA1_AFE_IRQ_MCU_B = BIT(20),
194 	WAKE_SRC_STA1_THERM_CTRL_EVENT_B = BIT(21),
195 	WAKE_SRC_STA1_SYS_CIRQ_IRQ_B = BIT(22),
196 	WAKE_SRC_STA1_PBUS_EVENT_B = BIT(23),
197 	WAKE_SRC_STA1_CSYSPWREQ_B = BIT(24),
198 	WAKE_SRC_STA1_MD1_WDT_B = BIT(25),
199 	WAKE_SRC_STA1_AP2AP_PEER_WAKEUPEVENT_B = BIT(26),
200 	WAKE_SRC_STA1_SEJ_EVENT_B = BIT(27),
201 	WAKE_SRC_STA1_SPM_CPU_WAKEUPEVENT_B = BIT(28),
202 	WAKE_SRC_STA1_APUSYS_WAKE_HOST_B = BIT(29),
203 	WAKE_SRC_STA1_PCIE_B = BIT(30),
204 	WAKE_SRC_STA1_MSDC_B = BIT(31),
205 };
206 
207 extern const char *wakesrc_str[32];
208 
209 #endif /* PCM_DEF_H */
210