xref: /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/mt_spm_stats.c (revision b47dddd061e92054c3b2096fc8aa9688bfef68d6)
1 /*
2  * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <lib/mmio.h>
8 
9 #include <mt_spm.h>
10 #include <mt_spm_reg.h>
11 #include <mt_spm_stats.h>
12 
13 #define READ_AND_MASK_16BIT(addr)	(mmio_read_32(addr) & 0xFFFF)
14 
15 void mt_spm_update_lp_stat(struct spm_lp_stat *stat)
16 {
17 	if (!stat)
18 		return;
19 
20 	stat->record[SPM_STAT_MCUSYS].count += 1;
21 	stat->record[SPM_STAT_MCUSYS].duration +=
22 			mmio_read_32(SPM_BK_PCM_TIMER);
23 	stat->record[SPM_STAT_D1_2].count +=
24 			READ_AND_MASK_16BIT(SPM_APSRC_EVENT_COUNT_STA);
25 	stat->record[SPM_STAT_D2].count +=
26 			READ_AND_MASK_16BIT(SPM_EMI_EVENT_COUNT_STA);
27 	stat->record[SPM_STAT_D3].count +=
28 			READ_AND_MASK_16BIT(SPM_VRF18_EVENT_COUNT_STA);
29 	stat->record[SPM_STAT_D4].count +=
30 			READ_AND_MASK_16BIT(SPM_INFRA_EVENT_COUNT_STA);
31 	stat->record[SPM_STAT_D6X].count +=
32 			READ_AND_MASK_16BIT(SPM_PMIC_EVENT_COUNT_STA);
33 	stat->record[SPM_STAT_F26M].count +=
34 			READ_AND_MASK_16BIT(SPM_SRCCLKENA_EVENT_COUNT_STA);
35 	stat->record[SPM_STAT_F26M].duration +=
36 			READ_AND_MASK_16BIT(SPM_BK_VTCXO_DUR);
37 	stat->record[SPM_STAT_VCORE].count +=
38 			READ_AND_MASK_16BIT(SPM_VCORE_EVENT_COUNT_STA);
39 	stat->record[SPM_STAT_VCORE].duration +=
40 			mmio_read_32(SPM_SW_RSV_4);
41 }
42 
43 uint64_t mt_spm_get_lp_stat(struct spm_lp_stat *stat,
44 			    uint32_t index, uint32_t type)
45 {
46 
47 	uint64_t ret;
48 
49 	if (!stat || index >= NUM_SPM_STAT)
50 		return 0;
51 
52 	switch (type) {
53 	case SPM_SLP_COUNT:
54 		ret = stat->record[index].count;
55 		break;
56 	case SPM_SLP_DURATION:
57 		ret = stat->record[index].duration;
58 		break;
59 	default:
60 		ret = 0;
61 		break;
62 	}
63 
64 	return ret;
65 }
66