1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_REG_H 8 #define MT_SPM_REG_H 9 10 #include <pcm_def.h> 11 #include <sleep_def.h> 12 13 /************************************** 14 * Define and Declare 15 **************************************/ 16 #define POWERON_CONFIG_EN (SPM_BASE + 0x0000) 17 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x0004) 18 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x0008) 19 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x000C) 20 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x0010) 21 #define PCM_PWR_IO_EN (SPM_BASE + 0x0014) 22 #define PCM_CON0 (SPM_BASE + 0x0018) 23 #define PCM_CON1 (SPM_BASE + 0x001C) 24 #define SPM_SRAM_SLEEP_CTRL (SPM_BASE + 0x0020) 25 #define SPM_CLK_CON (SPM_BASE + 0x0024) 26 #define SPM_CLK_SETTLE (SPM_BASE + 0x0028) 27 #define SPM_SW_RST_CON (SPM_BASE + 0x0040) 28 #define SPM_SW_RST_CON_SET (SPM_BASE + 0x0044) 29 #define SPM_SW_RST_CON_CLR (SPM_BASE + 0x0048) 30 #define R_SEC_READ_MASK (SPM_BASE + 0x0050) 31 #define R_ONE_TIME_LOCK_L (SPM_BASE + 0x0054) 32 #define R_ONE_TIME_LOCK_M (SPM_BASE + 0x0058) 33 #define R_ONE_TIME_LOCK_H (SPM_BASE + 0x005C) 34 #define SSPM_CLK_CON (SPM_BASE + 0x0084) 35 #define SCP_CLK_CON (SPM_BASE + 0x0088) 36 #define SPM_SWINT (SPM_BASE + 0x0090) 37 #define SPM_SWINT_SET (SPM_BASE + 0x0094) 38 #define SPM_SWINT_CLR (SPM_BASE + 0x0098) 39 #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x00B0) 40 #define SPM_IRQ_MASK (SPM_BASE + 0x00B4) 41 #define MD32PCM_SCU_CTRL0 (SPM_BASE + 0x0100) 42 #define MD32PCM_SCU_CTRL1 (SPM_BASE + 0x0104) 43 #define MD32PCM_SCU_CTRL2 (SPM_BASE + 0x0108) 44 #define MD32PCM_SCU_CTRL3 (SPM_BASE + 0x010C) 45 #define MD32PCM_SCU_STA0 (SPM_BASE + 0x0110) 46 #define SPM_IRQ_STA (SPM_BASE + 0x0128) 47 #define MD32PCM_WAKEUP_STA (SPM_BASE + 0x0130) 48 #define MD32PCM_EVENT_STA (SPM_BASE + 0x0134) 49 #define SPM_WAKEUP_MISC (SPM_BASE + 0x0140) 50 #define SPM_CK_STA (SPM_BASE + 0x0164) 51 #define MD32PCM_STA (SPM_BASE + 0x0190) 52 #define MD32PCM_PC (SPM_BASE + 0x0194) 53 #define SPM_CSOPLU_EN_CG_CON (SPM_BASE + 0x0198) 54 #define SPM_RESOURCE_CSOPLU_ACK_CON (SPM_BASE + 0x019C) 55 #define SPM_CSOPLU_OFF_MODE_CON (SPM_BASE + 0x01A0) 56 #define SPM_CSOPLU_ACK_STA (SPM_BASE + 0x01A4) 57 #define SPM_REOSURCE_CSOPLU_MASK (SPM_BASE + 0x01A8) 58 #define SPM_REQ_BLOCK (SPM_BASE + 0x01AC) 59 #define DVFS_IPS_CTRL (SPM_BASE + 0x01B0) 60 #define TOP_CKSYS_CON (SPM_BASE + 0x01B4) 61 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x0200) 62 #define CPU_WFI_EN (SPM_BASE + 0x0204) 63 #define CPU_WFI_EN_SET (SPM_BASE + 0x0208) 64 #define CPU_WFI_EN_CLR (SPM_BASE + 0x020C) 65 #define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x0210) 66 #define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x0214) 67 #define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x0218) 68 #define MCUSYS_IDLE_STA (SPM_BASE + 0x021C) 69 #define CPU_PWR_STATUS (SPM_BASE + 0x0220) 70 #define SW2SPM_WAKEUP (SPM_BASE + 0x0224) 71 #define SW2SPM_WAKEUP_SET (SPM_BASE + 0x0228) 72 #define SW2SPM_WAKEUP_CLR (SPM_BASE + 0x022C) 73 #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x0230) 74 #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x0234) 75 #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x0238) 76 #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x023C) 77 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x0240) 78 #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x0244) 79 #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x0248) 80 #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x024C) 81 #define SPM2MCUPM_CON (SPM_BASE + 0x0250) 82 #define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x0260) 83 #define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x0264) 84 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x0268) 85 #define SPM_CPU1_PWR_CON (SPM_BASE + 0x026C) 86 #define SPM_CPU2_PWR_CON (SPM_BASE + 0x0270) 87 #define SPM_CPU3_PWR_CON (SPM_BASE + 0x0274) 88 #define SPM_CPU4_PWR_CON (SPM_BASE + 0x0278) 89 #define SPM_CPU5_PWR_CON (SPM_BASE + 0x027C) 90 #define SPM_CPU6_PWR_CON (SPM_BASE + 0x0280) 91 #define SPM_CPU7_PWR_CON (SPM_BASE + 0x0284) 92 #define SPM_MCUPM_SPMC_CON (SPM_BASE + 0x0288) 93 #define SODI5_MCUSYS_CON (SPM_BASE + 0x028C) 94 #define SPM_DPM_P2P_STA (SPM_BASE + 0x02A0) 95 #define SPM_DPM_P2P_CON (SPM_BASE + 0x02A4) 96 #define SPM_DPM_INTF_STA (SPM_BASE + 0x02A8) 97 #define SPM_DPM_WB_CON (SPM_BASE + 0x02AC) 98 #define SPM_PWRAP_CON (SPM_BASE + 0x0300) 99 #define SPM_PWRAP_CON_STA (SPM_BASE + 0x0304) 100 #define SPM_PMIC_SPMI_CON (SPM_BASE + 0x0308) 101 #define SPM_PWRAP_CMD0 (SPM_BASE + 0x0310) 102 #define SPM_PWRAP_CMD1 (SPM_BASE + 0x0314) 103 #define SPM_PWRAP_CMD2 (SPM_BASE + 0x0318) 104 #define SPM_PWRAP_CMD3 (SPM_BASE + 0x031C) 105 #define SPM_PWRAP_CMD4 (SPM_BASE + 0x0320) 106 #define SPM_PWRAP_CMD5 (SPM_BASE + 0x0324) 107 #define SPM_PWRAP_CMD6 (SPM_BASE + 0x0328) 108 #define SPM_PWRAP_CMD7 (SPM_BASE + 0x032C) 109 #define SPM_PWRAP_CMD8 (SPM_BASE + 0x0330) 110 #define SPM_PWRAP_CMD9 (SPM_BASE + 0x0334) 111 #define SPM_PWRAP_CMD10 (SPM_BASE + 0x0338) 112 #define SPM_PWRAP_CMD11 (SPM_BASE + 0x033C) 113 #define SPM_PWRAP_CMD12 (SPM_BASE + 0x0340) 114 #define SPM_PWRAP_CMD13 (SPM_BASE + 0x0344) 115 #define SPM_PWRAP_CMD14 (SPM_BASE + 0x0348) 116 #define SPM_PWRAP_CMD15 (SPM_BASE + 0x034C) 117 #define SPM_PWRAP_CMD16 (SPM_BASE + 0x0350) 118 #define SPM_PWRAP_CMD17 (SPM_BASE + 0x0354) 119 #define SPM_PWRAP_CMD18 (SPM_BASE + 0x0358) 120 #define SPM_PWRAP_CMD19 (SPM_BASE + 0x035C) 121 #define SPM_PWRAP_CMD20 (SPM_BASE + 0x0360) 122 #define SPM_PWRAP_CMD21 (SPM_BASE + 0x0364) 123 #define SPM_PWRAP_CMD22 (SPM_BASE + 0x0368) 124 #define SPM_PWRAP_CMD23 (SPM_BASE + 0x036C) 125 #define SPM_PWRAP_CMD24 (SPM_BASE + 0x0370) 126 #define SPM_PWRAP_CMD25 (SPM_BASE + 0x0374) 127 #define SPM_PWRAP_CMD26 (SPM_BASE + 0x0378) 128 #define SPM_PWRAP_CMD27 (SPM_BASE + 0x037C) 129 #define SPM_PWRAP_CMD28 (SPM_BASE + 0x0380) 130 #define SPM_PWRAP_CMD29 (SPM_BASE + 0x0384) 131 #define SPM_PWRAP_CMD30 (SPM_BASE + 0x0388) 132 #define SPM_PWRAP_CMD31 (SPM_BASE + 0x038C) 133 #define DVFSRC_EVENT_STA (SPM_BASE + 0x0390) 134 #define SPM_FORCE_DVFS (SPM_BASE + 0x0394) 135 #define SPM_DVFS_STA (SPM_BASE + 0x0398) 136 #define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x039C) 137 #define SPM_DVFS_LEVEL (SPM_BASE + 0x03A0) 138 #define SPM_DVFS_OPP (SPM_BASE + 0x03A4) 139 #define SPM_ULTRA_REQ (SPM_BASE + 0x03A8) 140 #define SPM_DVFS_CON (SPM_BASE + 0x03AC) 141 #define SPM_SRAMRC_CON (SPM_BASE + 0x03B0) 142 #define SPM_SRCLKENRC_CON (SPM_BASE + 0x03B4) 143 #define SPM_DPSW_VAPU_ISO_CON (SPM_BASE + 0x03BC) 144 #define SPM_DPSW_VMM_ISO_CON (SPM_BASE + 0x03C0) 145 #define SPM_DPSW_VMD_ISO_CON (SPM_BASE + 0x03C4) 146 #define SPM_DPSW_VMODEM_ISO_CON (SPM_BASE + 0x03C8) 147 #define SPM_DPSW_VCORE_ISO_CON (SPM_BASE + 0x03CC) 148 #define SPM_DPSW_CON (SPM_BASE + 0x03D0) 149 #define SPM_DPSW_CON_SET (SPM_BASE + 0x03D4) 150 #define SPM_DPSW_CON_CLR (SPM_BASE + 0x03D8) 151 #define SPM_DPSW_AOC_ISO_CON (SPM_BASE + 0x03DC) 152 #define SPM_DPSW_AOC_ISO_CON_SET (SPM_BASE + 0x03E0) 153 #define SPM_DPSW_AOC_ISO_CON_CLR (SPM_BASE + 0x03E4) 154 #define SPM_DPSW_FORCE_SWITCH_CON (SPM_BASE + 0x03E8) 155 #define SPM_DPSW_FORCE_SWITCH_CON_SET (SPM_BASE + 0x03EC) 156 #define SPM_DPSW_FORCE_SWITCH_CON_CLR (SPM_BASE + 0x03F0) 157 #define SPM2DPSW_CTRL_ACK (SPM_BASE + 0x03F4) 158 #define CSOPLU_CON (SPM_BASE + 0x0400) 159 #define AP_MDSRC_REQ (SPM_BASE + 0x0404) 160 #define SPM2MD_SWITCH_CTRL (SPM_BASE + 0x0408) 161 #define RC_SPM_CTRL (SPM_BASE + 0x040C) 162 #define SPM2GPUPM_CON (SPM_BASE + 0x0410) 163 #define SPM2APU_CON (SPM_BASE + 0x0414) 164 #define SPM2EFUSE_CON (SPM_BASE + 0x0418) 165 #define SPM2DFD_CON (SPM_BASE + 0x041C) 166 #define RSV_PLL_CON (SPM_BASE + 0x0420) 167 #define EMI_SLB_CON (SPM_BASE + 0x0424) 168 #define SPM_SUSPEND_FLAG_CON (SPM_BASE + 0x0428) 169 #define SPM2PMSR_CON (SPM_BASE + 0x042C) 170 #define SPM_TOPCK_RTFF_CON (SPM_BASE + 0x0430) 171 #define EMI_SHF_CON (SPM_BASE + 0x0434) 172 #define CIRQ_BYPASS_CON (SPM_BASE + 0x0438) 173 #define AOC_VCORE_SRAM_CON (SPM_BASE + 0x043C) 174 #define SPM2EMI_PDN_CTRL (SPM_BASE + 0x0440) 175 #define VLP_RTFF_CTRL_MASK (SPM_BASE + 0x0444) 176 #define VLP_RTFF_CTRL_MASK_SET (SPM_BASE + 0x0448) 177 #define VLP_RTFF_CTRL_MASK_CLR (SPM_BASE + 0x044C) 178 #define VLP_RTFF_CTRL_MASK_2 (SPM_BASE + 0x0450) 179 #define VLP_RTFF_CTRL_MASK_2_SET (SPM_BASE + 0x0454) 180 #define VLP_RTFF_CTRL_MASK_2_CLR (SPM_BASE + 0x0458) 181 182 /* SW CG Register Define*/ 183 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_0 (SPM_BASE + 0x0460) 184 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_1 (SPM_BASE + 0x0464) 185 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_2 (SPM_BASE + 0x0468) 186 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_3 (SPM_BASE + 0x046C) 187 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_0 (SPM_BASE + 0x0470) 188 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_1 (SPM_BASE + 0x0474) 189 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_2 (SPM_BASE + 0x0478) 190 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_3 (SPM_BASE + 0x047C) 191 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_0 (SPM_BASE + 0x0480) 192 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_1 (SPM_BASE + 0x0484) 193 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_2 (SPM_BASE + 0x0488) 194 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_3 (SPM_BASE + 0x048C) 195 #define REG_MODULE_SW_CG_F26M_REQ_MASK_0 (SPM_BASE + 0x0490) 196 #define REG_MODULE_SW_CG_F26M_REQ_MASK_1 (SPM_BASE + 0x0494) 197 #define REG_MODULE_SW_CG_F26M_REQ_MASK_2 (SPM_BASE + 0x0498) 198 #define REG_MODULE_SW_CG_F26M_REQ_MASK_3 (SPM_BASE + 0x049C) 199 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_0 (SPM_BASE + 0x04A0) 200 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_1 (SPM_BASE + 0x04A4) 201 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_2 (SPM_BASE + 0x04A8) 202 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_3 (SPM_BASE + 0x04AC) 203 #define REG_PWR_STATUS_DDREN_REQ_MASK (SPM_BASE + 0x04B0) 204 #define REG_PWR_STATUS_VRF18_REQ_MASK (SPM_BASE + 0x04B4) 205 #define REG_PWR_STATUS_INFRA_REQ_MASK (SPM_BASE + 0x04B8) 206 #define REG_PWR_STATUS_F26M_REQ_MASK (SPM_BASE + 0x04BC) 207 #define REG_PWR_STATUS_PMIC_REQ_MASK (SPM_BASE + 0x04C0) 208 #define REG_PWR_STATUS_VCORE_REQ_MASK (SPM_BASE + 0x04C4) 209 #define REG_PWR_STATUS_MSB_DDREN_REQ_MASK (SPM_BASE + 0x04C8) 210 #define REG_PWR_STATUS_MSB_VRF18_REQ_MASK (SPM_BASE + 0x04CC) 211 #define REG_PWR_STATUS_MSB_INFRA_REQ_MASK (SPM_BASE + 0x04D0) 212 #define REG_PWR_STATUS_MSB_F26M_REQ_MASK (SPM_BASE + 0x04D4) 213 #define REG_PWR_STATUS_MSB_PMIC_REQ_MASK (SPM_BASE + 0x04D8) 214 #define REG_PWR_STATUS_MSB_VCORE_REQ_MASK (SPM_BASE + 0x04DC) 215 #define REG_MODULE_BUSY_DDREN_REQ_MASK (SPM_BASE + 0x04E0) 216 #define REG_MODULE_BUSY_VRF18_REQ_MASK (SPM_BASE + 0x04E4) 217 #define REG_MODULE_BUSY_INFRA_REQ_MASK (SPM_BASE + 0x04E8) 218 #define REG_MODULE_BUSY_F26M_REQ_MASK (SPM_BASE + 0x04EC) 219 #define REG_MODULE_BUSY_PMIC_REQ_MASK (SPM_BASE + 0x04F0) 220 #define REG_MODULE_BUSY_VCORE_REQ_MASK (SPM_BASE + 0x04F4) 221 222 /* SYS TIMER Register Define */ 223 #define SYS_TIMER_CON (SPM_BASE + 0x0500) 224 #define SYS_TIMER_VALUE_L (SPM_BASE + 0x0504) 225 #define SYS_TIMER_VALUE_H (SPM_BASE + 0x0508) 226 #define SYS_TIMER_START_L (SPM_BASE + 0x050C) 227 #define SYS_TIMER_START_H (SPM_BASE + 0x0510) 228 #define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x0514) 229 #define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x0518) 230 #define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x051C) 231 #define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x0520) 232 #define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x0524) 233 #define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x0528) 234 #define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x052C) 235 #define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x0530) 236 #define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x0534) 237 #define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x0538) 238 #define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x053C) 239 #define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x0540) 240 #define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x0544) 241 #define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x0548) 242 #define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x054C) 243 #define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x0550) 244 #define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x0554) 245 #define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x0558) 246 #define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x055C) 247 #define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x0560) 248 #define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x0564) 249 #define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x0568) 250 #define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x056C) 251 #define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x0570) 252 #define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x0574) 253 #define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x0578) 254 #define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x057C) 255 #define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x0580) 256 #define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x0584) 257 #define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x0588) 258 #define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x058C) 259 #define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x0590) 260 #define PCM_TIMER_VAL (SPM_BASE + 0x0594) 261 #define PCM_TIMER_OUT (SPM_BASE + 0x0598) 262 #define SPM_COUNTER_0 (SPM_BASE + 0x059C) 263 #define SPM_COUNTER_1 (SPM_BASE + 0x05A0) 264 #define SPM_COUNTER_2 (SPM_BASE + 0x05A4) 265 #define PCM_WDT_VAL (SPM_BASE + 0x05A8) 266 #define PCM_WDT_OUT (SPM_BASE + 0x05AC) 267 #define SPM_SW_FLAG_0 (SPM_BASE + 0x0600) 268 #define SPM_SW_DEBUG_0 (SPM_BASE + 0x0604) 269 #define SPM_SW_FLAG_1 (SPM_BASE + 0x0608) 270 #define SPM_SW_DEBUG_1 (SPM_BASE + 0x060C) 271 #define SPM_SW_RSV_0 (SPM_BASE + 0x0610) 272 #define SPM_SW_RSV_1 (SPM_BASE + 0x0614) 273 #define SPM_SW_RSV_2 (SPM_BASE + 0x0618) 274 #define SPM_SW_RSV_3 (SPM_BASE + 0x061C) 275 #define SPM_SW_RSV_4 (SPM_BASE + 0x0620) 276 #define SPM_SW_RSV_5 (SPM_BASE + 0x0624) 277 #define SPM_SW_RSV_6 (SPM_BASE + 0x0628) 278 #define SPM_SW_RSV_7 (SPM_BASE + 0x062C) 279 #define SPM_SW_RSV_8 (SPM_BASE + 0x0630) 280 #define SPM_BK_WAKE_EVENT (SPM_BASE + 0x0634) 281 #define SPM_BK_VTCXO_DUR (SPM_BASE + 0x0638) 282 #define SPM_BK_WAKE_MISC (SPM_BASE + 0x063C) 283 #define SPM_BK_PCM_TIMER (SPM_BASE + 0x0640) 284 #define SPM_RSV_CON_0 (SPM_BASE + 0x0650) 285 #define SPM_RSV_CON_1 (SPM_BASE + 0x0654) 286 #define SPM_RSV_STA_0 (SPM_BASE + 0x0658) 287 #define SPM_RSV_STA_1 (SPM_BASE + 0x065C) 288 #define SPM_SPARE_CON (SPM_BASE + 0x0660) 289 #define SPM_SPARE_CON_SET (SPM_BASE + 0x0664) 290 #define SPM_SPARE_CON_CLR (SPM_BASE + 0x0668) 291 #define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x066C) 292 #define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x0670) 293 #define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x0674) 294 #define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x0678) 295 #define SCP_VCORE_LEVEL (SPM_BASE + 0x067C) 296 #define SPM_DDREN_ACK_SEL_CON (SPM_BASE + 0x0680) 297 #define SPM_SW_FLAG_2 (SPM_BASE + 0x0684) 298 #define SPM_SW_DEBUG_2 (SPM_BASE + 0x0688) 299 #define SPM_DV_CON_0 (SPM_BASE + 0x068C) 300 #define SPM_DV_CON_1 (SPM_BASE + 0x0690) 301 #define SPM_SEMA_M0 (SPM_BASE + 0x069C) 302 #define SPM_SEMA_M1 (SPM_BASE + 0x06A0) 303 #define SPM_SEMA_M2 (SPM_BASE + 0x06A4) 304 #define SPM_SEMA_M3 (SPM_BASE + 0x06A8) 305 #define SPM_SEMA_M4 (SPM_BASE + 0x06AC) 306 #define SPM_SEMA_M5 (SPM_BASE + 0x06B0) 307 #define SPM_SEMA_M6 (SPM_BASE + 0x06B4) 308 #define SPM_SEMA_M7 (SPM_BASE + 0x06B8) 309 #define SPM2ADSP_MAILBOX (SPM_BASE + 0x06BC) 310 #define ADSP2SPM_MAILBOX (SPM_BASE + 0x06C0) 311 #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x06C4) 312 #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x06C8) 313 #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x06CC) 314 #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x06D0) 315 #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x06D4) 316 #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x06D8) 317 #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x06DC) 318 #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x06E0) 319 #define SPM2SCP_MAILBOX (SPM_BASE + 0x06E4) 320 #define SCP2SPM_MAILBOX (SPM_BASE + 0x06E8) 321 #define SCP_AOV_BUS_CON (SPM_BASE + 0x06EC) 322 #define VCORE_RTFF_CTRL_MASK (SPM_BASE + 0x06F0) 323 #define VCORE_RTFF_CTRL_MASK_SET (SPM_BASE + 0x06F4) 324 #define VCORE_RTFF_CTRL_MASK_CLR (SPM_BASE + 0x06F8) 325 #define SPM_SRAM_SRCLKENO_MASK (SPM_BASE + 0x06FC) 326 #define SPM_WAKEUP_STA (SPM_BASE + 0x0800) 327 #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x0804) 328 #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0808) 329 #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x080C) 330 #define SPM_WAKEUP_EVENT_SENS (SPM_BASE + 0x0810) 331 #define SPM_WAKEUP_EVENT_CLEAR (SPM_BASE + 0x0814) 332 #define SPM_SRC_REQ (SPM_BASE + 0x0818) 333 #define SPM_SRC_MASK_0 (SPM_BASE + 0x081C) 334 #define SPM_SRC_MASK_1 (SPM_BASE + 0x0820) 335 #define SPM_SRC_MASK_2 (SPM_BASE + 0x0824) 336 #define SPM_SRC_MASK_3 (SPM_BASE + 0x0828) 337 #define SPM_SRC_MASK_4 (SPM_BASE + 0x082C) 338 #define SPM_SRC_MASK_5 (SPM_BASE + 0x0830) 339 #define SPM_SRC_MASK_6 (SPM_BASE + 0x0834) 340 #define SPM_SRC_MASK_7 (SPM_BASE + 0x0838) 341 #define SPM_SRC_MASK_8 (SPM_BASE + 0x083C) 342 #define SPM_SRC_MASK_9 (SPM_BASE + 0x0840) 343 #define SPM_SRC_MASK_10 (SPM_BASE + 0x0844) 344 #define SPM_SRC_MASK_11 (SPM_BASE + 0x0848) 345 #define SPM_SRC_MASK_12 (SPM_BASE + 0x084C) 346 #define SPM_SRC_MASK_13 (SPM_BASE + 0x0850) 347 #define SPM_SRC_MASK_14 (SPM_BASE + 0x0854) 348 #define SPM_SRC_MASK_15 (SPM_BASE + 0x0858) 349 #define SPM_SRC_MASK_16 (SPM_BASE + 0x085C) 350 #define SPM_REQ_STA_0 (SPM_BASE + 0x0860) 351 #define SPM_REQ_STA_1 (SPM_BASE + 0x0864) 352 #define SPM_REQ_STA_2 (SPM_BASE + 0x0868) 353 #define SPM_REQ_STA_3 (SPM_BASE + 0x086C) 354 #define SPM_REQ_STA_4 (SPM_BASE + 0x0870) 355 #define SPM_REQ_STA_5 (SPM_BASE + 0x0874) 356 #define SPM_REQ_STA_6 (SPM_BASE + 0x0878) 357 #define SPM_REQ_STA_7 (SPM_BASE + 0x087C) 358 #define SPM_REQ_STA_8 (SPM_BASE + 0x0880) 359 #define SPM_REQ_STA_9 (SPM_BASE + 0x0884) 360 #define SPM_REQ_STA_10 (SPM_BASE + 0x0888) 361 #define SPM_REQ_STA_11 (SPM_BASE + 0x088C) 362 #define SPM_REQ_STA_12 (SPM_BASE + 0x0890) 363 #define SPM_REQ_STA_13 (SPM_BASE + 0x0894) 364 #define SPM_REQ_STA_14 (SPM_BASE + 0x0898) 365 #define SPM_REQ_STA_15 (SPM_BASE + 0x089C) 366 #define SPM_REQ_STA_16 (SPM_BASE + 0x08A0) 367 #define SPM_IPC_WAKEUP_REQ (SPM_BASE + 0x08A4) 368 #define IPC_WAKEUP_REQ_MASK_STA (SPM_BASE + 0x08A8) 369 #define SPM_EVENT_CON_MISC (SPM_BASE + 0x08AC) 370 #define DDREN_DBC_CON (SPM_BASE + 0x08B0) 371 #define SPM_RESOURCE_ACK_CON_0 (SPM_BASE + 0x08B4) 372 #define SPM_RESOURCE_ACK_CON_1 (SPM_BASE + 0x08B8) 373 #define SPM_RESOURCE_ACK_MASK_0 (SPM_BASE + 0x08BC) 374 #define SPM_RESOURCE_ACK_MASK_1 (SPM_BASE + 0x08C0) 375 #define SPM_RESOURCE_ACK_MASK_2 (SPM_BASE + 0x08C4) 376 #define SPM_RESOURCE_ACK_MASK_3 (SPM_BASE + 0x08C8) 377 #define SPM_RESOURCE_ACK_MASK_4 (SPM_BASE + 0x08CC) 378 #define SPM_RESOURCE_ACK_MASK_5 (SPM_BASE + 0x08D0) 379 #define SPM_RESOURCE_ACK_MASK_6 (SPM_BASE + 0x08D4) 380 #define SPM_RESOURCE_ACK_MASK_7 (SPM_BASE + 0x08D8) 381 #define SPM_RESOURCE_ACK_MASK_8 (SPM_BASE + 0x08DC) 382 #define SPM_RESOURCE_ACK_MASK_9 (SPM_BASE + 0x08E0) 383 #define SPM_RESOURCE_ACK_MASK_10 (SPM_BASE + 0x08E4) 384 #define SPM_RESOURCE_ACK_MASK_11 (SPM_BASE + 0x08E8) 385 #define SPM_RESOURCE_ACK_MASK_12 (SPM_BASE + 0x08EC) 386 #define SPM_EVENT_COUNTER_CLEAR (SPM_BASE + 0x08F0) 387 #define SPM_VCORE_EVENT_COUNT_STA (SPM_BASE + 0x08F4) 388 #define SPM_PMIC_EVENT_COUNT_STA (SPM_BASE + 0x08F8) 389 #define SPM_SRCCLKENA_EVENT_COUNT_STA (SPM_BASE + 0x08FC) 390 #define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x0900) 391 #define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x0904) 392 #define SPM_EMI_EVENT_COUNT_STA (SPM_BASE + 0x0908) 393 #define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x090C) 394 #define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x0910) 395 #define SPM_SRC_MASK_17 (SPM_BASE + 0x0914) 396 #define SPM_SRC_MASK_18 (SPM_BASE + 0x0918) 397 #define SPM_RESOURCE_ACK_MASK_13 (SPM_BASE + 0x091C) 398 #define SPM_RESOURCE_ACK_MASK_14 (SPM_BASE + 0x0920) 399 #define SPM_REQ_STA_17 (SPM_BASE + 0x0924) 400 #define SPM_REQ_STA_18 (SPM_BASE + 0x0928) 401 #define MD1_PWR_CON (SPM_BASE + 0x0E00) 402 #define CONN_PWR_CON (SPM_BASE + 0x0E04) 403 #define APIFR_IO_PWR_CON (SPM_BASE + 0x0E08) 404 #define APIFR_MEM_PWR_CON (SPM_BASE + 0x0E0C) 405 #define PERI_PWR_CON (SPM_BASE + 0x0E10) 406 #define PERI_ETHER_PWR_CON (SPM_BASE + 0x0E14) 407 #define SSUSB_DP_PHY_P0_PWR_CON (SPM_BASE + 0x0E18) 408 #define SSUSB_P0_PWR_CON (SPM_BASE + 0x0E1C) 409 #define SSUSB_P1_PWR_CON (SPM_BASE + 0x0E20) 410 #define SSUSB_P23_PWR_CON (SPM_BASE + 0x0E24) 411 #define SSUSB_PHY_P2_PWR_CON (SPM_BASE + 0x0E28) 412 #define UFS0_PWR_CON (SPM_BASE + 0x0E2C) 413 #define UFS0_PHY_PWR_CON (SPM_BASE + 0x0E30) 414 #define PEXTP_MAC0_PWR_CON (SPM_BASE + 0x0E34) 415 #define PEXTP_MAC1_PWR_CON (SPM_BASE + 0x0E38) 416 #define PEXTP_MAC2_PWR_CON (SPM_BASE + 0x0E3C) 417 #define PEXTP_PHY0_PWR_CON (SPM_BASE + 0x0E40) 418 #define PEXTP_PHY1_PWR_CON (SPM_BASE + 0x0E44) 419 #define PEXTP_PHY2_PWR_CON (SPM_BASE + 0x0E48) 420 #define AUDIO_PWR_CON (SPM_BASE + 0x0E4C) 421 #define ADSP_CORE1_PWR_CON (SPM_BASE + 0x0E50) 422 #define ADSP_TOP_PWR_CON (SPM_BASE + 0x0E54) 423 #define ADSP_INFRA_PWR_CON (SPM_BASE + 0x0E58) 424 #define ADSP_AO_PWR_CON (SPM_BASE + 0x0E5C) 425 #define MM_PROC_PWR_CON (SPM_BASE + 0x0E60) 426 #define SCP_PWR_CON (SPM_BASE + 0x0E64) 427 #define DPM0_PWR_CON (SPM_BASE + 0x0E68) 428 #define DPM1_PWR_CON (SPM_BASE + 0x0E6C) 429 #define DPM2_PWR_CON (SPM_BASE + 0x0E70) 430 #define DPM3_PWR_CON (SPM_BASE + 0x0E74) 431 #define EMI0_PWR_CON (SPM_BASE + 0x0E78) 432 #define EMI1_PWR_CON (SPM_BASE + 0x0E7C) 433 #define EMI_INFRA_PWR_CON (SPM_BASE + 0x0E80) 434 #define SSRSYS_PWR_CON (SPM_BASE + 0x0E84) 435 #define SPU_ISE_PWR_CON (SPM_BASE + 0x0E88) 436 #define SPU_HWROT_PWR_CON (SPM_BASE + 0x0E8C) 437 #define VLP_PWR_CON (SPM_BASE + 0x0E90) 438 #define HSGMII0_PWR_CON (SPM_BASE + 0x0E94) 439 #define HSGMII1_PWR_CON (SPM_BASE + 0x0E98) 440 #define MFG_VLP_PWR_CON (SPM_BASE + 0x0E9C) 441 #define MCUSYS_BUSBLK_PWR_CON (SPM_BASE + 0x0EA0) 442 #define CPUEB_PWR_CON (SPM_BASE + 0x0EA4) 443 #define MFG0_PWR_CON (SPM_BASE + 0x0EA8) 444 #define ADSP_HRE_SRAM_CON (SPM_BASE + 0x0EAC) 445 #define CCU_SLEEP_SRAM_CON (SPM_BASE + 0x0EB0) 446 #define EFUSE_SRAM_CON (SPM_BASE + 0x0EB4) 447 #define EMI_HRE_SRAM_CON (SPM_BASE + 0x0EB8) 448 #define INFRA_HRE_SRAM_CON (SPM_BASE + 0x0EBC) 449 #define INFRA_SLEEP_SRAM_CON (SPM_BASE + 0x0EC0) 450 #define MML_HRE_SRAM_CON (SPM_BASE + 0x0EC4) 451 #define MM_HRE_SRAM_CON (SPM_BASE + 0x0EC8) 452 #define MM_INFRA_AO_PDN_SRAM_CON (SPM_BASE + 0x0ECC) 453 #define NTH_EMI_SLB_SRAM_CON (SPM_BASE + 0x0ED0) 454 #define PERI_SLEEP_SRAM_CON (SPM_BASE + 0x0ED4) 455 #define SPM_SRAM_CON (SPM_BASE + 0x0ED8) 456 #define SPU_HWROT_SLEEP_SRAM_CON (SPM_BASE + 0x0EDC) 457 #define SPU_ISE_SLEEP_SRAM_CON (SPM_BASE + 0x0EE0) 458 #define SSPM_SRAM_CON (SPM_BASE + 0x0EE4) 459 #define SSR_SLEEP_SRAM_CON (SPM_BASE + 0x0EE8) 460 #define STH_EMI_SLB_SRAM_CON (SPM_BASE + 0x0EEC) 461 #define UFS_SLEEP_SRAM_CON (SPM_BASE + 0x0EF0) 462 #define UNIPRO_PDN_SRAM_CON (SPM_BASE + 0x0EF4) 463 #define CPU_BUCK_ISO_CON (SPM_BASE + 0x0EF8) 464 #define MD_BUCK_ISO_CON (SPM_BASE + 0x0EFC) 465 #define SOC_BUCK_ISO_CON (SPM_BASE + 0x0F00) 466 #define SOC_BUCK_ISO_CON_SET (SPM_BASE + 0x0F0C) 467 #define SOC_BUCK_ISO_CON_CLR (SPM_BASE + 0x0F10) 468 #define PWR_STATUS (SPM_BASE + 0x0F14) 469 #define PWR_STATUS_2ND (SPM_BASE + 0x0F18) 470 #define PWR_STATUS_MSB (SPM_BASE + 0x0F1C) 471 #define PWR_STATUS_MSB_2ND (SPM_BASE + 0x0F20) 472 #define XPU_PWR_STATUS (SPM_BASE + 0x0F24) 473 #define XPU_PWR_STATUS_2ND (SPM_BASE + 0x0F28) 474 #define DFD_SOC_PWR_LATCH (SPM_BASE + 0x0F2C) 475 #define NTH_EMI_SLB_SRAM_ACK (SPM_BASE + 0x0F30) 476 #define STH_EMI_SLB_SRAM_ACK (SPM_BASE + 0x0F34) 477 #define DPYD0_PWR_CON (SPM_BASE + 0x0F38) 478 #define DPYD1_PWR_CON (SPM_BASE + 0x0F3C) 479 #define DPYD2_PWR_CON (SPM_BASE + 0x0F40) 480 #define DPYD3_PWR_CON (SPM_BASE + 0x0F44) 481 #define DPYA0_PWR_CON (SPM_BASE + 0x0F48) 482 #define DPYA1_PWR_CON (SPM_BASE + 0x0F4C) 483 #define DPYA2_PWR_CON (SPM_BASE + 0x0F50) 484 #define DPYA3_PWR_CON (SPM_BASE + 0x0F5C) 485 #define SCP_2_PWR_CON (SPM_BASE + 0x0F60) 486 #define RSV_0_SLEEP_SRAM_CON (SPM_BASE + 0x0F64) 487 #define RSV_1_SLEEP_SRAM_CON (SPM_BASE + 0x0F68) 488 #define APIFR_MEM_SLEEP_SRAM_CON (SPM_BASE + 0x0F6C) 489 #define RSV_0_PWR_CON (SPM_BASE + 0x0F70) 490 #define RSV_1_PWR_CON (SPM_BASE + 0x0F74) 491 #define SPM_TWAM_CON (SPM_BASE + 0x0FD0) 492 #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0FD4) 493 #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0FD8) 494 #define SPM_TWAM_LAST_STA_0 (SPM_BASE + 0x0FDC) 495 #define SPM_TWAM_LAST_STA_1 (SPM_BASE + 0x0FE0) 496 #define SPM_TWAM_LAST_STA_2 (SPM_BASE + 0x0FE4) 497 #define SPM_TWAM_LAST_STA_3 (SPM_BASE + 0x0FE8) 498 #define SPM_TWAM_CURR_STA_0 (SPM_BASE + 0x0FEC) 499 #define SPM_TWAM_CURR_STA_1 (SPM_BASE + 0x0FF0) 500 #define SPM_TWAM_CURR_STA_2 (SPM_BASE + 0x0FF4) 501 #define SPM_TWAM_CURR_STA_3 (SPM_BASE + 0x0FF8) 502 #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x0FFC) 503 #define MD1_SSYSPM_CON (SPM_BASE + 0x9000) 504 #define CONN_SSYSPM_CON (SPM_BASE + 0x9004) 505 #define APIFR_IO_SSYSPM_CON (SPM_BASE + 0x9008) 506 #define APIFR_MEM_SSYSPM_CON (SPM_BASE + 0x900C) 507 #define PERI_SSYSPM_CON (SPM_BASE + 0x9010) 508 #define PERI_ETHER_SSYSPM_CON (SPM_BASE + 0x9014) 509 #define SSUSB_DP_PHY_P0_SSYSPM_CON (SPM_BASE + 0x9018) 510 #define SSUSB_P0_SSYSPM_CON (SPM_BASE + 0x901C) 511 #define SSUSB_P1_SSYSPM_CON (SPM_BASE + 0x9020) 512 #define SSUSB_P23_SSYSPM_CON (SPM_BASE + 0x9024) 513 #define SSUSB_PHY_P2_SSYSPM_CON (SPM_BASE + 0x9028) 514 #define UFS0_SSYSPM_CON (SPM_BASE + 0x902C) 515 #define UFS0_PHY_SSYSPM_CON (SPM_BASE + 0x9030) 516 #define PEXTP_MAC0_SSYSPM_CON (SPM_BASE + 0x9034) 517 #define PEXTP_MAC1_SSYSPM_CON (SPM_BASE + 0x9038) 518 #define PEXTP_MAC2_SSYSPM_CON (SPM_BASE + 0x903C) 519 #define PEXTP_PHY0_SSYSPM_CON (SPM_BASE + 0x9040) 520 #define PEXTP_PHY1_SSYSPM_CON (SPM_BASE + 0x9044) 521 #define PEXTP_PHY2_SSYSPM_CON (SPM_BASE + 0x9048) 522 #define AUDIO_SSYSPM_CON (SPM_BASE + 0x904C) 523 #define ADSP_CORE1_SSYSPM_CON (SPM_BASE + 0x9050) 524 #define ADSP_TOP_SSYSPM_CON (SPM_BASE + 0x9054) 525 #define ADSP_INFRA_SSYSPM_CON (SPM_BASE + 0x9058) 526 #define ADSP_AO_SSYSPM_CON (SPM_BASE + 0x905C) 527 #define MM_PROC_SSYSPM_CON (SPM_BASE + 0x9060) 528 #define SCP_SSYSPM_CON (SPM_BASE + 0x9064) 529 #define SCP_2_SSYSPM_CON (SPM_BASE + 0x9068) 530 #define DPYD0_SSYSPM_CON (SPM_BASE + 0x906C) 531 #define DPYD1_SSYSPM_CON (SPM_BASE + 0x9070) 532 #define DPYD2_SSYSPM_CON (SPM_BASE + 0x9074) 533 #define DPYD3_SSYSPM_CON (SPM_BASE + 0x9078) 534 #define DPYA0_SSYSPM_CON (SPM_BASE + 0x907C) 535 #define DPYA1_SSYSPM_CON (SPM_BASE + 0x9080) 536 #define DPYA2_SSYSPM_CON (SPM_BASE + 0x9084) 537 #define DPYA3_SSYSPM_CON (SPM_BASE + 0x9088) 538 #define DPM0_SSYSPM_CON (SPM_BASE + 0x908C) 539 #define DPM1_SSYSPM_CON (SPM_BASE + 0x9090) 540 #define DPM2_SSYSPM_CON (SPM_BASE + 0x9094) 541 #define DPM3_SSYSPM_CON (SPM_BASE + 0x9098) 542 #define EMI0_SSYSPM_CON (SPM_BASE + 0x909C) 543 #define EMI1_SSYSPM_CON (SPM_BASE + 0x90A0) 544 #define EMI_INFRA_SSYSPM_CON (SPM_BASE + 0x90A4) 545 #define SSRSYS_SSYSPM_CON (SPM_BASE + 0x90A8) 546 #define SPU_ISE_SSYSPM_CON (SPM_BASE + 0x90AC) 547 #define SPU_HWROT_SSYSPM_CON (SPM_BASE + 0x90B0) 548 #define VLP_SSYSPM_CON (SPM_BASE + 0x90B4) 549 #define HSGMII0_SSYSPM_CON (SPM_BASE + 0x90B8) 550 #define HSGMII1_SSYSPM_CON (SPM_BASE + 0x90BC) 551 #define MFG_VLP_SSYSPM_CON (SPM_BASE + 0x90C0) 552 #define MCUSYS_BUSBLK_SSYSPM_CON (SPM_BASE + 0x90C4) 553 #define RSV_0_SSYSPM_CON (SPM_BASE + 0x90C8) 554 #define RSV_1_SSYSPM_CON (SPM_BASE + 0x90CC) 555 #define CPUEB_SSYSPM_CON (SPM_BASE + 0x90D0) 556 #define MFG0_SSYSPM_CON (SPM_BASE + 0x90D4) 557 #define BUS_PROTECT_CON (SPM_BASE + 0x90D8) 558 #define BUS_PROTECT_CON_SET (SPM_BASE + 0x90DC) 559 #define BUS_PROTECT_CON_CLR (SPM_BASE + 0x90E0) 560 #define BUS_PROTECT_MSB_CON (SPM_BASE + 0x90E4) 561 #define BUS_PROTECT_MSB_CON_SET (SPM_BASE + 0x90E8) 562 #define BUS_PROTECT_MSB_CON_CLR (SPM_BASE + 0x90EC) 563 #define BUS_PROTECT_CG_CON (SPM_BASE + 0x90F0) 564 #define BUS_PROTECT_CG_CON_SET (SPM_BASE + 0x90F4) 565 #define BUS_PROTECT_CG_CON_CLR (SPM_BASE + 0x90F8) 566 #define BUS_PROTECT_CG_MSB_CON (SPM_BASE + 0x90FC) 567 #define ALCO_EN (SPM_BASE + 0x9100) 568 #define ALCO_SW_RST (SPM_BASE + 0x9104) 569 #define ALCO_CONFIG_0 (SPM_BASE + 0x9108) 570 #define ALCO_CAND_MUX_SEL (SPM_BASE + 0x910C) 571 #define ALCO_SLEEP_SRAM_CON (SPM_BASE + 0x9110) 572 #define ALCO_COMP_VAL (SPM_BASE + 0x9114) 573 #define ALCO_VCORE_REQ_SEL (SPM_BASE + 0x9118) 574 #define ALCO_VCORE_ACK_SEL (SPM_BASE + 0x911C) 575 #define ALCO_PMIC_REQ_SEL (SPM_BASE + 0x9120) 576 #define ALCO_PMIC_ACK_SEL (SPM_BASE + 0x9124) 577 #define ALCO_26M_REQ_SEL (SPM_BASE + 0x9128) 578 #define ALCO_26M_ACK_SEL (SPM_BASE + 0x912C) 579 #define ALCO_INFRA_REQ_SEL (SPM_BASE + 0x9130) 580 #define ALCO_INFRA_ACK_SEL (SPM_BASE + 0x9134) 581 #define ALCO_BUSPLL_REQ_SEL (SPM_BASE + 0x9138) 582 #define ALCO_BUSPLL_ACK_SEL (SPM_BASE + 0x913C) 583 #define ALCO_EMI_REQ_SEL (SPM_BASE + 0x9140) 584 #define ALCO_EMI_ACK_SEL (SPM_BASE + 0x9144) 585 #define ALCO_APSRC_REQ_SEL (SPM_BASE + 0x9148) 586 #define ALCO_APSRC_ACK_SEL (SPM_BASE + 0x914C) 587 #define ALCO_DDREN_REQ_SEL (SPM_BASE + 0x9150) 588 #define ALCO_DDREN_ACK_SEL (SPM_BASE + 0x9154) 589 #define ALCO_MTCMOS_PWR_ON_SEL (SPM_BASE + 0x9158) 590 #define ALCO_MTCMOS_PWR_ACK_SEL (SPM_BASE + 0x915C) 591 #define ALCO_MON_MODE_0 (SPM_BASE + 0x9160) 592 #define ALCO_MON_MODE_1 (SPM_BASE + 0x9164) 593 #define ALCO_BIT_SEQ_0 (SPM_BASE + 0x9168) 594 #define ALCO_BIT_SEQ_1 (SPM_BASE + 0x916C) 595 #define ALCO_BIT_EN (SPM_BASE + 0x9170) 596 #define ALCO_TIMER_LSB (SPM_BASE + 0x9174) 597 #define ALCO_TIMER_MSB (SPM_BASE + 0x9178) 598 #define ALCO_TRIG_ADDR (SPM_BASE + 0x917C) 599 #define ALCO_STA (SPM_BASE + 0x9180) 600 #define ALCO_LEVEL_MAX_TIME (SPM_BASE + 0x9184) 601 #define ALCO_RSV_0 (SPM_BASE + 0x9188) 602 #define ALCO_RSV_1 (SPM_BASE + 0x918C) 603 #define ALCO_RSV_2 (SPM_BASE + 0x9190) 604 #define ALCO_RSV_3 (SPM_BASE + 0x9194) 605 #define ALCO_RSV_4 (SPM_BASE + 0x9198) 606 #define ALCO_RSV_5 (SPM_BASE + 0x919C) 607 #define BUS_PROTECT_CG_MSB_CON_SET (SPM_BASE + 0x9200) 608 #define BUS_PROTECT_CG_MSB_CON_CLR (SPM_BASE + 0x9204) 609 #define BUS_PROTECT_RDY (SPM_BASE + 0x9208) 610 #define BUS_PROTECT_RDY_MSB (SPM_BASE + 0x920C) 611 #define SPM_RSV_CSOPLU_REQ (SPM_BASE + 0x9210) 612 #define SPM_SW_RSV_VCORE_REQ_CON (SPM_BASE + 0x9214) 613 #define SPM_SW_RSV_VCORE_REQ_CON_SET (SPM_BASE + 0x9218) 614 #define SPM_SW_RSV_VCORE_REQ_CON_CLR (SPM_BASE + 0x921C) 615 #define SPM_LTECLKSQ_BG_OFF (SPM_BASE + 0x9220) 616 #define PBUS_VCORE_PKT_CTRL (SPM_BASE + 0x9300) 617 #define PBUS_VLP_PKT_CTRL (SPM_BASE + 0x9304) 618 #define PBUS_VLP_PKT_DATA_0 (SPM_BASE + 0x9310) 619 #define PBUS_VLP_PKT_DATA_1 (SPM_BASE + 0x9314) 620 #define PBUS_VLP_PKT_DATA_2 (SPM_BASE + 0x9318) 621 #define PBUS_VLP_PKT_DATA_3 (SPM_BASE + 0x931C) 622 #define PBUS_VCORE_PKT_DATA_0 (SPM_BASE + 0x9320) 623 #define PBUS_VCORE_PKT_DATA_1 (SPM_BASE + 0x9324) 624 #define PBUS_VCORE_PKT_DATA_2 (SPM_BASE + 0x9328) 625 #define PBUS_VCORE_PKT_DATA_3 (SPM_BASE + 0x932C) 626 #define PBUS_VCORE_CTRL (SPM_BASE + 0x9330) 627 #define PBUS_VLP_CTRL (SPM_BASE + 0x9334) 628 #define PBUS_VCORE_RX_PKT_CTRL (SPM_BASE + 0x9340) 629 #define PBUS_VLP_RX_PKT_CTRL (SPM_BASE + 0x9344) 630 #define PBUS_VLP_RX_PKT_DATA_0 (SPM_BASE + 0x9350) 631 #define PBUS_VLP_RX_PKT_DATA_1 (SPM_BASE + 0x9354) 632 #define PBUS_VLP_RX_PKT_DATA_2 (SPM_BASE + 0x9358) 633 #define PBUS_VLP_RX_PKT_DATA_3 (SPM_BASE + 0x935C) 634 #define PBUS_VCORE_RX_PKT_DATA_0 (SPM_BASE + 0x9360) 635 #define PBUS_VCORE_RX_PKT_DATA_1 (SPM_BASE + 0x9364) 636 #define PBUS_VCORE_RX_PKT_DATA_2 (SPM_BASE + 0x9368) 637 #define PBUS_VCORE_RX_PKT_DATA_3 (SPM_BASE + 0x936C) 638 #define PCM_WDT_LATCH_0 (SPM_BASE + 0x9500) 639 #define PCM_WDT_LATCH_1 (SPM_BASE + 0x9504) 640 #define PCM_WDT_LATCH_2 (SPM_BASE + 0x9508) 641 #define PCM_WDT_LATCH_3 (SPM_BASE + 0x950C) 642 #define PCM_WDT_LATCH_4 (SPM_BASE + 0x9510) 643 #define PCM_WDT_LATCH_5 (SPM_BASE + 0x9514) 644 #define PCM_WDT_LATCH_6 (SPM_BASE + 0x9518) 645 #define PCM_WDT_LATCH_7 (SPM_BASE + 0x951C) 646 #define PCM_WDT_LATCH_8 (SPM_BASE + 0x9520) 647 #define PCM_WDT_LATCH_9 (SPM_BASE + 0x9524) 648 #define PCM_WDT_LATCH_10 (SPM_BASE + 0x9528) 649 #define PCM_WDT_LATCH_11 (SPM_BASE + 0x952C) 650 #define PCM_WDT_LATCH_12 (SPM_BASE + 0x9530) 651 #define PCM_WDT_LATCH_13 (SPM_BASE + 0x9534) 652 #define PCM_WDT_LATCH_14 (SPM_BASE + 0x9538) 653 #define PCM_WDT_LATCH_15 (SPM_BASE + 0x953C) 654 #define PCM_WDT_LATCH_16 (SPM_BASE + 0x9540) 655 #define PCM_WDT_LATCH_17 (SPM_BASE + 0x9544) 656 #define PCM_WDT_LATCH_18 (SPM_BASE + 0x9548) 657 #define PCM_WDT_LATCH_19 (SPM_BASE + 0x954C) 658 #define PCM_WDT_LATCH_20 (SPM_BASE + 0x9550) 659 #define PCM_WDT_LATCH_21 (SPM_BASE + 0x9554) 660 #define PCM_WDT_LATCH_22 (SPM_BASE + 0x9558) 661 #define PCM_WDT_LATCH_23 (SPM_BASE + 0x955C) 662 #define PCM_WDT_LATCH_24 (SPM_BASE + 0x9560) 663 #define PCM_WDT_LATCH_25 (SPM_BASE + 0x9564) 664 #define PCM_WDT_LATCH_26 (SPM_BASE + 0x9568) 665 #define PCM_WDT_LATCH_27 (SPM_BASE + 0x956C) 666 #define PCM_WDT_LATCH_28 (SPM_BASE + 0x9570) 667 #define PCM_WDT_LATCH_29 (SPM_BASE + 0x9574) 668 #define PCM_WDT_LATCH_30 (SPM_BASE + 0x9578) 669 #define PCM_WDT_LATCH_31 (SPM_BASE + 0x957C) 670 #define PCM_WDT_LATCH_32 (SPM_BASE + 0x9580) 671 #define PCM_WDT_LATCH_33 (SPM_BASE + 0x9584) 672 #define PCM_WDT_LATCH_34 (SPM_BASE + 0x9588) 673 #define PCM_WDT_LATCH_35 (SPM_BASE + 0x958C) 674 #define PCM_WDT_LATCH_36 (SPM_BASE + 0x9590) 675 #define PCM_WDT_LATCH_37 (SPM_BASE + 0x9594) 676 #define PCM_WDT_LATCH_38 (SPM_BASE + 0x9598) 677 #define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x959C) 678 #define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x95A0) 679 #define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x95A4) 680 #define PCM_WDT_LATCH_SPARE_3 (SPM_BASE + 0x95A8) 681 #define PCM_WDT_LATCH_SPARE_4 (SPM_BASE + 0x95AC) 682 #define PCM_WDT_LATCH_SPARE_5 (SPM_BASE + 0x95B0) 683 #define PCM_WDT_LATCH_SPARE_6 (SPM_BASE + 0x95B4) 684 #define PCM_WDT_LATCH_SPARE_7 (SPM_BASE + 0x95B8) 685 #define PCM_WDT_LATCH_SPARE_8 (SPM_BASE + 0x95BC) 686 #define PCM_WDT_LATCH_SPARE_9 (SPM_BASE + 0x95C0) 687 #define DRAMC_GATING_ERR_LATCH_0 (SPM_BASE + 0x95C4) 688 #define DRAMC_GATING_ERR_LATCH_1 (SPM_BASE + 0x95C8) 689 #define DRAMC_GATING_ERR_LATCH_2 (SPM_BASE + 0x95CC) 690 #define DRAMC_GATING_ERR_LATCH_3 (SPM_BASE + 0x95D0) 691 #define DRAMC_GATING_ERR_LATCH_4 (SPM_BASE + 0x95D4) 692 #define DRAMC_GATING_ERR_LATCH_5 (SPM_BASE + 0x95D8) 693 #define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x95DC) 694 #define SPM_DEBUG_CON (SPM_BASE + 0x95E0) 695 #define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x95E4) 696 #define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x95E8) 697 #define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x95EC) 698 #define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x95F0) 699 #define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x95F4) 700 #define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x95F8) 701 #define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x95FC) 702 #define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x9600) 703 #define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x9604) 704 #define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x9608) 705 #define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x960C) 706 #define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x9610) 707 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x9614) 708 #define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x9618) 709 #define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x961C) 710 #define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x9620) 711 #define PCM_APWDT_LATCH_0 (SPM_BASE + 0x9630) 712 #define PCM_APWDT_LATCH_1 (SPM_BASE + 0x9634) 713 #define PCM_APWDT_LATCH_2 (SPM_BASE + 0x9638) 714 #define PCM_APWDT_LATCH_3 (SPM_BASE + 0x963C) 715 #define PCM_APWDT_LATCH_4 (SPM_BASE + 0x9640) 716 #define PCM_APWDT_LATCH_5 (SPM_BASE + 0x9644) 717 #define PCM_APWDT_LATCH_6 (SPM_BASE + 0x9648) 718 #define PCM_APWDT_LATCH_7 (SPM_BASE + 0x964C) 719 #define PCM_APWDT_LATCH_8 (SPM_BASE + 0x9650) 720 #define PCM_APWDT_LATCH_9 (SPM_BASE + 0x9654) 721 #define PCM_APWDT_LATCH_10 (SPM_BASE + 0x9658) 722 #define PCM_APWDT_LATCH_11 (SPM_BASE + 0x965C) 723 #define PCM_APWDT_LATCH_12 (SPM_BASE + 0x9660) 724 #define PCM_APWDT_LATCH_13 (SPM_BASE + 0x9664) 725 #define PCM_APWDT_LATCH_14 (SPM_BASE + 0x9668) 726 #define PCM_APWDT_LATCH_15 (SPM_BASE + 0x966C) 727 #define PCM_APWDT_LATCH_16 (SPM_BASE + 0x9670) 728 #define PCM_APWDT_LATCH_17 (SPM_BASE + 0x9674) 729 #define PCM_APWDT_LATCH_18 (SPM_BASE + 0x9678) 730 #define PCM_APWDT_LATCH_19 (SPM_BASE + 0x967C) 731 #define PCM_APWDT_LATCH_20 (SPM_BASE + 0x9680) 732 #define PCM_APWDT_LATCH_21 (SPM_BASE + 0x9684) 733 #define PCM_APWDT_LATCH_22 (SPM_BASE + 0x9688) 734 #define PCM_APWDT_LATCH_23 (SPM_BASE + 0x968C) 735 #define PCM_APWDT_LATCH_24 (SPM_BASE + 0x9690) 736 #define PCM_APWDT_LATCH_25 (SPM_BASE + 0x9694) 737 #define PCM_APWDT_LATCH_26 (SPM_BASE + 0x9698) 738 #define PCM_APWDT_LATCH_27 (SPM_BASE + 0x96A4) 739 #define PCM_APWDT_LATCH_28 (SPM_BASE + 0x96A8) 740 #define PCM_APWDT_LATCH_29 (SPM_BASE + 0x96AC) 741 #define PCM_APWDT_LATCH_30 (SPM_BASE + 0x96B0) 742 #define PCM_APWDT_LATCH_31 (SPM_BASE + 0x96B4) 743 #define PCM_APWDT_LATCH_32 (SPM_BASE + 0x96B8) 744 #define PCM_APWDT_LATCH_33 (SPM_BASE + 0x96BC) 745 #define PCM_APWDT_LATCH_34 (SPM_BASE + 0x96C0) 746 #define PCM_APWDT_LATCH_35 (SPM_BASE + 0x96C4) 747 #define PCM_APWDT_LATCH_36 (SPM_BASE + 0x96C8) 748 #define PCM_APWDT_LATCH_37 (SPM_BASE + 0x96CC) 749 #define PCM_APWDT_LATCH_38 (SPM_BASE + 0x96D0) 750 751 #define MODE_SET 0x1002d3d8 752 #define SET_GPIO_MODE 0x70000000 753 754 #define MODE_BACKUP_REG 0x1002d3d0 755 #define DIR_BACKUP_REG 0x1002d030 756 #define DOUT_BACKUP_REG 0x1002d130 757 758 #define EC_SUSPEND_PIN 38 759 #define EC_SUSPEND_BK_PIN 111 760 761 /* POWERON_CONFIG_EN (0x1C004000+0x0) */ 762 #define BCLK_CG_EN_LSB BIT(0) 763 #define PROJECT_CODE_LSB BIT(16) 764 #define POWER_ON_VAL0_LSB BIT(0) 765 #define POWER_ON_VAL1_LSB BIT(0) 766 #define POWER_ON_VAL2_LSB BIT(0) 767 #define POWER_ON_VAL3_LSB BIT(0) 768 #define PCM_PWR_IO_EN_LSB BIT(0) 769 #define PCM_CK_EN_LSB BIT(2) 770 #define PCM_SW_RESET_LSB BIT(15) 771 #define PCM_CON0_PROJECT_CODE_LSB BIT(16) 772 #define REG_SPM_APB_INTERNAL_EN_LSB BIT(3) 773 #define REG_PCM_TIMER_EN_LSB BIT(5) 774 #define REG_PCM_WDT_EN_LSB BIT(8) 775 #define REG_PCM_WDT_WAKE_LSB BIT(9) 776 #define REG_SSPM_APB_P2P_EN_LSB BIT(10) 777 #define REG_MCUPM_APB_P2P_EN_LSB BIT(11) 778 #define REG_RSV_APB_P2P_EN_LSB BIT(12) 779 #define RG_PCM_IRQ_MSK_LSB BIT(15) 780 #define PCM_CON1_PROJECT_CODE_LSB BIT(16) 781 #define REG_SRAM_ISO_ACTIVE_LSB BIT(0) 782 #define REG_SRAM_SLP2ISO_TIME_LSB BIT(8) 783 #define REG_SPM_SRAM_CTRL_MUX_LSB BIT(16) 784 #define REG_SRAM_SLEEP_TIME_LSB BIT(24) 785 #define REG_SPM_LOCK_INFRA_DCM_LSB BIT(0) 786 #define REG_CXO32K_REMOVE_EN_LSB BIT(1) 787 #define REG_SPM_LEAVE_SUSPEND_MERGE_MASK_LSB BIT(4) 788 #define REG_SRCLKENO0_SRC_MB_LSB BIT(8) 789 #define REG_SRCLKENO1_SRC_MB_LSB BIT(16) 790 #define REG_SRCLKENO2_SRC_MB_LSB BIT(24) 791 #define SYSCLK_SETTLE_LSB BIT(0) 792 #define SPM_SW_RST_CON_LSB BIT(0) 793 #define SPM_SW_RST_CON_PROJECT_CODE_LSB BIT(16) 794 #define SPM_SW_RST_CON_SET_LSB BIT(0) 795 #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB BIT(16) 796 #define SPM_SW_RST_CON_CLR_LSB BIT(0) 797 #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB BIT(16) 798 #define SPM_SEC_READ_MASK_LSB BIT(0) 799 #define SPM_ONE_TIME_LOCK_L_LSB BIT(0) 800 #define SPM_ONE_TIME_LOCK_M_LSB BIT(0) 801 #define SPM_ONE_TIME_LOCK_H_LSB BIT(0) 802 #define REG_SSPM_26M_CK_SEL_LSB BIT(0) 803 #define REG_SSPM_DCM_EN_LSB BIT(1) 804 #define REG_SCP_26M_CK_SEL_LSB BIT(0) 805 #define REG_SCP_DCM_EN_LSB BIT(1) 806 #define SCP_SECURE_VREQ_MASK_LSB BIT(2) 807 #define SCP_SLP_REQ_LSB BIT(3) 808 #define SCP_SLP_ACK_LSB BIT(4) 809 #define SPM_SWINT_LSB BIT(0) 810 #define SPM_SWINT_SET_LSB BIT(0) 811 #define SPM_SWINT_CLR_LSB BIT(0) 812 #define REG_CPU_WAKEUP_LSB BIT(0) 813 #define REG_SPM_IRQ_MASK_LSB BIT(0) 814 #define MD32PCM_CTRL0_LSB BIT(0) 815 #define MD32PCM_CTRL1_LSB BIT(0) 816 #define MD32PCM_CTRL2_LSB BIT(0) 817 #define MD32PCM_CTRL3_LSB BIT(0) 818 #define MD32PCM_STA0_LSB BIT(0) 819 #define PCM_IRQ_LSB BIT(3) 820 #define MD32PCM_WAKEUP_STA_LSB BIT(0) 821 #define MD32PCM_EVENT_STA_LSB BIT(0) 822 #define SRCLKEN_RC_ERR_INT_LSB BIT(0) 823 #define SPM_TIMEOUT_WAKEUP_0_LSB BIT(1) 824 #define SPM_TIMEOUT_WAKEUP_1_LSB BIT(2) 825 #define SPM_TIMEOUT_WAKEUP_2_LSB BIT(3) 826 #define DVFSRC_IRQ_LSB BIT(4) 827 #define TWAM_IRQ_B_LSB BIT(5) 828 #define SPM_ACK_CHK_WAKEUP_0_LSB BIT(6) 829 #define SPM_ACK_CHK_WAKEUP_1_LSB BIT(7) 830 #define SPM_ACK_CHK_WAKEUP_2_LSB BIT(8) 831 #define SPM_ACK_CHK_WAKEUP_3_LSB BIT(9) 832 #define SPM_ACK_CHK_WAKEUP_ALL_LSB BIT(10) 833 #define VLP_BUS_TIMEOUT_IRQ_LSB BIT(11) 834 #define PCM_TIMER_EVENT_LSB BIT(16) 835 #define PMIC_EINT_OUT_LSB BIT(19) 836 #define PMIC_IRQ_ACK_LSB BIT(30) 837 #define PMIC_SCP_IRQ_LSB BIT(31) 838 #define PCM_CK_SEL_O_LSB BIT(0) 839 #define EXT_SRC_STA_LSB BIT(4) 840 #define CK_SLEEP_EN_LSB BIT(8) 841 #define SPM_SRAM_CTRL_CK_SEL_LSB BIT(9) 842 #define MD32PCM_HALT_LSB BIT(0) 843 #define MD32PCM_GATED_LSB BIT(1) 844 #define MON_PC_LSB BIT(0) 845 #define REG_CSOPLU_EN_CG_SLOW_MODE_LSB BIT(0) 846 #define REG_CSOPLU_EN_CG_LEN_LSB BIT(4) 847 #define REG_PCM_CSOPLU_RMB_LSB BIT(16) 848 #define REG_CSOPLU_ACK_LEN_LSB BIT(0) 849 #define SC_REG_UPLOSC_MODE_SEL_LSB BIT(0) 850 #define DA_OSC_EN_32K_LSB BIT(4) 851 #define CSOPLU_ACK_LSB BIT(0) 852 #define SPM_CSOPLU_INTERNAL_ACK_LSB BIT(16) 853 #define REG_CSOPLU_RMB_LSB BIT(0) 854 #define REG_CSOPLU_ACK_MASK_LSB BIT(16) 855 #define SPM_APSRC_REQ_BLOCK_LSB BIT(0) 856 #define SPM_DDREN_REQ_BLOCK_LSB BIT(1) 857 #define SPM_VRF18_REQ_BLOCK_LSB BIT(2) 858 #define SPM_INFRA_REQ_BLOCK_LSB BIT(3) 859 #define SPM_EMI_REQ_BLOCK_LSB BIT(4) 860 #define SPM_SRCCLKENA_REQ_BLOCK_LSB BIT(5) 861 #define SPM_PMIC_REQ_BLOCK_LSB BIT(6) 862 #define SPM_VCORE_REQ_BLOCK_LSB BIT(7) 863 #define IPS_DVFS_DELTA_LSB BIT(0) 864 #define SPM_AXI_CK_EN_LSB BIT(0) 865 #define SPM_MEM_SUB_CK_EN_LSB BIT(1) 866 #define SPM_IO_NOC_CK_EN_LSB BIT(2) 867 #define TOP_CKSYS_RSV_CON_LSB BIT(3) 868 #define REG_WFI_OP_LSB BIT(0) 869 #define REG_WFI_TYPE_LSB BIT(1) 870 #define REG_MP0_CPUTOP_IDLE_MASK_LSB BIT(2) 871 #define REG_MP1_CPUTOP_IDLE_MASK_LSB BIT(3) 872 #define REG_MCUSYS_IDLE_MASK_LSB BIT(4) 873 #define REG_CSYSPWRUP_REQ_MASK_LSB BIT(5) 874 #define WFI_AF_SEL_LSB BIT(16) 875 #define CPU_SLEEP_WFI_LSB BIT(31) 876 #define CPU_WFI_EN_LSB BIT(0) 877 #define CPU_WFI_EN_SET_LSB BIT(0) 878 #define CPU_WFI_EN_CLR_LSB BIT(0) 879 #define EXT_INT_WAKEUP_REQ_LSB BIT(0) 880 #define EXT_INT_WAKEUP_REQ_SET_LSB BIT(0) 881 #define EXT_INT_WAKEUP_REQ_CLR_LSB BIT(0) 882 #define MCUSYS_DDREN_LSB BIT(0) 883 #define ARMBUS_IDLE_TO_26M_LSB BIT(8) 884 #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB BIT(9) 885 #define MP0_CPU_IDLE_TO_PWR_OFF_LSB BIT(16) 886 #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB BIT(0) 887 #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB BIT(1) 888 #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB BIT(2) 889 #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB BIT(3) 890 #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB BIT(4) 891 #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB BIT(5) 892 #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB BIT(6) 893 #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB BIT(7) 894 #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB BIT(8) 895 #define MCUSYS_SPMC_PWR_ON_ACK_LSB BIT(9) 896 #define SW2SPM_WAKEUP_LSB BIT(0) 897 #define SW2SPM_WAKEUP_SET_LSB BIT(0) 898 #define SW2SPM_WAKEUP_CLR_LSB BIT(0) 899 #define SW2SPM_MAILBOX_0_LSB BIT(0) 900 #define SW2SPM_MAILBOX_1_LSB BIT(0) 901 #define SW2SPM_MAILBOX_2_LSB BIT(0) 902 #define SW2SPM_MAILBOX_3_LSB BIT(0) 903 #define SPM2SW_MAILBOX_0_LSB BIT(0) 904 #define SPM2SW_MAILBOX_1_LSB BIT(0) 905 #define SPM2SW_MAILBOX_2_LSB BIT(0) 906 #define SPM2SW_MAILBOX_3_LSB BIT(0) 907 #define CPUEB_STATE_VALID_LSB BIT(0) 908 #define REQ_PWR_ON_LSB BIT(1) 909 #define REQ_MEM_RET_LSB BIT(2) 910 #define RESET_PWR_ON_LSB BIT(4) 911 #define RESET_MEM_RET_LSB BIT(5) 912 #define CPUEB_STATE_FINISH_ACK_LSB BIT(31) 913 #define MCUSYS_D7X_STATUS_LSB BIT(0) 914 #define MCUSYS_VCORE_DEBUG_LSB BIT(1) 915 #define DPSW_MCUSYS_ISO_LSB BIT(2) 916 #define VMCU_VLP_ISO_LSB BIT(3) 917 #define AOC_VMCU_SRAM_ISO_DIN_LSB BIT(4) 918 #define AOC_VMCU_SRAM_LATCH_ENB_LSB BIT(5) 919 #define AOC_VMCU_ANA_ISO_LSB BIT(6) 920 #define P2P_TX_STA_LSB BIT(0) 921 #define REG_P2P_TX_ERROR_FLAG_EN_LSB BIT(0) 922 #define SC_HW_S1_REQ_LSB BIT(0) 923 #define SC_HW_S1_WLA_MEMSYS_ACK_LSB BIT(1) 924 #define REG_HW_S1_ACK_MASK_LSB BIT(4) 925 #define SC_HW_S1_ACK_LSB BIT(8) 926 #define SC_DPM2SPM_PST_ACK_LSB BIT(16) 927 #define SC_DPM_WFI_STA_LSB BIT(20) 928 #define SC_SPM_WLA_MEMSYS_DDREN_REQ_LSB BIT(24) 929 #define SC_SPM_WLA_MEMSYS_DDREN_URGENT_LSB BIT(25) 930 #define SC_SPM_WLA_MEMSYS_DDREN_ACK_LSB BIT(28) 931 #define REG_DPM_WB_EN_LSB BIT(0) 932 #define SPM_PWRAP_CON_LSB BIT(0) 933 #define SPM_PWRAP_CON_STA_LSB BIT(0) 934 #define SPM_PMIC_SPMI_CMD_LSB BIT(0) 935 #define SPM_PMIC_SPMI_SLAVEID_LSB BIT(2) 936 #define SPM_PMIC_SPMI_PMIFID_LSB BIT(6) 937 #define SPM_PMIC_SPMI_DBCNT_LSB BIT(7) 938 #define SPM_PWRAP_CMD0_LSB BIT(0) 939 #define SPM_PWRAP_CMD1_LSB BIT(0) 940 #define SPM_PWRAP_CMD2_LSB BIT(0) 941 #define SPM_PWRAP_CMD3_LSB BIT(0) 942 #define SPM_PWRAP_CMD4_LSB BIT(0) 943 #define SPM_PWRAP_CMD5_LSB BIT(0) 944 #define SPM_PWRAP_CMD6_LSB BIT(0) 945 #define SPM_PWRAP_CMD7_LSB BIT(0) 946 #define SPM_PWRAP_CMD8_LSB BIT(0) 947 #define SPM_PWRAP_CMD9_LSB BIT(0) 948 #define SPM_PWRAP_CMD10_LSB BIT(0) 949 #define SPM_PWRAP_CMD11_LSB BIT(0) 950 #define SPM_PWRAP_CMD12_LSB BIT(0) 951 #define SPM_PWRAP_CMD13_LSB BIT(0) 952 #define SPM_PWRAP_CMD14_LSB BIT(0) 953 #define SPM_PWRAP_CMD15_LSB BIT(0) 954 #define SPM_PWRAP_CMD16_LSB BIT(0) 955 #define SPM_PWRAP_CMD17_LSB BIT(0) 956 #define SPM_PWRAP_CMD18_LSB BIT(0) 957 #define SPM_PWRAP_CMD19_LSB BIT(0) 958 #define SPM_PWRAP_CMD20_LSB BIT(0) 959 #define SPM_PWRAP_CMD21_LSB BIT(0) 960 #define SPM_PWRAP_CMD22_LSB BIT(0) 961 #define SPM_PWRAP_CMD23_LSB BIT(0) 962 #define SPM_PWRAP_CMD24_LSB BIT(0) 963 #define SPM_PWRAP_CMD25_LSB BIT(0) 964 #define SPM_PWRAP_CMD26_LSB BIT(0) 965 #define SPM_PWRAP_CMD27_LSB BIT(0) 966 #define SPM_PWRAP_CMD28_LSB BIT(0) 967 #define SPM_PWRAP_CMD29_LSB BIT(0) 968 #define SPM_PWRAP_CMD30_LSB BIT(0) 969 #define SPM_PWRAP_CMD31_LSB BIT(0) 970 #define DVFSRC_EVENT_LSB BIT(0) 971 #define FORCE_DVFS_LEVEL_LSB BIT(0) 972 #define TARGET_DVFS_LEVEL_LSB BIT(0) 973 #define SPM_EMI_DFS_LEVEL_LSB BIT(0) 974 #define SPM_DDR_DFS_LEVEL_LSB BIT(12) 975 #define SPM_DVS_LEVEL_LSB BIT(24) 976 #define SPM_DVFS_LEVEL_LSB BIT(0) 977 #define SPM_DVFS_OPP_LSB BIT(0) 978 #define SPM2MM_FORCE_ULTRA_LSB BIT(0) 979 #define SPM2MM_DBL_OSTD_ACT_LSB BIT(1) 980 #define SPM2MM_ULTRAREQ_LSB BIT(2) 981 #define SPM2MD_ULTRAREQ_LSB BIT(3) 982 #define SPM2ISP_ULTRAREQ_LSB BIT(4) 983 #define SPM2ISP_ULTRAACK_D2T_LSB BIT(18) 984 #define SPM2MM_ULTRAACK_D2T_LSB BIT(19) 985 #define SPM2MD_ULTRAACK_D2T_LSB BIT(20) 986 #define SPM_DVFS_FORCE_ENABLE_LSB BIT(2) 987 #define FORCE_DVFS_WAKE_LSB BIT(3) 988 #define SPM_DVFSRC_ENABLE_LSB BIT(4) 989 #define DVFSRC_WAKEUP_EVENT_MASK_LSB BIT(6) 990 #define SPM2RC_EVENT_ABORT_LSB BIT(7) 991 #define DVFSRC_LEVEL_ACK_LSB BIT(8) 992 #define VSRAM_GEAR_REQ_LSB BIT(0) 993 #define VSRAM_GEAR_RDY_LSB BIT(4) 994 #define VSRAM_VAL_LEVEL_LSB BIT(16) 995 #define SPM_PMIF_VALID_LSB BIT(0) 996 #define SPM_PMIF_ACK_LSB BIT(4) 997 #define DPSW_VAPU_ISO_LSB BIT(0) 998 #define DPSW_VAPU_ISO_SWITCH_LSB BIT(4) 999 #define DPSW_VMM_ISO_LSB BIT(0) 1000 #define DPSW_VMM_ISO_SWITCH_LSB BIT(4) 1001 #define DPSW_VMD_ISO_LSB BIT(0) 1002 #define DPSW_VMD_ISO_SWITCH_LSB BIT(4) 1003 #define DPSW_VMODEM_ISO_LSB BIT(0) 1004 #define DPSW_VMODEM_ISO_SWITCH_LSB BIT(4) 1005 #define DPSW_VCORE_ISO_LSB BIT(0) 1006 #define DPSW_VCORE_ISO_SWITCH_LSB BIT(4) 1007 #define SPM2DPSW_CTRL_REQ_SOC_LSB BIT(0) 1008 #define SPM2DPSW_CTRL_REQ_PCIE_0_LSB BIT(1) 1009 #define SPM2DPSW_CTRL_REQ_PCIE_1_LSB BIT(2) 1010 #define SPM2DPSW_CTRL_REQ_USB_LSB BIT(3) 1011 #define SPM2DPSW_CTRL_REQ_CPU_CORE_LSB BIT(4) 1012 #define SPM2DPSW_CTRL_REQ_MD_LSB BIT(5) 1013 #define SPM2DPSW_CTRL_ISO_SOC_LSB BIT(8) 1014 #define SPM2DPSW_CTRL_ISO_PCIE_0_LSB BIT(9) 1015 #define SPM2DPSW_CTRL_ISO_PCIE_1_LSB BIT(10) 1016 #define SPM2DPSW_CTRL_ISO_USB_LSB BIT(11) 1017 #define SPM2DPSW_CTRL_ISO_CPU_CORE_LSB BIT(12) 1018 #define SPM2DPSW_CTRL_ISO_MD_LSB BIT(13) 1019 #define DPSW_AOCISO_SOC_LSB BIT(0) 1020 #define DPSW_AOCISO_VMM_LSB BIT(1) 1021 #define DPSW_AOCISO_VAPU_LSB BIT(2) 1022 #define DPSW_AOCISO_MD_LSB BIT(3) 1023 #define DPSW_AOCSIO_SWITCH_SOC_LSB BIT(8) 1024 #define DPSW_AOCSIO_SWITCH_VMM_LSB BIT(9) 1025 #define DPSW_AOCSIO_SWITCH_VAPU_LSB BIT(10) 1026 #define DPSW_AOCSIO_SWITCH_MD_LSB BIT(11) 1027 #define DPSW_FORCE_UP_OUT_SOC_LSB BIT(0) 1028 #define DPSW_FORCE_UP_OUT_PCIE_0_LSB BIT(1) 1029 #define DPSW_FORCE_UP_OUT_PCIE_1_LSB BIT(2) 1030 #define DPSW_FORCE_UP_OUT_USB_LSB BIT(3) 1031 #define DPSW_FORCE_UP_OUT_CPU_CORE_LSB BIT(4) 1032 #define DPSW_FORCE_UP_OUT_MD_LSB BIT(5) 1033 #define DPSW_FORCE_DN_OUT_SOC_LSB BIT(8) 1034 #define DPSW_FORCE_DN_OUT_PCIE_0_LSB BIT(9) 1035 #define DPSW_FORCE_DN_OUT_PCIE_1_LSB BIT(10) 1036 #define DPSW_FORCE_DN_OUT_USB_LSB BIT(11) 1037 #define DPSW_FORCE_DN_OUT_CPU_CORE_LSB BIT(12) 1038 #define DPSW_FORCE_DN_OUT_MD_LSB BIT(13) 1039 #define SPM2DPSW_CTRL_VSRAM_ACK_SOC_LSB BIT(0) 1040 #define SPM2DPSW_CTRL_VSRAM_ACK_PCIE_0_LSB BIT(1) 1041 #define SPM2DPSW_CTRL_VSRAM_ACK_PCIE_1_LSB BIT(2) 1042 #define SPM2DPSW_CTRL_VSRAM_ACK_USB_LSB BIT(3) 1043 #define SPM2DPSW_CTRL_VSRAM_ACK_CPU_CORE_LSB BIT(4) 1044 #define SPM2DPSW_CTRL_VSRAM_ACK_MD_LSB BIT(5) 1045 #define SPM2DPSW_CTRL_VLOGIC_ACK_SOC_LSB BIT(6) 1046 #define SPM2DPSW_CTRL_VLOGIC_ACK_PCIE_0_LSB BIT(7) 1047 #define SPM2DPSW_CTRL_VLOGIC_ACK_PCIE_1_LSB BIT(8) 1048 #define SPM2DPSW_CTRL_VLOOGIC_ACK_USB_LSB BIT(9) 1049 #define SPM2DPSW_CTRL_VLOGIC_ACK_CPU_CORE_LSB BIT(10) 1050 #define SPM2DPSW_CTRL_VLOGIC_ACK_MD_LSB BIT(11) 1051 #define CSOPLU_EN_LSB BIT(0) 1052 #define CSOPLU_RST_LSB BIT(1) 1053 #define CSOPLU_CG_EN_LSB BIT(2) 1054 #define CSOPLU_CLK_SEL_LSB BIT(3) 1055 #define AP_MDSMSRC_REQ_LSB BIT(0) 1056 #define AP_L1SMSRC_REQ_LSB BIT(1) 1057 #define AP2MD_PEER_WAKEUP_LSB BIT(3) 1058 #define AP_MDSMSRC_ACK_LSB BIT(4) 1059 #define AP_L1SMSRC_ACK_LSB BIT(5) 1060 #define SPM2MD_SWITCH_CTRL_LSB BIT(0) 1061 #define SPM_AP_26M_RDY_LSB BIT(0) 1062 #define SPM2RC_DMY_CTRL_LSB BIT(2) 1063 #define RC2SPM_SRCCLKENO_0_ACK_LSB BIT(16) 1064 #define SPM2GPUEB_SW_RST_B_LSB BIT(0) 1065 #define SPM2GPUEB_SW_INT_LSB BIT(1) 1066 #define SC_MFG_PLL_EN_LSB BIT(4) 1067 #define GPUEB_WFI_LSB BIT(16) 1068 #define RPC_SRAM_CTRL_MUX_SEL_LSB BIT(0) 1069 #define APU_VCORE_OFF_ISO_EN_LSB BIT(1) 1070 #define APU_ARE_REQ_LSB BIT(4) 1071 #define APU_ARE_ACK_LSB BIT(8) 1072 #define APU_ACTIVE_STATE_LSB BIT(9) 1073 #define APU_AOV_WAKEUP_LSB BIT(16) 1074 #define AOC_EFUSE_EN_LSB BIT(0) 1075 #define AOC_EFUSE_RESTORE_RDY_LSB BIT(1) 1076 #define DFD_SOC_MTCMOS_ACK_LSB BIT(0) 1077 #define DFD_SOC_MTCMOS_REQ_LSB BIT(1) 1078 #define SC_UNIVPLL_EN_LSB BIT(0) 1079 #define SC_MMPLL_EN_LSB BIT(1) 1080 #define SC_RSV_PLL_EN_LSB BIT(2) 1081 #define APU_26M_CLK_EN_LSB BIT(16) 1082 #define IFR_26M_CLK_EN_LSB BIT(17) 1083 #define VLP_26M2CSOPLU_EN_LSB BIT(18) 1084 #define SC_RSV_CLK_EN_LSB BIT(20) 1085 #define EMI_SLB_MODE_MASK_LSB BIT(0) 1086 #define SPM2EMI_SLP_PROT_EN_LSB BIT(1) 1087 #define SPM2EMI_SLP_PROT_SRC_LSB BIT(2) 1088 #define EMI_DRAMC_MD32_SLEEP_IDLE_LSB BIT(4) 1089 #define EMI_SLB_ONLY_MODE_LSB BIT(8) 1090 #define SPM2SLC_SLP_LSB BIT(10) 1091 #define SPM2SLC_SLP_DLY_LSB BIT(12) 1092 #define SPM_SUSPEND_RESUME_FLAG_LSB BIT(0) 1093 #define SPM2PMSR_DRAMC_S0_FLAG_LSB BIT(0) 1094 #define SPM2PMSR_SYSTEM_POWER_STATE_LSB BIT(4) 1095 #define SPM_CKSYS_RTFF_DIVIDER_RST_LSB BIT(0) 1096 #define SPM_32K_VCORE_CLK_EN_LSB BIT(1) 1097 #define SPM_CSOPLU_VCORE_CLK_EN_LSB BIT(2) 1098 #define SPM2EMI_SHF_REQ_LSB BIT(0) 1099 #define SPM2EMI_SHF_REQ_ACK_LSB BIT(4) 1100 #define SPM_CIRQ_BYPASS_MODE_EN_LSB BIT(0) 1101 #define AOC_VCORE_SRAM_PDN_EN_LSB BIT(0) 1102 #define AOC_VCORE_SRAM_PDN_SHIFT_LSB BIT(1) 1103 #define SPM2EMI_PDN_REQ_LSB BIT(0) 1104 #define SPM2EMI_PDN_RDY_LSB BIT(4) 1105 #define VLP_RTFF_CTRL_MASK_LSB BIT(0) 1106 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_0_LSB BIT(0) 1107 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_1_LSB BIT(0) 1108 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_2_LSB BIT(0) 1109 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_3_LSB BIT(0) 1110 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_0_LSB BIT(0) 1111 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_1_LS BIT(0) 1112 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_2_LSB BIT(0) 1113 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_3_LSB BIT(0) 1114 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_0_LSB BIT(0) 1115 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_1_LSB BIT(0) 1116 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_2_LSB BIT(0) 1117 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_3_LSB BIT(0) 1118 #define REG_MODULE_SW_CG_F26M_REQ_MASK_0_LSB BIT(0) 1119 #define REG_MODULE_SW_CG_F26M_REQ_MASK_1_LSB BIT(0) 1120 #define REG_MODULE_SW_CG_F26M_REQ_MASK_2_LSB BIT(0) 1121 #define REG_MODULE_SW_CG_F26M_REQ_MASK_3_LSB BIT(0) 1122 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_0_LSB BIT(0) 1123 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_1_LSB BIT(0) 1124 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_2_LSB BIT(0) 1125 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_3_LSB BIT(0) 1126 #define REG_PWR_STATUS_DDREN_REQ_MASK_LSB BIT(0) 1127 #define REG_PWR_STATUS_VRF18_REQ_MASK_LSB BIT(0) 1128 #define REG_PWR_STATUS_INFRA_REQ_MASK_LSB BIT(0) 1129 #define REG_PWR_STATUS_F26M_REQ_MASK_LSB BIT(0) 1130 #define REG_PWR_STATUS_PMIC_REQ_MASK_LSB BIT(0) 1131 #define REG_PWR_STATUS_VCORE_REQ_MASK_LSB BIT(0) 1132 #define REG_PWR_STATUS_MSB_DDREN_REQ_MASK_LSB BIT(0) 1133 #define REG_PWR_STATUS_MSB_VRF18_REQ_MASK_LSB BIT(0) 1134 #define REG_PWR_STATUS_MSB_INFRA_REQ_MASK_LSB BIT(0) 1135 #define REG_PWR_STATUS_MSB_F26M_REQ_MASK_LSB BIT(0) 1136 #define REG_PWR_STATUS_MSB_PMIC_REQ_MASK_LSB BIT(0) 1137 #define REG_PWR_STATUS_MSB_VCORE_REQ_MASK_LSB BIT(0) 1138 #define REG_MODULE_BUSY_DDREN_REQ_MASK_LSB BIT(0) 1139 #define REG_MODULE_BUSY_VRF18_REQ_MASK_LSB BIT(0) 1140 #define REG_MODULE_BUSY_INFRA_REQ_MASK_LSB BIT(0) 1141 #define REG_MODULE_BUSY_F26M_REQ_MASK_LSB BIT(0) 1142 #define REG_MODULE_BUSY_PMIC_REQ_MASK_LSB BIT(0) 1143 #define REG_MODULE_BUSY_VCORE_REQ_MASK_LSB BIT(0) 1144 #define SYS_TIMER_START_EN_LSB BIT(0) 1145 #define SYS_TIMER_LATCH_EN_LSB BIT(1) 1146 #define SYS_TIMER_ID_LSB BIT(8) 1147 #define SYS_TIMER_VALID_LSB BIT(31) 1148 #define SYS_TIMER_VALUE_L_LSB BIT(0) 1149 #define SYS_TIMER_VALUE_H_LSB BIT(0) 1150 #define SYS_TIMER_START_L_LSB BIT(0) 1151 #define SYS_TIMER_START_H_LSB BIT(0) 1152 #define SYS_TIMER_LATCH_L_00_LSB BIT(0) 1153 #define SYS_TIMER_LATCH_H_00_LSB BIT(0) 1154 #define SYS_TIMER_LATCH_L_01_LSB BIT(0) 1155 #define SYS_TIMER_LATCH_H_01_LSB BIT(0) 1156 #define SYS_TIMER_LATCH_L_02_LSB BIT(0) 1157 #define SYS_TIMER_LATCH_H_02_LSB BIT(0) 1158 #define SYS_TIMER_LATCH_L_03_LSB BIT(0) 1159 #define SYS_TIMER_LATCH_H_03_LSB BIT(0) 1160 #define SYS_TIMER_LATCH_L_04_LSB BIT(0) 1161 #define SYS_TIMER_LATCH_H_04_LSB BIT(0) 1162 #define SYS_TIMER_LATCH_L_05_LSB BIT(0) 1163 #define SYS_TIMER_LATCH_H_05_LSB BIT(0) 1164 #define SYS_TIMER_LATCH_L_06_LSB BIT(0) 1165 #define SYS_TIMER_LATCH_H_06_LSB BIT(0) 1166 #define SYS_TIMER_LATCH_L_07_LSB BIT(0) 1167 #define SYS_TIMER_LATCH_H_07_LSB BIT(0) 1168 #define SYS_TIMER_LATCH_L_08_LSB BIT(0) 1169 #define SYS_TIMER_LATCH_H_08_LSB BIT(0) 1170 #define SYS_TIMER_LATCH_L_09_LSB BIT(0) 1171 #define SYS_TIMER_LATCH_H_09_LSB BIT(0) 1172 #define SYS_TIMER_LATCH_L_10_LSB BIT(0) 1173 #define SYS_TIMER_LATCH_H_10_LSB BIT(0) 1174 #define SYS_TIMER_LATCH_L_11_LSB BIT(0) 1175 #define SYS_TIMER_LATCH_H_11_LSB BIT(0) 1176 #define SYS_TIMER_LATCH_L_12_LSB BIT(0) 1177 #define SYS_TIMER_LATCH_H_12_LSB BIT(0) 1178 #define SYS_TIMER_LATCH_L_13_LSB BIT(0) 1179 #define SYS_TIMER_LATCH_H_13_LSB BIT(0) 1180 #define SYS_TIMER_LATCH_L_14_LSB BIT(0) 1181 #define SYS_TIMER_LATCH_H_14_LSB BIT(0) 1182 #define SYS_TIMER_LATCH_L_15_LSB BIT(0) 1183 #define SYS_TIMER_LATCH_H_15_LSB BIT(0) 1184 #define REG_PCM_TIMER_VAL_LSB BIT(0) 1185 #define PCM_TIMER_LSB BIT(0) 1186 #define SPM_COUNTER_VAL_0_LSB BIT(0) 1187 #define SPM_COUNTER_OUT_0_LSB BIT(14) 1188 #define SPM_COUNTER_EN_0_LSB BIT(28) 1189 #define SPM_COUNTER_CLR_0_LSB BIT(29) 1190 #define SPM_COUNTER_TIMEOUT_0_LSB BIT(30) 1191 #define SPM_COUNTER_WAKEUP_EN_0_LSB BIT(31) 1192 #define SPM_COUNTER_VAL_1_LSB BIT(0) 1193 #define SPM_COUNTER_OUT_1_LSB BIT(14) 1194 #define SPM_COUNTER_EN_1_LSB BIT(28) 1195 #define SPM_COUNTER_CLR_1_LSB BIT(29) 1196 #define SPM_COUNTER_TIMEOUT_1_LSB BIT(30) 1197 #define SPM_COUNTER_WAKEUP_EN_1_LSB BIT(31) 1198 #define SPM_COUNTER_VAL_2_LSB BIT(0) 1199 #define SPM_COUNTER_OUT_2_LSB BIT(14) 1200 #define SPM_COUNTER_EN_2_LSB BIT(28) 1201 #define SPM_COUNTER_CLR_2_LSB BIT(29) 1202 #define SPM_COUNTER_TIMEOUT_2_LSB BIT(30) 1203 #define SPM_COUNTER_WAKEUP_EN_2_LSB BIT(31) 1204 #define REG_PCM_WDT_VAL_LSB BIT(0) 1205 #define PCM_WDT_TIMER_VAL_OUT_LSB BIT(0) 1206 #define SPM_SW_FLAG_LSB BIT(0) 1207 #define SPM_SW_DEBUG_0_LSB BIT(0) 1208 #define SPM_SW_FLAG_1_LSB BIT(0) 1209 #define SPM_SW_DEBUG_1_LSB BIT(0) 1210 #define SPM_SW_RSV_0_LSB BIT(0) 1211 #define SPM_SW_RSV_1_LSB BIT(0) 1212 #define SPM_SW_RSV_2_LSB BIT(0) 1213 #define SPM_SW_RSV_3_LSB BIT(0) 1214 #define SPM_SW_RSV_4_LSB BIT(0) 1215 #define SPM_SW_RSV_5_LSB BIT(0) 1216 #define SPM_SW_RSV_6_LSB BIT(0) 1217 #define SPM_SW_RSV_7_LSB BIT(0) 1218 #define SPM_SW_RSV_8_LSB BIT(0) 1219 #define SPM_BK_WAKE_EVENT_LSB BIT(0) 1220 #define SPM_BK_VTCXO_DUR_LSB BIT(0) 1221 #define SPM_BK_WAKE_MISC_LSB BIT(0) 1222 #define SPM_BK_PCM_TIMER_LSB BIT(0) 1223 #define SPM_RSV_CON_0_LSB BIT(0) 1224 #define SPM_RSV_CON_1_LSB BIT(0) 1225 #define SPM_RSV_STA_0_LSB BIT(0) 1226 #define SPM_RSV_STA_1_LSB BIT(0) 1227 #define SPM_SPARE_CON_LSB BIT(0) 1228 #define SPM_SPARE_CON_SET_LSB BIT(0) 1229 #define SPM_SPARE_CON_CLR_LSB BIT(0) 1230 #define SPM_M0_CROSS_WAKE_REQ_LSB BIT(0) 1231 #define SPM_CROSS_WAKE_M0_CHK_LSB BIT(4) 1232 #define SPM_M1_CROSS_WAKE_REQ_LSB BIT(0) 1233 #define SPM_CROSS_WAKE_M1_CHK_LSB BIT(4) 1234 #define SPM_M2_CROSS_WAKE_REQ_LSB BIT(0) 1235 #define SPM_CROSS_WAKE_M2_CHK_LSB BIT(4) 1236 #define SPM_M3_CROSS_WAKE_REQ_LSB BIT(0) 1237 #define SPM_CROSS_WAKE_M3_CHK_LSB BIT(4) 1238 #define SCP_VCORE_LEVEL_LSB BIT(0) 1239 #define SPM_DDREN_ACK_SEL_OTHERS_LSB BIT(0) 1240 #define SPM_DDREN_ACK_SEL_MCU_LSB BIT(1) 1241 #define SPM_DDREN_ACK_SEL_WLA_MEMSYS_LSB BIT(2) 1242 #define SPM_SW_FLAG_2_LSB BIT(0) 1243 #define SPM_SW_DEBUG_2_LSB BIT(0) 1244 #define SPM_DV_CON_0_LSB BIT(0) 1245 #define SPM_DV_CON_1_LSB BIT(0) 1246 #define SPM_SEMA_M0_LSB BIT(0) 1247 #define SPM_SEMA_M1_LSB BIT(0) 1248 #define SPM_SEMA_M2_LSB BIT(0) 1249 #define SPM_SEMA_M3_LSB BIT(0) 1250 #define SPM_SEMA_M4_LSB BIT(0) 1251 #define SPM_SEMA_M5_LSB BIT(0) 1252 #define SPM_SEMA_M6_LSB BIT(0) 1253 #define SPM_SEMA_M7_LSB BIT(0) 1254 #define SPM2ADSP_MAILBOX_LSB BIT(0) 1255 #define ADSP2SPM_MAILBOX_LSB BIT(0) 1256 #define SPM2PMCU_MAILBOX_0_LSB BIT(0) 1257 #define SPM2PMCU_MAILBOX_1_LSB BIT(0) 1258 #define SPM2PMCU_MAILBOX_2_LSB BIT(0) 1259 #define SPM2PMCU_MAILBOX_3_LSB BIT(0) 1260 #define PMCU2SPM_MAILBOX_0_LSB BIT(0) 1261 #define PMCU2SPM_MAILBOX_1_LSB BIT(0) 1262 #define PMCU2SPM_MAILBOX_2_LSB BIT(0) 1263 #define PMCU2SPM_MAILBOX_3_LSB BIT(0) 1264 #define SPM_SCP_MAILBOX_LSB BIT(0) 1265 #define SCP_SPM_MAILBOX_LSB BIT(0) 1266 #define SCP_AOV_BUS_REQ_LSB BIT(0) 1267 #define SCP_AOV_BUS_ACK_LSB BIT(8) 1268 #define VCORE_RTFF_CTRL_MASK_LSB BIT(0) 1269 #define SPM_SRAM_SRCLKENO_MASK_LSB BIT(0) 1270 #define SPM_WAKEUP_EVENT_L_LSB BIT(0) 1271 #define EXT_WAKEUP_EVENT_LSB BIT(0) 1272 #define REG_WAKEUP_EVENT_MASK_LSB BIT(0) 1273 #define REG_EXT_WAKEUP_EVENT_MASK_LSB BIT(0) 1274 #define REG_WAKEUP_EVENT_SENS_LSB BIT(0) 1275 #define REG_WAKEUP_EVENT_CLR_LSB BIT(0) 1276 #define REG_SPM_ADSP_MAILBOX_REQ_LSB BIT(0) 1277 #define REG_SPM_APSRC_REQ_LSB BIT(1) 1278 #define REG_SPM_DDREN_REQ_LSB BIT(2) 1279 #define REG_SPM_DVFS_REQ_LSB BIT(3) 1280 #define REG_SPM_EMI_REQ_LSB BIT(4) 1281 #define REG_SPM_F26M_REQ_LSB BIT(5) 1282 #define REG_SPM_INFRA_REQ_LSB BIT(6) 1283 #define REG_SPM_PMIC_REQ_LSB BIT(7) 1284 #define REG_SPM_SCP_MAILBOX_REQ_LSB BIT(8) 1285 #define REG_SPM_SSPM_MAILBOX_REQ_LSB BIT(9) 1286 #define REG_SPM_SW_MAILBOX_REQ_LSB BIT(10) 1287 #define REG_SPM_VCORE_REQ_LSB BIT(11) 1288 #define REG_SPM_VRF18_REQ_LSB BIT(12) 1289 #define ADSP_MAILBOX_STATE_LSB BIT(16) 1290 #define APSRC_STATE_LSB BIT(17) 1291 #define DDREN_STATE_LSB BIT(18) 1292 #define DVFS_STATE_LSB BIT(19) 1293 #define EMI_STATE_LSB BIT(20) 1294 #define F26M_STATE_LSB BIT(21) 1295 #define INFRA_STATE_LSB BIT(22) 1296 #define PMIC_STATE_LSB BIT(23) 1297 #define SCP_MAILBOX_STATE_LSB BIT(24) 1298 #define SSPM_MAILBOX_STATE_LSB BIT(25) 1299 #define SW_MAILBOX_STATE_LSB BIT(26) 1300 #define VCORE_STATE_LSB BIT(27) 1301 #define VRF18_STATE_LSB BIT(28) 1302 #define REG_APIFR_APSRC_RMB_LSB BIT(0) 1303 #define REG_APIFR_DDREN_RMB_LSB BIT(1) 1304 #define REG_APIFR_EMI_RMB_LSB BIT(2) 1305 #define REG_APIFR_INFRA_RMB_LSB BIT(3) 1306 #define REG_APIFR_PMIC_RMB_LSB BIT(4) 1307 #define REG_APIFR_SRCCLKENA_MB_LSB BIT(5) 1308 #define REG_APIFR_VCORE_RMB_LSB BIT(6) 1309 #define REG_APIFR_VRF18_RMB_LSB BIT(7) 1310 #define REG_APU_APSRC_RMB_LSB BIT(8) 1311 #define REG_APU_DDREN_RMB_LSB BIT(9) 1312 #define REG_APU_EMI_RMB_LSB BIT(10) 1313 #define REG_APU_INFRA_RMB_LSB BIT(11) 1314 #define REG_APU_PMIC_RMB_LSB BIT(12) 1315 #define REG_APU_SRCCLKENA_MB_LSB BIT(13) 1316 #define REG_APU_VCORE_RMB_LSB BIT(14) 1317 #define REG_APU_VRF18_RMB_LSB BIT(15) 1318 #define REG_AUDIO_APSRC_RMB_LSB BIT(16) 1319 #define REG_AUDIO_DDREN_RMB_LSB BIT(17) 1320 #define REG_AUDIO_EMI_RMB_LSB BIT(18) 1321 #define REG_AUDIO_INFRA_RMB_LSB BIT(19) 1322 #define REG_AUDIO_PMIC_RMB_LSB BIT(20) 1323 #define REG_AUDIO_SRCCLKENA_MB_LSB BIT(21) 1324 #define REG_AUDIO_VCORE_RMB_LSB BIT(22) 1325 #define REG_AUDIO_VRF18_RMB_LSB BIT(23) 1326 #define REG_AUDIO_DSP_APSRC_RMB_LSB BIT(0) 1327 #define REG_AUDIO_DSP_DDREN_RMB_LSB BIT(1) 1328 #define REG_AUDIO_DSP_EMI_RMB_LSB BIT(2) 1329 #define REG_AUDIO_DSP_INFRA_RMB_LSB BIT(3) 1330 #define REG_AUDIO_DSP_PMIC_RMB_LSB BIT(4) 1331 #define REG_AUDIO_DSP_SRCCLKENA_MB_LSB BIT(5) 1332 #define REG_AUDIO_DSP_VCORE_RMB_LSB BIT(6) 1333 #define REG_AUDIO_DSP_VRF18_RMB_LSB BIT(7) 1334 #define REG_CAM_APSRC_RMB_LSB BIT(8) 1335 #define REG_CAM_DDREN_RMB_LSB BIT(9) 1336 #define REG_CAM_EMI_RMB_LSB BIT(10) 1337 #define REG_CAM_INFRA_RMB_LSB BIT(11) 1338 #define REG_CAM_PMIC_RMB_LSB BIT(12) 1339 #define REG_CAM_SRCCLKENA_MB_LSB BIT(13) 1340 #define REG_CAM_VRF18_RMB_LSB BIT(14) 1341 #define REG_CCIF_APSRC_RMB_LSB BIT(15) 1342 #define REG_CCIF_EMI_RMB_LSB BIT(0) 1343 #define REG_CCIF_INFRA_RMB_LSB BIT(12) 1344 #define REG_CCIF_PMIC_RMB_LSB BIT(0) 1345 #define REG_CCIF_SRCCLKENA_MB_LSB BIT(12) 1346 #define REG_CCIF_VCORE_RMB_LSB BIT(0) 1347 #define REG_CCIF_VRF18_RMB_LSB BIT(12) 1348 #define REG_CCU_APSRC_RMB_LSB BIT(24) 1349 #define REG_CCU_DDREN_RMB_LSB BIT(25) 1350 #define REG_CCU_EMI_RMB_LSB BIT(26) 1351 #define REG_CCU_INFRA_RMB_LSB BIT(27) 1352 #define REG_CCU_PMIC_RMB_LSB BIT(28) 1353 #define REG_CCU_SRCCLKENA_MB_LSB BIT(29) 1354 #define REG_CCU_VRF18_RMB_LSB BIT(30) 1355 #define REG_CG_CHECK_APSRC_RMB_LSB BIT(31) 1356 #define REG_CG_CHECK_DDREN_RMB_LSB BIT(0) 1357 #define REG_CG_CHECK_EMI_RMB_LSB BIT(1) 1358 #define REG_CG_CHECK_INFRA_RMB_LSB BIT(2) 1359 #define REG_CG_CHECK_PMIC_RMB_LSB BIT(3) 1360 #define REG_CG_CHECK_SRCCLKENA_MB_LS BIT(4) 1361 #define REG_CG_CHECK_VCORE_RMB_LSB BIT(5) 1362 #define REG_CG_CHECK_VRF18_RMB_LSB BIT(6) 1363 #define REG_CKSYS_APSRC_RMB_LSB BIT(7) 1364 #define REG_CKSYS_DDREN_RMB_LSB BIT(8) 1365 #define REG_CKSYS_EMI_RMB_LSB BIT(9) 1366 #define REG_CKSYS_INFRA_RMB_LSB BIT(10) 1367 #define REG_CKSYS_PMIC_RMB_LSB BIT(11) 1368 #define REG_CKSYS_SRCCLKENA_MB_LSB BIT(12) 1369 #define REG_CKSYS_VCORE_RMB_LSB BIT(13) 1370 #define REG_CKSYS_VRF18_RMB_LSB BIT(14) 1371 #define REG_CKSYS_1_APSRC_RMB_LSB BIT(15) 1372 #define REG_CKSYS_1_DDREN_RMB_LSB BIT(16) 1373 #define REG_CKSYS_1_EMI_RMB_LSB BIT(17) 1374 #define REG_CKSYS_1_INFRA_RMB_LSB BIT(18) 1375 #define REG_CKSYS_1_PMIC_RMB_LSB BIT(19) 1376 #define REG_CKSYS_1_SRCCLKENA_MB_LSB BIT(20) 1377 #define REG_CKSYS_1_VCORE_RMB_LSB BIT(21) 1378 #define REG_CKSYS_1_VRF18_RMB_LSB BIT(22) 1379 #define REG_CKSYS_2_APSRC_RMB_LSB BIT(0) 1380 #define REG_CKSYS_2_DDREN_RMB_LSB BIT(1) 1381 #define REG_CKSYS_2_EMI_RMB_LSB BIT(2) 1382 #define REG_CKSYS_2_INFRA_RMB_LSB BIT(3) 1383 #define REG_CKSYS_2_PMIC_RMB_LSB BIT(4) 1384 #define REG_CKSYS_2_SRCCLKENA_MB_LSB BIT(5) 1385 #define REG_CKSYS_2_VCORE_RMB_LSB BIT(6) 1386 #define REG_CKSYS_2_VRF18_RMB_LSB BIT(7) 1387 #define REG_CONN_APSRC_RMB_LSB BIT(8) 1388 #define REG_CONN_DDREN_RMB_LSB BIT(9) 1389 #define REG_CONN_EMI_RMB_LSB BIT(10) 1390 #define REG_CONN_INFRA_RMB_LSB BIT(11) 1391 #define REG_CONN_PMIC_RMB_LSB BIT(12) 1392 #define REG_CONN_SRCCLKENA_MB_LSB BIT(13) 1393 #define REG_CONN_SRCCLKENB_MB_LSB BIT(14) 1394 #define REG_CONN_VCORE_RMB_LSB BIT(15) 1395 #define REG_CONN_VRF18_RMB_LSB BIT(16) 1396 #define REG_CORECFG_APSRC_RMB_LSB BIT(17) 1397 #define REG_CORECFG_DDREN_RMB_LSB BIT(18) 1398 #define REG_CORECFG_EMI_RMB_LSB BIT(19) 1399 #define REG_CORECFG_INFRA_RMB_LSB BIT(20) 1400 #define REG_CORECFG_PMIC_RMB_LSB BIT(21) 1401 #define REG_CORECFG_SRCCLKENA_MB_LSB BIT(22) 1402 #define REG_CORECFG_VCORE_RMB_LSB BIT(23) 1403 #define REG_CORECFG_VRF18_RMB_LSB BIT(24) 1404 #define REG_CPUEB_APSRC_RMB_LSB BIT(0) 1405 #define REG_CPUEB_DDREN_RMB_LSB BIT(1) 1406 #define REG_CPUEB_EMI_RMB_LSB BIT(2) 1407 #define REG_CPUEB_INFRA_RMB_LSB BIT(3) 1408 #define REG_CPUEB_PMIC_RMB_LSB BIT(4) 1409 #define REG_CPUEB_SRCCLKENA_MB_LSB BIT(5) 1410 #define REG_CPUEB_VCORE_RMB_LSB BIT(6) 1411 #define REG_CPUEB_VRF18_RMB_LSB BIT(7) 1412 #define REG_DISP0_APSRC_RMB_LSB BIT(8) 1413 #define REG_DISP0_DDREN_RMB_LSB BIT(9) 1414 #define REG_DISP0_EMI_RMB_LSB BIT(10) 1415 #define REG_DISP0_INFRA_RMB_LSB BIT(11) 1416 #define REG_DISP0_PMIC_RMB_LSB BIT(12) 1417 #define REG_DISP0_SRCCLKENA_MB_LSB BIT(13) 1418 #define REG_DISP0_VRF18_RMB_LSB BIT(14) 1419 #define REG_DISP1_APSRC_RMB_LSB BIT(15) 1420 #define REG_DISP1_DDREN_RMB_LSB BIT(16) 1421 #define REG_DISP1_EMI_RMB_LSB BIT(17) 1422 #define REG_DISP1_INFRA_RMB_LSB BIT(18) 1423 #define REG_DISP1_PMIC_RMB_LSB BIT(19) 1424 #define REG_DISP1_SRCCLKENA_MB_LSB BIT(20) 1425 #define REG_DISP1_VRF18_RMB_LSB BIT(21) 1426 #define REG_DPM_APSRC_RMB_LSB BIT(22) 1427 #define REG_DPM_DDREN_RMB_LSB BIT(26) 1428 #define REG_DPM_EMI_RMB_LSB BIT(0) 1429 #define REG_DPM_INFRA_RMB_LSB BIT(4) 1430 #define REG_DPM_PMIC_RMB_LSB BIT(8) 1431 #define REG_DPM_SRCCLKENA_MB_LSB BIT(12) 1432 #define REG_DPM_VCORE_RMB_LSB BIT(16) 1433 #define REG_DPM_VRF18_RMB_LSB BIT(20) 1434 #define REG_DPMAIF_APSRC_RMB_LSB BIT(24) 1435 #define REG_DPMAIF_DDREN_RMB_LSB BIT(25) 1436 #define REG_DPMAIF_EMI_RMB_LSB BIT(26) 1437 #define REG_DPMAIF_INFRA_RMB_LSB BIT(27) 1438 #define REG_DPMAIF_PMIC_RMB_LSB BIT(28) 1439 #define REG_DPMAIF_SRCCLKENA_MB_LSB BIT(29) 1440 #define REG_DPMAIF_VCORE_RMB_LSB BIT(30) 1441 #define REG_DPMAIF_VRF18_RMB_LSB BIT(31) 1442 #define REG_DVFSRC_LEVEL_RMB_LSB BIT(0) 1443 #define REG_EMISYS_APSRC_RMB_LSB BIT(1) 1444 #define REG_EMISYS_DDREN_RMB_LSB BIT(2) 1445 #define REG_EMISYS_EMI_RMB_LSB BIT(3) 1446 #define REG_EMISYS_INFRA_RMB_LSB BIT(4) 1447 #define REG_EMISYS_PMIC_RMB_LSB BIT(5) 1448 #define REG_EMISYS_SRCCLKENA_MB_LSB BIT(6) 1449 #define REG_EMISYS_VCORE_RMB_LSB BIT(7) 1450 #define REG_EMISYS_VRF18_RMB_LSB BIT(8) 1451 #define REG_GCE_APSRC_RMB_LSB BIT(9) 1452 #define REG_GCE_DDREN_RMB_LSB BIT(10) 1453 #define REG_GCE_EMI_RMB_LSB BIT(11) 1454 #define REG_GCE_INFRA_RMB_LSB BIT(12) 1455 #define REG_GCE_PMIC_RMB_LSB BIT(13) 1456 #define REG_GCE_SRCCLKENA_MB_LSB BIT(14) 1457 #define REG_GCE_VCORE_RMB_LSB BIT(15) 1458 #define REG_GCE_VRF18_RMB_LSB BIT(16) 1459 #define REG_GPUEB_APSRC_RMB_LSB BIT(17) 1460 #define REG_GPUEB_DDREN_RMB_LSB BIT(18) 1461 #define REG_GPUEB_EMI_RMB_LSB BIT(19) 1462 #define REG_GPUEB_INFRA_RMB_LSB BIT(20) 1463 #define REG_GPUEB_PMIC_RMB_LSB BIT(21) 1464 #define REG_GPUEB_SRCCLKENA_MB_LSB BIT(22) 1465 #define REG_GPUEB_VCORE_RMB_LSB BIT(23) 1466 #define REG_GPUEB_VRF18_RMB_LSB BIT(24) 1467 #define REG_HWCCF_APSRC_RMB_LSB BIT(25) 1468 #define REG_HWCCF_DDREN_RMB_LSB BIT(26) 1469 #define REG_HWCCF_EMI_RMB_LSB BIT(27) 1470 #define REG_HWCCF_INFRA_RMB_LSB BIT(28) 1471 #define REG_HWCCF_PMIC_RMB_LSB BIT(29) 1472 #define REG_HWCCF_SRCCLKENA_MB_LSB BIT(30) 1473 #define REG_HWCCF_VCORE_RMB_LSB BIT(31) 1474 #define REG_HWCCF_VRF18_RMB_LSB BIT(0) 1475 #define REG_IMG_APSRC_RMB_LSB BIT(1) 1476 #define REG_IMG_DDREN_RMB_LSB BIT(2) 1477 #define REG_IMG_EMI_RMB_LSB BIT(3) 1478 #define REG_IMG_INFRA_RMB_LSB BIT(4) 1479 #define REG_IMG_PMIC_RMB_LSB BIT(5) 1480 #define REG_IMG_SRCCLKENA_MB_LSB BIT(6) 1481 #define REG_IMG_VRF18_RMB_LSB BIT(7) 1482 #define REG_INFRASYS_APSRC_RMB_LSB BIT(8) 1483 #define REG_INFRASYS_DDREN_RMB_LSB BIT(9) 1484 #define REG_INFRASYS_EMI_RMB_LSB BIT(10) 1485 #define REG_INFRASYS_INFRA_RMB_LSB BIT(11) 1486 #define REG_INFRASYS_PMIC_RMB_LSB BIT(12) 1487 #define REG_INFRASYS_SRCCLKENA_MB_LSB BIT(13) 1488 #define REG_INFRASYS_VCORE_RMB_LSB BIT(14) 1489 #define REG_INFRASYS_VRF18_RMB_LSB BIT(15) 1490 #define REG_IPIC_INFRA_RMB_LSB BIT(16) 1491 #define REG_IPIC_VRF18_RMB_LSB BIT(17) 1492 #define REG_MCU_APSRC_RMB_LSB BIT(18) 1493 #define REG_MCU_DDREN_RMB_LSB BIT(19) 1494 #define REG_MCU_EMI_RMB_LSB BIT(20) 1495 #define REG_MCU_INFRA_RMB_LSB BIT(21) 1496 #define REG_MCU_PMIC_RMB_LSB BIT(22) 1497 #define REG_MCU_SRCCLKENA_MB_LSB BIT(23) 1498 #define REG_MCU_VCORE_RMB_LSB BIT(24) 1499 #define REG_MCU_VRF18_RMB_LSB BIT(25) 1500 #define REG_MD_APSRC_RMB_LSB BIT(26) 1501 #define REG_MD_DDREN_RMB_LSB BIT(27) 1502 #define REG_MD_EMI_RMB_LSB BIT(28) 1503 #define REG_MD_INFRA_RMB_LSB BIT(29) 1504 #define REG_MD_PMIC_RMB_LSB BIT(30) 1505 #define REG_MD_SRCCLKENA_MB_LSB BIT(31) 1506 #define REG_MD_SRCCLKENA1_MB_LSB BIT(0) 1507 #define REG_MD_VCORE_RMB_LSB BIT(1) 1508 #define REG_MD_VRF18_RMB_LSB BIT(2) 1509 #define REG_MM_PROC_APSRC_RMB_LSB BIT(3) 1510 #define REG_MM_PROC_DDREN_RMB_LSB BIT(4) 1511 #define REG_MM_PROC_EMI_RMB_LSB BIT(5) 1512 #define REG_MM_PROC_INFRA_RMB_LSB BIT(6) 1513 #define REG_MM_PROC_PMIC_RMB_LSB BIT(7) 1514 #define REG_MM_PROC_SRCCLKENA_MB_LSB BIT(8) 1515 #define REG_MM_PROC_VCORE_RMB_LSB BIT(9) 1516 #define REG_MM_PROC_VRF18_RMB_LSB BIT(10) 1517 #define REG_MML0_APSRC_RMB_LSB BIT(11) 1518 #define REG_MML0_DDREN_RMB_LSB BIT(12) 1519 #define REG_MML0_EMI_RMB_LSB BIT(13) 1520 #define REG_MML0_INFRA_RMB_LSB BIT(14) 1521 #define REG_MML0_PMIC_RMB_LSB BIT(15) 1522 #define REG_MML0_SRCCLKENA_MB_LSB BIT(16) 1523 #define REG_MML0_VRF18_RMB_LSB BIT(17) 1524 #define REG_MML1_APSRC_RMB_LSB BIT(18) 1525 #define REG_MML1_DDREN_RMB_LSB BIT(19) 1526 #define REG_MML1_EMI_RMB_LSB BIT(20) 1527 #define REG_MML1_INFRA_RMB_LSB BIT(21) 1528 #define REG_MML1_PMIC_RMB_LSB BIT(22) 1529 #define REG_MML1_SRCCLKENA_MB_LSB BIT(23) 1530 #define REG_MML1_VRF18_RMB_LSB BIT(24) 1531 #define REG_OVL0_APSRC_RMB_LSB BIT(25) 1532 #define REG_OVL0_DDREN_RMB_LSB BIT(26) 1533 #define REG_OVL0_EMI_RMB_LSB BIT(27) 1534 #define REG_OVL0_INFRA_RMB_LSB BIT(28) 1535 #define REG_OVL0_PMIC_RMB_LSB BIT(29) 1536 #define REG_OVL0_SRCCLKENA_MB_LSB BIT(30) 1537 #define REG_OVL0_VRF18_RMB_LSB BIT(31) 1538 #define REG_OVL1_APSRC_RMB_LSB BIT(0) 1539 #define REG_OVL1_DDREN_RMB_LSB BIT(1) 1540 #define REG_OVL1_EMI_RMB_LSB BIT(2) 1541 #define REG_OVL1_INFRA_RMB_LSB BIT(3) 1542 #define REG_OVL1_PMIC_RMB_LSB BIT(4) 1543 #define REG_OVL1_SRCCLKENA_MB_LSB BIT(5) 1544 #define REG_OVL1_VRF18_RMB_LSB BIT(6) 1545 #define REG_PCIE0_APSRC_RMB_LSB BIT(7) 1546 #define REG_PCIE0_DDREN_RMB_LSB BIT(8) 1547 #define REG_PCIE0_EMI_RMB_LSB BIT(9) 1548 #define REG_PCIE0_INFRA_RMB_LSB BIT(10) 1549 #define REG_PCIE0_PMIC_RMB_LSB BIT(11) 1550 #define REG_PCIE0_SRCCLKENA_MB_LSB BIT(12) 1551 #define REG_PCIE0_VCORE_RMB_LSB BIT(13) 1552 #define REG_PCIE0_VRF18_RMB_LSB BIT(14) 1553 #define REG_PCIE1_APSRC_RMB_LSB BIT(15) 1554 #define REG_PCIE1_DDREN_RMB_LSB BIT(16) 1555 #define REG_PCIE1_EMI_RMB_LSB BIT(17) 1556 #define REG_PCIE1_INFRA_RMB_LSB BIT(18) 1557 #define REG_PCIE1_PMIC_RMB_LSB BIT(19) 1558 #define REG_PCIE1_SRCCLKENA_MB_LSB BIT(20) 1559 #define REG_PCIE1_VCORE_RMB_LSB BIT(21) 1560 #define REG_PCIE1_VRF18_RMB_LSB BIT(22) 1561 #define REG_PERISYS_APSRC_RMB_LSB BIT(23) 1562 #define REG_PERISYS_DDREN_RMB_LSB BIT(24) 1563 #define REG_PERISYS_EMI_RMB_LSB BIT(25) 1564 #define REG_PERISYS_INFRA_RMB_LSB BIT(26) 1565 #define REG_PERISYS_PMIC_RMB_LSB BIT(27) 1566 #define REG_PERISYS_SRCCLKENA_MB_LSB BIT(28) 1567 #define REG_PERISYS_VCORE_RMB_LSB BIT(29) 1568 #define REG_PERISYS_VRF18_RMB_LSB BIT(30) 1569 #define REG_PMSR_APSRC_RMB_LSB BIT(31) 1570 #define REG_PMSR_DDREN_RMB_LSB BIT(0) 1571 #define REG_PMSR_EMI_RMB_LSB BIT(1) 1572 #define REG_PMSR_INFRA_RMB_LSB BIT(2) 1573 #define REG_PMSR_PMIC_RMB_LSB BIT(3) 1574 #define REG_PMSR_SRCCLKENA_MB_LSB BIT(4) 1575 #define REG_PMSR_VCORE_RMB_LSB BIT(5) 1576 #define REG_PMSR_VRF18_RMB_LSB BIT(6) 1577 #define REG_SCP_APSRC_RMB_LSB BIT(7) 1578 #define REG_SCP_DDREN_RMB_LSB BIT(8) 1579 #define REG_SCP_EMI_RMB_LSB BIT(9) 1580 #define REG_SCP_INFRA_RMB_LSB BIT(10) 1581 #define REG_SCP_PMIC_RMB_LSB BIT(11) 1582 #define REG_SCP_SRCCLKENA_MB_LSB BIT(12) 1583 #define REG_SCP_VCORE_RMB_LSB BIT(13) 1584 #define REG_SCP_VRF18_RMB_LSB BIT(14) 1585 #define REG_SPU_HWR_APSRC_RMB_LSB BIT(15) 1586 #define REG_SPU_HWR_DDREN_RMB_LSB BIT(16) 1587 #define REG_SPU_HWR_EMI_RMB_LSB BIT(17) 1588 #define REG_SPU_HWR_INFRA_RMB_LSB BIT(18) 1589 #define REG_SPU_HWR_PMIC_RMB_LSB BIT(19) 1590 #define REG_SPU_HWR_SRCCLKENA_MB_LSB BIT(20) 1591 #define REG_SPU_HWR_VCORE_RMB_LSB BIT(21) 1592 #define REG_SPU_HWR_VRF18_RMB_LSB BIT(22) 1593 #define REG_SPU_ISE_APSRC_RMB_LSB BIT(23) 1594 #define REG_SPU_ISE_DDREN_RMB_LSB BIT(24) 1595 #define REG_SPU_ISE_EMI_RMB_LSB BIT(25) 1596 #define REG_SPU_ISE_INFRA_RMB_LSB BIT(26) 1597 #define REG_SPU_ISE_PMIC_RMB_LSB BIT(27) 1598 #define REG_SPU_ISE_SRCCLKENA_MB_LSB BIT(28) 1599 #define REG_SPU_ISE_VCORE_RMB_LSB BIT(29) 1600 #define REG_SPU_ISE_VRF18_RMB_LSB BIT(30) 1601 #define REG_SRCCLKENI_INFRA_RMB_LSB BIT(0) 1602 #define REG_SRCCLKENI_PMIC_RMB_LSB BIT(2) 1603 #define REG_SRCCLKENI_SRCCLKENA_MB_LSB BIT(4) 1604 #define REG_SRCCLKENI_VCORE_RMB_LSB BIT(6) 1605 #define REG_SSPM_APSRC_RMB_LSB BIT(8) 1606 #define REG_SSPM_DDREN_RMB_LSB BIT(9) 1607 #define REG_SSPM_EMI_RMB_LSB BIT(10) 1608 #define REG_SSPM_INFRA_RMB_LSB BIT(11) 1609 #define REG_SSPM_PMIC_RMB_LSB BIT(12) 1610 #define REG_SSPM_SRCCLKENA_MB_LSB BIT(13) 1611 #define REG_SSPM_VRF18_RMB_LSB BIT(14) 1612 #define REG_SSRSYS_APSRC_RMB_LSB BIT(15) 1613 #define REG_SSRSYS_DDREN_RMB_LSB BIT(16) 1614 #define REG_SSRSYS_EMI_RMB_LSB BIT(17) 1615 #define REG_SSRSYS_INFRA_RMB_LSB BIT(18) 1616 #define REG_SSRSYS_PMIC_RMB_LSB BIT(19) 1617 #define REG_SSRSYS_SRCCLKENA_MB_LSB BIT(20) 1618 #define REG_SSRSYS_VCORE_RMB_LSB BIT(21) 1619 #define REG_SSRSYS_VRF18_RMB_LSB BIT(22) 1620 #define REG_SSUSB_APSRC_RMB_LSB BIT(23) 1621 #define REG_SSUSB_DDREN_RMB_LSB BIT(24) 1622 #define REG_SSUSB_EMI_RMB_LSB BIT(25) 1623 #define REG_SSUSB_INFRA_RMB_LSB BIT(26) 1624 #define REG_SSUSB_PMIC_RMB_LSB BIT(27) 1625 #define REG_SSUSB_SRCCLKENA_MB_LSB BIT(28) 1626 #define REG_SSUSB_VCORE_RMB_LSB BIT(29) 1627 #define REG_SSUSB_VRF18_RMB_LSB BIT(30) 1628 #define REG_UART_HUB_INFRA_RMB_LSB BIT(31) 1629 #define REG_UART_HUB_PMIC_RMB_LSB BIT(0) 1630 #define REG_UART_HUB_SRCCLKENA_MB_LSB BIT(1) 1631 #define REG_UART_HUB_VCORE_RMB_LSB BIT(2) 1632 #define REG_UART_HUB_VRF18_RMB_LSB BIT(3) 1633 #define REG_UFS_APSRC_RMB_LSB BIT(4) 1634 #define REG_UFS_DDREN_RMB_LSB BIT(5) 1635 #define REG_UFS_EMI_RMB_LSB BIT(6) 1636 #define REG_UFS_INFRA_RMB_LSB BIT(7) 1637 #define REG_UFS_PMIC_RMB_LSB BIT(8) 1638 #define REG_UFS_SRCCLKENA_MB_LSB BIT(9) 1639 #define REG_UFS_VCORE_RMB_LSB BIT(10) 1640 #define REG_UFS_VRF18_RMB_LSB BIT(11) 1641 #define REG_VDEC_APSRC_RMB_LSB BIT(12) 1642 #define REG_VDEC_DDREN_RMB_LSB BIT(13) 1643 #define REG_VDEC_EMI_RMB_LSB BIT(14) 1644 #define REG_VDEC_INFRA_RMB_LSB BIT(15) 1645 #define REG_VDEC_PMIC_RMB_LSB BIT(16) 1646 #define REG_VDEC_SRCCLKENA_MB_LSB BIT(17) 1647 #define REG_VDEC_VRF18_RMB_LSB BIT(18) 1648 #define REG_VENC_APSRC_RMB_LSB BIT(19) 1649 #define REG_VENC_DDREN_RMB_LSB BIT(20) 1650 #define REG_VENC_EMI_RMB_LSB BIT(21) 1651 #define REG_VENC_INFRA_RMB_LSB BIT(22) 1652 #define REG_VENC_PMIC_RMB_LSB BIT(23) 1653 #define REG_VENC_SRCCLKENA_MB_LSB BIT(24) 1654 #define REG_VENC_VRF18_RMB_LSB BIT(25) 1655 #define REG_VLPCFG_APSRC_RMB_LSB BIT(26) 1656 #define REG_VLPCFG_DDREN_RMB_LSB BIT(27) 1657 #define REG_VLPCFG_EMI_RMB_LSB BIT(28) 1658 #define REG_VLPCFG_INFRA_RMB_LSB BIT(29) 1659 #define REG_VLPCFG_PMIC_RMB_LSB BIT(30) 1660 #define REG_VLPCFG_SRCCLKENA_MB_LSB BIT(31) 1661 #define REG_VLPCFG_VCORE_RMB_LSB BIT(0) 1662 #define REG_VLPCFG_VRF18_RMB_LSB BIT(1) 1663 #define REG_VLPCFG1_APSRC_RMB_LSB BIT(2) 1664 #define REG_VLPCFG1_DDREN_RMB_LSB BIT(3) 1665 #define REG_VLPCFG1_EMI_RMB_LSB BIT(4) 1666 #define REG_VLPCFG1_INFRA_RMB_LSB BIT(5) 1667 #define REG_VLPCFG1_PMIC_RMB_LSB BIT(6) 1668 #define REG_VLPCFG1_SRCCLKENA_MB_LSB BIT(7) 1669 #define REG_VLPCFG1_VCORE_RMB_LSB BIT(8) 1670 #define REG_VLPCFG1_VRF18_RMB_LSB BIT(9) 1671 #define APIFR_MEM_APSRC_REQ_LSB BIT(0) 1672 #define APIFR_MEM_DDREN_REQ_LSB BIT(1) 1673 #define APIFR_MEM_EMI_REQ_LSB BIT(2) 1674 #define APIFR_MEM_INFRA_REQ_LSB BIT(3) 1675 #define APIFR_MEM_PMIC_REQ_LSB BIT(4) 1676 #define APIFR_MEM_SRCCLKENA_LSB BIT(5) 1677 #define APIFR_MEM_VCORE_REQ_LSB BIT(6) 1678 #define APIFR_MEM_VRF18_REQ_LSB BIT(7) 1679 #define APU_APSRC_REQ_LSB BIT(8) 1680 #define APU_DDREN_REQ_LSB BIT(9) 1681 #define APU_EMI_REQ_LSB BIT(10) 1682 #define APU_INFRA_REQ_LSB BIT(11) 1683 #define APU_PMIC_REQ_LSB BIT(12) 1684 #define APU_SRCCLKENA_LSB BIT(13) 1685 #define APU_VCORE_REQ_LSB BIT(14) 1686 #define APU_VRF18_REQ_LSB BIT(15) 1687 #define AUDIO_APSRC_REQ_LSB BIT(16) 1688 #define AUDIO_DDREN_REQ_LSB BIT(17) 1689 #define AUDIO_EMI_REQ_LSB BIT(18) 1690 #define AUDIO_INFRA_REQ_LSB BIT(19) 1691 #define AUDIO_PMIC_REQ_LSB BIT(20) 1692 #define AUDIO_SRCCLKENA_LSB BIT(21) 1693 #define AUDIO_VCORE_REQ_LSB BIT(22) 1694 #define AUDIO_VRF18_REQ_LSB BIT(23) 1695 #define AUDIO_DSP_APSRC_REQ_LSB BIT(0) 1696 #define AUDIO_DSP_DDREN_REQ_LSB BIT(1) 1697 #define AUDIO_DSP_EMI_REQ_LSB BIT(2) 1698 #define AUDIO_DSP_INFRA_REQ_LSB BIT(3) 1699 #define AUDIO_DSP_PMIC_REQ_LSB BIT(4) 1700 #define AUDIO_DSP_SRCCLKENA_LSB BIT(5) 1701 #define AUDIO_DSP_VCORE_REQ_LSB BIT(6) 1702 #define AUDIO_DSP_VRF18_REQ_LSB BIT(7) 1703 #define CAM_APSRC_REQ_LSB BIT(8) 1704 #define CAM_DDREN_REQ_LSB BIT(9) 1705 #define CAM_EMI_REQ_LSB BIT(10) 1706 #define CAM_INFRA_REQ_LSB BIT(11) 1707 #define CAM_PMIC_REQ_LSB BIT(12) 1708 #define CAM_SRCCLKENA_LSB BIT(13) 1709 #define CAM_VRF18_REQ_LSB BIT(14) 1710 #define CCIF_APSRC_REQ_LSB BIT(15) 1711 #define CCIF_EMI_REQ_LSB BIT(0) 1712 #define CCIF_INFRA_REQ_LSB BIT(12) 1713 #define CCIF_PMIC_REQ_LSB BIT(0) 1714 #define CCIF_SRCCLKENA_LSB BIT(12) 1715 #define CCIF_VCORE_REQ_LSB BIT(0) 1716 #define CCIF_VRF18_REQ_LSB BIT(12) 1717 #define CCU_APSRC_REQ_LSB BIT(24) 1718 #define CCU_DDREN_REQ_LSB BIT(25) 1719 #define CCU_EMI_REQ_LSB BIT(26) 1720 #define CCU_INFRA_REQ_LSB BIT(27) 1721 #define CCU_PMIC_REQ_LSB BIT(28) 1722 #define CCU_SRCCLKENA_LSB BIT(29) 1723 #define CCU_VRF18_REQ_LSB BIT(30) 1724 #define CG_CHECK_APSRC_REQ_LSB BIT(31) 1725 #define CG_CHECK_DDREN_REQ_LSB BIT(0) 1726 #define CG_CHECK_EMI_REQ_LSB BIT(1) 1727 #define CG_CHECK_INFRA_REQ_LSB BIT(2) 1728 #define CG_CHECK_PMIC_REQ_LSB BIT(3) 1729 #define CG_CHECK_SRCCLKENA_LSB BIT(4) 1730 #define CG_CHECK_VCORE_REQ_LSB BIT(5) 1731 #define CG_CHECK_VRF18_REQ_LSB BIT(6) 1732 #define CKSYS_APSRC_REQ_LSB BIT(7) 1733 #define CKSYS_DDREN_REQ_LSB BIT(8) 1734 #define CKSYS_EMI_REQ_LSB BIT(9) 1735 #define CKSYS_INFRA_REQ_LSB BIT(10) 1736 #define CKSYS_PMIC_REQ_LSB BIT(11) 1737 #define CKSYS_SRCCLKENA_LSB BIT(12) 1738 #define CKSYS_VCORE_REQ_LSB BIT(13) 1739 #define CKSYS_VRF18_REQ_LSB BIT(14) 1740 #define CKSYS_1_APSRC_REQ_LSB BIT(15) 1741 #define CKSYS_1_DDREN_REQ_LSB BIT(16) 1742 #define CKSYS_1_EMI_REQ_LSB BIT(17) 1743 #define CKSYS_1_INFRA_REQ_LSB BIT(18) 1744 #define CKSYS_1_PMIC_REQ_LSB BIT(19) 1745 #define CKSYS_1_SRCCLKENA_LSB BIT(20) 1746 #define CKSYS_1_VCORE_REQ_LSB BIT(21) 1747 #define CKSYS_1_VRF18_REQ_LSB BIT(22) 1748 #define CKSYS_2_APSRC_REQ_LSB BIT(23) 1749 #define CKSYS_2_DDREN_REQ_LSB BIT(24) 1750 #define CKSYS_2_EMI_REQ_LSB BIT(25) 1751 #define CKSYS_2_INFRA_REQ_LSB BIT(26) 1752 #define CKSYS_2_PMIC_REQ_LSB BIT(27) 1753 #define CKSYS_2_SRCCLKENA_LSB BIT(28) 1754 #define CKSYS_2_VCORE_REQ_LSB BIT(29) 1755 #define CKSYS_2_VRF18_REQ_LSB BIT(30) 1756 #define CONN_APSRC_REQ_LSB BIT(0) 1757 #define CONN_DDREN_REQ_LSB BIT(1) 1758 #define CONN_EMI_REQ_LSB BIT(2) 1759 #define CONN_INFRA_REQ_LSB BIT(3) 1760 #define CONN_PMIC_REQ_LSB BIT(4) 1761 #define CONN_SRCCLKENA_LSB BIT(5) 1762 #define CONN_SRCCLKENB_LSB BIT(6) 1763 #define CONN_VCORE_REQ_LSB BIT(7) 1764 #define CONN_VRF18_REQ_LSB BIT(8) 1765 #define CORECFG_RSV0_APSRC_REQ_LSB BIT(9) 1766 #define CORECFG_RSV0_DDREN_REQ_LSB BIT(10) 1767 #define CORECFG_RSV0_EMI_REQ_LSB BIT(11) 1768 #define CORECFG_RSV0_INFRA_REQ_LSB BIT(12) 1769 #define CORECFG_RSV0_PMIC_REQ_LSB BIT(13) 1770 #define CORECFG_RSV0_SRCCLKENA_LSB BIT(14) 1771 #define CPUEB_APSRC_REQ_LSB BIT(0) 1772 #define CPUEB_DDREN_REQ_LSB BIT(1) 1773 #define CPUEB_EMI_REQ_LSB BIT(2) 1774 #define CPUEB_INFRA_REQ_LSB BIT(3) 1775 #define CPUEB_PMIC_REQ_LSB BIT(4) 1776 #define CPUEB_SRCCLKENA_LSB BIT(5) 1777 #define CPUEB_VCORE_REQ_LSB BIT(6) 1778 #define CPUEB_VRF18_REQ_LSB BIT(7) 1779 #define DISP0_APSRC_REQ_LSB BIT(8) 1780 #define DISP0_DDREN_REQ_LSB BIT(9) 1781 #define DISP0_EMI_REQ_LSB BIT(10) 1782 #define DISP0_INFRA_REQ_LSB BIT(11) 1783 #define DISP0_PMIC_REQ_LSB BIT(12) 1784 #define DISP0_SRCCLKENA_LSB BIT(13) 1785 #define DISP0_VRF18_REQ_LSB BIT(14) 1786 #define DISP1_APSRC_REQ_LSB BIT(15) 1787 #define DISP1_DDREN_REQ_LSB BIT(16) 1788 #define DISP1_EMI_REQ_LSB BIT(17) 1789 #define DISP1_INFRA_REQ_LSB BIT(18) 1790 #define DISP1_PMIC_REQ_LSB BIT(19) 1791 #define DISP1_SRCCLKENA_LSB BIT(20) 1792 #define DISP1_VRF18_REQ_LSB BIT(21) 1793 #define DPM_APSRC_REQ_LSB BIT(22) 1794 #define DPM_DDREN_REQ_LSB BIT(26) 1795 #define DPM_EMI_REQ_LSB BIT(0) 1796 #define DPM_INFRA_REQ_LSB BIT(4) 1797 #define DPM_PMIC_REQ_LSB BIT(8) 1798 #define DPM_SRCCLKENA_LSB BIT(12) 1799 #define DPM_VCORE_REQ_LSB BIT(16) 1800 #define DPM_VRF18_REQ_LSB BIT(20) 1801 #define DPMAIF_APSRC_REQ_LSB BIT(24) 1802 #define DPMAIF_DDREN_REQ_LSB BIT(25) 1803 #define DPMAIF_EMI_REQ_LSB BIT(26) 1804 #define DPMAIF_INFRA_REQ_LSB BIT(27) 1805 #define DPMAIF_PMIC_REQ_LSB BIT(28) 1806 #define DPMAIF_SRCCLKENA_LSB BIT(29) 1807 #define DPMAIF_VCORE_REQ_LSB BIT(30) 1808 #define DPMAIF_VRF18_REQ_LSB BIT(31) 1809 #define DVFSRC_LEVEL_REQ_LSB BIT(0) 1810 #define EMISYS_APSRC_REQ_LSB BIT(1) 1811 #define EMISYS_DDREN_REQ_LSB BIT(2) 1812 #define EMISYS_EMI_REQ_LSB BIT(3) 1813 #define EMISYS_INFRA_REQ_LSB BIT(4) 1814 #define EMISYS_PMIC_REQ_LSB BIT(5) 1815 #define EMISYS_SRCCLKENA_LSB BIT(6) 1816 #define EMISYS_VCORE_REQ_LSB BIT(7) 1817 #define EMISYS_VRF18_REQ_LSB BIT(8) 1818 #define GCE_APSRC_REQ_LSB BIT(9) 1819 #define GCE_DDREN_REQ_LSB BIT(10) 1820 #define GCE_EMI_REQ_LSB BIT(11) 1821 #define GCE_INFRA_REQ_LSB BIT(12) 1822 #define GCE_PMIC_REQ_LSB BIT(13) 1823 #define GCE_SRCCLKENA_LSB BIT(14) 1824 #define GCE_VCORE_REQ_LSB BIT(15) 1825 #define GCE_VRF18_REQ_LSB BIT(16) 1826 #define GPUEB_APSRC_REQ_LSB BIT(17) 1827 #define GPUEB_DDREN_REQ_LSB BIT(18) 1828 #define GPUEB_EMI_REQ_LSB BIT(19) 1829 #define GPUEB_INFRA_REQ_LSB BIT(20) 1830 #define GPUEB_PMIC_REQ_LSB BIT(21) 1831 #define GPUEB_SRCCLKENA_LSB BIT(22) 1832 #define GPUEB_VCORE_REQ_LSB BIT(23) 1833 #define GPUEB_VRF18_REQ_LSB BIT(24) 1834 #define HWCCF_APSRC_REQ_LSB BIT(25) 1835 #define HWCCF_DDREN_REQ_LSB BIT(26) 1836 #define HWCCF_EMI_REQ_LSB BIT(27) 1837 #define HWCCF_INFRA_REQ_LSB BIT(28) 1838 #define HWCCF_PMIC_REQ_LSB BIT(29) 1839 #define HWCCF_SRCCLKENA_LSB BIT(30) 1840 #define HWCCF_VCORE_REQ_LSB BIT(31) 1841 #define HWCCF_VRF18_REQ_LSB BIT(0) 1842 #define IMG_APSRC_REQ_LSB BIT(1) 1843 #define IMG_DDREN_REQ_LSB BIT(2) 1844 #define IMG_EMI_REQ_LSB BIT(3) 1845 #define IMG_INFRA_REQ_LSB BIT(4) 1846 #define IMG_PMIC_REQ_LSB BIT(5) 1847 #define IMG_SRCCLKENA_LSB BIT(6) 1848 #define IMG_VRF18_REQ_LSB BIT(7) 1849 #define INFRASYS_APSRC_REQ_LSB BIT(8) 1850 #define INFRASYS_DDREN_REQ_LSB BIT(9) 1851 #define INFRASYS_EMI_REQ_LSB BIT(10) 1852 #define INFRASYS_INFRA_REQ_LSB BIT(11) 1853 #define INFRASYS_PMIC_REQ_LSB BIT(12) 1854 #define INFRASYS_SRCCLKENA_LSB BIT(13) 1855 #define INFRASYS_VCORE_REQ_LSB BIT(14) 1856 #define INFRASYS_VRF18_REQ_LSB BIT(15) 1857 #define IPIC_INFRA_REQ_LSB BIT(16) 1858 #define IPIC_VRF18_REQ_LSB BIT(17) 1859 #define MCU_APSRC_REQ_LSB BIT(18) 1860 #define MCU_DDREN_REQ_LSB BIT(19) 1861 #define MCU_EMI_REQ_LSB BIT(20) 1862 #define MCU_INFRA_REQ_LSB BIT(21) 1863 #define MCU_PMIC_REQ_LSB BIT(22) 1864 #define MCU_SRCCLKENA_LSB BIT(23) 1865 #define MCU_VCORE_REQ_LSB BIT(24) 1866 #define MCU_VRF18_REQ_LSB BIT(25) 1867 #define MD_APSRC_REQ_LSB BIT(26) 1868 #define MD_DDREN_REQ_LSB BIT(27) 1869 #define MD_EMI_REQ_LSB BIT(28) 1870 #define MD_INFRA_REQ_LSB BIT(29) 1871 #define MD_PMIC_REQ_LSB BIT(30) 1872 #define MD_SRCCLKENA_LSB BIT(31) 1873 #define MD_SRCCLKENA1_LSB BIT(0) 1874 #define MD_VCORE_REQ_LSB BIT(1) 1875 #define MD_VRF18_REQ_LSB BIT(2) 1876 #define MM_PROC_APSRC_REQ_LSB BIT(3) 1877 #define MM_PROC_DDREN_REQ_LSB BIT(4) 1878 #define MM_PROC_EMI_REQ_LSB BIT(5) 1879 #define MM_PROC_INFRA_REQ_LSB BIT(6) 1880 #define MM_PROC_PMIC_REQ_LSB BIT(7) 1881 #define MM_PROC_SRCCLKENA_LSB BIT(8) 1882 #define MM_PROC_VCORE_REQ_LSB BIT(9) 1883 #define MM_PROC_VRF18_REQ_LSB BIT(10) 1884 #define MML0_APSRC_REQ_LSB BIT(11) 1885 #define MML0_DDREN_REQ_LSB BIT(12) 1886 #define MML0_EMI_REQ_LSB BIT(13) 1887 #define MML0_INFRA_REQ_LSB BIT(14) 1888 #define MML0_PMIC_REQ_LSB BIT(15) 1889 #define MML0_SRCCLKENA_LSB BIT(16) 1890 #define MML0_VRF18_REQ_LSB BIT(17) 1891 #define MML1_APSRC_REQ_LSB BIT(18) 1892 #define MML1_DDREN_REQ_LSB BIT(19) 1893 #define MML1_EMI_REQ_LSB BIT(20) 1894 #define MML1_INFRA_REQ_LSB BIT(21) 1895 #define MML1_PMIC_REQ_LSB BIT(22) 1896 #define MML1_SRCCLKENA_LSB BIT(23) 1897 #define MML1_VRF18_REQ_LSB BIT(24) 1898 #define OVL0_APSRC_REQ_LSB BIT(25) 1899 #define OVL0_DDREN_REQ_LSB BIT(26) 1900 #define OVL0_EMI_REQ_LSB BIT(27) 1901 #define OVL0_INFRA_REQ_LSB BIT(28) 1902 #define OVL0_PMIC_REQ_LSB BIT(29) 1903 #define OVL0_SRCCLKENA_LSB BIT(30) 1904 #define OVL0_VRF18_REQ_LSB BIT(31) 1905 #define OVL1_APSRC_REQ_LSB BIT(0) 1906 #define OVL1_DDREN_REQ_LSB BIT(1) 1907 #define OVL1_EMI_REQ_LSB BIT(2) 1908 #define OVL1_INFRA_REQ_LSB BIT(3) 1909 #define OVL1_PMIC_REQ_LSB BIT(4) 1910 #define OVL1_SRCCLKENA_LSB BIT(5) 1911 #define OVL1_VRF18_REQ_LSB BIT(6) 1912 #define PCIE0_APSRC_REQ_LSB BIT(7) 1913 #define PCIE0_DDREN_REQ_LSB BIT(8) 1914 #define PCIE0_EMI_REQ_LSB BIT(9) 1915 #define PCIE0_INFRA_REQ_LSB BIT(10) 1916 #define PCIE0_PMIC_REQ_LSB BIT(11) 1917 #define PCIE0_SRCCLKENA_LSB BIT(12) 1918 #define PCIE0_VCORE_REQ_LSB BIT(13) 1919 #define PCIE0_VRF18_REQ_LSB BIT(14) 1920 #define PCIE1_APSRC_REQ_LSB BIT(15) 1921 #define PCIE1_DDREN_REQ_LSB BIT(16) 1922 #define PCIE1_EMI_REQ_LSB BIT(17) 1923 #define PCIE1_INFRA_REQ_LSB BIT(18) 1924 #define PCIE1_PMIC_REQ_LSB BIT(19) 1925 #define PCIE1_SRCCLKENA_LSB BIT(20) 1926 #define PCIE1_VCORE_REQ_LSB BIT(21) 1927 #define PCIE1_VRF18_REQ_LSB BIT(22) 1928 #define PERISYS_APSRC_REQ_LSB BIT(23) 1929 #define PERISYS_DDREN_REQ_LSB BIT(24) 1930 #define PERISYS_EMI_REQ_LSB BIT(25) 1931 #define PERISYS_INFRA_REQ_LSB BIT(26) 1932 #define PERISYS_PMIC_REQ_LSB BIT(27) 1933 #define PERISYS_SRCCLKENA_LSB BIT(28) 1934 #define PERISYS_VCORE_REQ_LSB BIT(29) 1935 #define PERISYS_VRF18_REQ_LSB BIT(30) 1936 #define PMSR_APSRC_REQ_LSB BIT(31) 1937 #define PMSR_DDREN_REQ_LSB BIT(0) 1938 #define PMSR_EMI_REQ_LSB BIT(1) 1939 #define PMSR_INFRA_REQ_LSB BIT(2) 1940 #define PMSR_PMIC_REQ_LSB BIT(3) 1941 #define PMSR_SRCCLKENA_LSB BIT(4) 1942 #define PMSR_VCORE_REQ_LSB BIT(5) 1943 #define PMSR_VRF18_REQ_LSB BIT(6) 1944 #define SCP_APSRC_REQ_LSB BIT(7) 1945 #define SCP_DDREN_REQ_LSB BIT(8) 1946 #define SCP_EMI_REQ_LSB BIT(9) 1947 #define SCP_INFRA_REQ_LSB BIT(10) 1948 #define SCP_PMIC_REQ_LSB BIT(11) 1949 #define SCP_SRCCLKENA_LSB BIT(12) 1950 #define SCP_VCORE_REQ_LSB BIT(13) 1951 #define SCP_VRF18_REQ_LSB BIT(14) 1952 #define SPU_HWROT_APSRC_REQ_LSB BIT(15) 1953 #define SPU_HWROT_DDREN_REQ_LSB BIT(16) 1954 #define SPU_HWROT_EMI_REQ_LSB BIT(17) 1955 #define SPU_HWROT_INFRA_REQ_LSB BIT(18) 1956 #define SPU_HWROT_PMIC_REQ_LSB BIT(19) 1957 #define SPU_HWROT_SRCCLKENA_LSB BIT(20) 1958 #define SPU_HWROT_VCORE_REQ_LSB BIT(21) 1959 #define SPU_HWROT_VRF18_REQ_LSB BIT(22) 1960 #define SPU_ISE_APSRC_REQ_LSB BIT(23) 1961 #define SPU_ISE_DDREN_REQ_LSB BIT(24) 1962 #define SPU_ISE_EMI_REQ_LSB BIT(25) 1963 #define SPU_ISE_INFRA_REQ_LSB BIT(26) 1964 #define SPU_ISE_PMIC_REQ_LSB BIT(27) 1965 #define SPU_ISE_SRCCLKENA_LSB BIT(28) 1966 #define SPU_ISE_VCORE_REQ_LSB BIT(29) 1967 #define SPU_ISE_VRF18_REQ_LSB BIT(30) 1968 #define SRCCLKENI_INFRA_REQ_LSB BIT(0) 1969 #define SRCCLKENI_PMIC_REQ_LSB BIT(2) 1970 #define SRCCLKENI_SRCCLKENA_LSB BIT(4) 1971 #define SRCCLKENI_VCORE_REQ_LSB BIT(6) 1972 #define SSPM_APSRC_REQ_LSB BIT(8) 1973 #define SSPM_DDREN_REQ_LSB BIT(9) 1974 #define SSPM_EMI_REQ_LSB BIT(10) 1975 #define SSPM_INFRA_REQ_LSB BIT(11) 1976 #define SSPM_PMIC_REQ_LSB BIT(12) 1977 #define SSPM_SRCCLKENA_LSB BIT(13) 1978 #define SSPM_VRF18_REQ_LSB BIT(14) 1979 #define SSRSYS_APSRC_REQ_LSB BIT(15) 1980 #define SSRSYS_DDREN_REQ_LSB BIT(16) 1981 #define SSRSYS_EMI_REQ_LSB BIT(17) 1982 #define SSRSYS_INFRA_REQ_LSB BIT(18) 1983 #define SSRSYS_PMIC_REQ_LSB BIT(19) 1984 #define SSRSYS_SRCCLKENA_LSB BIT(20) 1985 #define SSRSYS_VCORE_REQ_LSB BIT(21) 1986 #define SSRSYS_VRF18_REQ_LSB BIT(22) 1987 #define SSUSB_APSRC_REQ_LSB BIT(23) 1988 #define SSUSB_DDREN_REQ_LSB BIT(24) 1989 #define SSUSB_EMI_REQ_LSB BIT(25) 1990 #define SSUSB_INFRA_REQ_LSB BIT(26) 1991 #define SSUSB_PMIC_REQ_LSB BIT(27) 1992 #define SSUSB_SRCCLKENA_LSB BIT(28) 1993 #define SSUSB_VCORE_REQ_LSB BIT(29) 1994 #define SSUSB_VRF18_REQ_LSB BIT(30) 1995 #define UART_HUB_INFRA_REQ_LSB BIT(31) 1996 #define UART_HUB_PMIC_REQ_LSB BIT(0) 1997 #define UART_HUB_SRCCLKENA_LSB BIT(1) 1998 #define UART_HUB_VCORE_REQ_LSB BIT(2) 1999 #define UART_HUB_VRF18_REQ_LSB BIT(3) 2000 #define UFS_APSRC_REQ_LSB BIT(4) 2001 #define UFS_DDREN_REQ_LSB BIT(5) 2002 #define UFS_EMI_REQ_LSB BIT(6) 2003 #define UFS_INFRA_REQ_LSB BIT(7) 2004 #define UFS_PMIC_REQ_LSB BIT(8) 2005 #define UFS_SRCCLKENA_LSB BIT(9) 2006 #define UFS_VCORE_REQ_LSB BIT(10) 2007 #define UFS_VRF18_REQ_LSB BIT(11) 2008 #define VDEC_APSRC_REQ_LSB BIT(12) 2009 #define VDEC_DDREN_REQ_LSB BIT(13) 2010 #define VDEC_EMI_REQ_LSB BIT(14) 2011 #define VDEC_INFRA_REQ_LSB BIT(15) 2012 #define VDEC_PMIC_REQ_LSB BIT(16) 2013 #define VDEC_SRCCLKENA_LSB BIT(17) 2014 #define VDEC_VRF18_REQ_LSB BIT(18) 2015 #define VENC_APSRC_REQ_LSB BIT(19) 2016 #define VENC_DDREN_REQ_LSB BIT(20) 2017 #define VENC_EMI_REQ_LSB BIT(21) 2018 #define VENC_INFRA_REQ_LSB BIT(22) 2019 #define VENC_PMIC_REQ_LSB BIT(23) 2020 #define VENC_SRCCLKENA_LSB BIT(24) 2021 #define VENC_VRF18_REQ_LSB BIT(25) 2022 #define VLPCFG_RSV0_APSRC_REQ_LSB BIT(26) 2023 #define VLPCFG_RSV0_DDREN_REQ_LSB BIT(27) 2024 #define VLPCFG_RSV0_EMI_REQ_LSB BIT(28) 2025 #define VLPCFG_RSV0_INFRA_REQ_LSB BIT(29) 2026 #define VLPCFG_RSV0_PMIC_REQ_LSB BIT(30) 2027 #define VLPCFG_RSV0_SRCCLKENA_LSB BIT(31) 2028 #define VLPCFG_RSV0_VCORE_REQ_LSB BIT(0) 2029 #define VLPCFG_RSV0_VRF18_REQ_LSB BIT(1) 2030 #define VLPCFG_RSV1_APSRC_REQ_LSB BIT(2) 2031 #define VLPCFG_RSV1_DDREN_REQ_LSB BIT(3) 2032 #define VLPCFG_RSV1_EMI_REQ_LSB BIT(4) 2033 #define VLPCFG_RSV1_INFRA_REQ_LSB BIT(5) 2034 #define VLPCFG_RSV1_PMIC_REQ_LSB BIT(6) 2035 #define VLPCFG_RSV1_SRCCLKENA_LSB BIT(7) 2036 #define VLPCFG_RSV1_VCORE_REQ_LSB BIT(8) 2037 #define VLPCFG_RSV1_VRF18_REQ_LSB BIT(9) 2038 #define SPM2SSPM_WAKEUP_LSB BIT(0) 2039 #define SPM2SCP_WAKEUP_LSB BIT(1) 2040 #define SPM2ADSP_WAKEUP_LSB BIT(2) 2041 #define REG_SW2SPM_WAKEUP_MB_LSB BIT(0) 2042 #define REG_SSPM2SPM_WAKEUP_MB_LSB BIT(4) 2043 #define REG_SCP2SPM_WAKEUP_MB_LSB BIT(5) 2044 #define REG_ADSP2SPM_WAKEUP_MB_LSB BIT(6) 2045 #define SSPM2SPM_WAKEUP_LSB BIT(20) 2046 #define SCP2SPM_WAKEUP_LSB BIT(21) 2047 #define ADSP2SPM_WAKEUP_LSB BIT(22) 2048 #define REG_SRCCLKEN_FAST_RESP_LSB BIT(0) 2049 #define REG_CSYSPWRUP_ACK_MASK_LSB BIT(1) 2050 #define REG_DDREN_DBC_LEN_LSB BIT(0) 2051 #define REG_DDREN_DBC_EN_LSB BIT(16) 2052 #define SPM_VCORE_ACK_WAIT_CYCLE_LSB BIT(0) 2053 #define SPM_PMIC_ACK_WAIT_CYCLE_LSB BIT(8) 2054 #define SPM_SRCCLKENA_ACK_WAIT_CYCLE_LSB BIT(16) 2055 #define SPM_INFRA_ACK_WAIT_CYCLE_LSB BIT(24) 2056 #define SPM_VRF18_ACK_WAIT_CYCLE_LSB BIT(0) 2057 #define SPM_EMI_ACK_WAIT_CYCLE_LSB BIT(8) 2058 #define SPM_APSRC_ACK_WAIT_CYCLE_LSB BIT(16) 2059 #define SPM_DDREN_ACK_WAIT_CYCLE_LSB BIT(24) 2060 #define REG_APIFR_APSRC_ACK_MASK_LSB BIT(0) 2061 #define REG_APIFR_DDREN_ACK_MASK_LSB BIT(1) 2062 #define REG_APIFR_EMI_ACK_MASK_LSB BIT(2) 2063 #define REG_APIFR_INFRA_ACK_MASK_LSB BIT(3) 2064 #define REG_APIFR_PMIC_ACK_MASK_LSB BIT(4) 2065 #define REG_APIFR_SRCCLKENA_ACK_MASK_LSB BIT(5) 2066 #define REG_APIFR_VCORE_ACK_MASK_LSB BIT(6) 2067 #define REG_APIFR_VRF18_ACK_MASK_LSB BIT(7) 2068 #define REG_APU_APSRC_ACK_MASK_LSB BIT(8) 2069 #define REG_APU_DDREN_ACK_MASK_LSB BIT(9) 2070 #define REG_APU_EMI_ACK_MASK_LSB BIT(10) 2071 #define REG_APU_INFRA_ACK_MASK_LSB BIT(11) 2072 #define REG_APU_PMIC_ACK_MASK_LSB BIT(12) 2073 #define REG_APU_SRCCLKENA_ACK_MASK_LSB BIT(13) 2074 #define REG_APU_VCORE_ACK_MASK_LSB BIT(14) 2075 #define REG_APU_VRF18_ACK_MASK_LSB BIT(15) 2076 #define REG_AUDIO_APSRC_ACK_MASK_LSB BIT(16) 2077 #define REG_AUDIO_DDREN_ACK_MASK_LSB BIT(17) 2078 #define REG_AUDIO_EMI_ACK_MASK_LSB BIT(18) 2079 #define REG_AUDIO_INFRA_ACK_MASK_LSB BIT(19) 2080 #define REG_AUDIO_PMIC_ACK_MASK_LSB BIT(20) 2081 #define REG_AUDIO_SRCCLKENA_ACK_MASK_LSB BIT(21) 2082 #define REG_AUDIO_VCORE_ACK_MASK_LSB BIT(22) 2083 #define REG_AUDIO_VRF18_ACK_MASK_LSB BIT(23) 2084 /* SPM_RESOURCE_ACK_MASK_1 (0x1C004000+0x8C0) */ 2085 #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB BIT(0) 2086 #define REG_AUDIO_DSP_DDREN_ACK_MASK_LSB BIT(1) 2087 #define REG_AUDIO_DSP_EMI_ACK_MASK_LSB BIT(2) 2088 #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB BIT(3) 2089 #define REG_AUDIO_DSP_PMIC_ACK_MASK_LSB BIT(4) 2090 #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB BIT(5) 2091 #define REG_AUDIO_DSP_VCORE_ACK_MASK_LSB BIT(6) 2092 #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB BIT(7) 2093 #define REG_SPM_EVENT_COUNTER_CLR_LSB BIT(0) 2094 #define SPM2MCUPM_SW_INT_LSB BIT(1) 2095 2096 #define SPM_PROJECT_CODE 0xb16 2097 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 2098 2099 #endif /* MT_SPM_REG_H */ 2100