1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_INTERNAL_H 8 #define MT_SPM_INTERNAL_H 9 10 #include <dbg_ctrl.h> 11 #include <mt_spm.h> 12 #include <mt_spm_stats.h> 13 14 /************************************** 15 * Config and Parameter 16 **************************************/ 17 #define POWER_ON_VAL0_DEF 0x0000F100 18 /* SPM_POWER_ON_VAL1 */ 19 #define POWER_ON_VAL1_DEF 0x003FFE20 20 /* SPM_WAKE_MASK*/ 21 #define SPM_WAKEUP_EVENT_MASK_DEF 0xEFFFFFFF 22 23 #define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ 24 #define PCM_TIMER_MAX (0xFFFFFFFF) 25 /************************************** 26 * Define and Declare 27 **************************************/ 28 /* PCM_PWR_IO_EN */ 29 #define PCM_PWRIO_EN_R0 BIT(0) 30 #define PCM_PWRIO_EN_R7 BIT(7) 31 #define PCM_RF_SYNC_R0 BIT(16) 32 #define PCM_RF_SYNC_R6 BIT(22) 33 #define PCM_RF_SYNC_R7 BIT(23) 34 35 /* SPM_SWINT */ 36 #define PCM_SW_INT0 BIT(0) 37 #define PCM_SW_INT1 BIT(1) 38 #define PCM_SW_INT2 BIT(2) 39 #define PCM_SW_INT3 BIT(3) 40 #define PCM_SW_INT4 BIT(4) 41 #define PCM_SW_INT5 BIT(5) 42 #define PCM_SW_INT6 BIT(6) 43 #define PCM_SW_INT7 BIT(7) 44 #define PCM_SW_INT8 BIT(8) 45 #define PCM_SW_INT9 BIT(9) 46 #define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ 47 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ 48 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ 49 PCM_SW_INT0) 50 51 /* SPM_AP_STANDBY_CON */ 52 #define WFI_OP_AND 1 53 #define WFI_OP_OR 0 54 55 /* SPM_IRQ_MASK */ 56 #define ISRM_TWAM BIT(2) 57 #define ISRM_PCM_RETURN BIT(3) 58 #define ISRM_RET_IRQ0 BIT(8) 59 #define ISRM_RET_IRQ1 BIT(9) 60 #define ISRM_RET_IRQ2 BIT(10) 61 #define ISRM_RET_IRQ3 BIT(11) 62 #define ISRM_RET_IRQ4 BIT(12) 63 #define ISRM_RET_IRQ5 BIT(13) 64 #define ISRM_RET_IRQ6 BIT(14) 65 #define ISRM_RET_IRQ7 BIT(15) 66 #define ISRM_RET_IRQ8 BIT(16) 67 #define ISRM_RET_IRQ9 BIT(17) 68 #define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \ 69 (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \ 70 (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \ 71 (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \ 72 (ISRM_RET_IRQ1)) 73 #define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) 74 #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) 75 76 /* SPM_IRQ_STA */ 77 #define ISRS_TWAM BIT(2) 78 #define ISRS_PCM_RETURN BIT(3) 79 #define ISRC_TWAM ISRS_TWAM 80 #define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN 81 #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) 82 83 /* SPM_WAKEUP_MISC */ 84 #define WAKE_MISC_GIC_WAKEUP 0x3FF /* bit0 ~ bit9 */ 85 #define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB 86 #define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB 87 #define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB 88 #define WAKE_MISC_PMIC_OUT_B (BIT(19) | BIT(20)) 89 #define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB 90 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB 91 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB 92 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB 93 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB 94 #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB 95 #define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB 96 #define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB 97 98 /* MD32PCM ADDR for SPM code fetch */ 99 #define MD32PCM_BASE (SPM_BASE + 0x0A00) 100 #define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000) 101 #define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200) 102 #define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204) 103 #define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208) 104 #define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C) 105 #define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210) 106 #define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214) 107 #define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218) 108 #define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224) 109 #define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C) 110 111 /* ABORT MASK for DEBUG FOORTPRINT */ 112 #define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \ 113 SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN) 114 115 #define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_0 | \ 116 SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_1 | \ 117 SPM_DBG1_DEBUG_IDX_VCORE_SLEEP_ABORT_0 | \ 118 SPM_DBG1_DEBUG_IDX_VCORE_SLEEP_ABORT_1 | \ 119 SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_LOW_ABORT | \ 120 SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_HIGH_ABORT | \ 121 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \ 122 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \ 123 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \ 124 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \ 125 SPM_DBG1_DEBUG_IDX_SPM_PMIF_CMD_RDY_ABORT) 126 127 struct pwr_ctrl { 128 129 /* For SPM */ 130 uint32_t pcm_flags; 131 uint32_t pcm_flags_cust; 132 uint32_t pcm_flags_cust_set; 133 uint32_t pcm_flags_cust_clr; 134 uint32_t pcm_flags1; 135 uint32_t pcm_flags1_cust; 136 uint32_t pcm_flags1_cust_set; 137 uint32_t pcm_flags1_cust_clr; 138 uint32_t timer_val; 139 uint32_t timer_val_cust; 140 uint32_t timer_val_ramp_en; 141 uint32_t timer_val_ramp_en_sec; 142 uint32_t wake_src; 143 uint32_t wake_src_cust; 144 uint32_t wakelock_timer_val; 145 uint8_t wdt_disable; 146 /* Auto-gen Start */ 147 148 /* SPM_CLK_CON */ 149 uint8_t reg_spm_lock_infra_dcm_lsb; 150 uint8_t reg_cxo32k_remove_en_lsb; 151 uint8_t reg_spm_leave_suspend_merge_mask_lsb; 152 uint8_t reg_sysclk0_src_mb_lsb; 153 uint8_t reg_sysclk1_src_mb_lsb; 154 uint8_t reg_sysclk2_src_mb_lsb; 155 156 /* SPM_AP_STANDBY_CON */ 157 uint8_t reg_wfi_op; 158 uint8_t reg_wfi_type; 159 uint8_t reg_mp0_cputop_idle_mask; 160 uint8_t reg_mp1_cputop_idle_mask; 161 uint8_t reg_mcusys_idle_mask; 162 uint8_t reg_csyspwrup_req_mask_lsb; 163 uint8_t reg_wfi_af_sel; 164 uint8_t reg_cpu_sleep_wfi; 165 166 /* SPM_SRC_REQ */ 167 uint8_t reg_spm_adsp_mailbox_req; 168 uint8_t reg_spm_apsrc_req; 169 uint8_t reg_spm_ddren_req; 170 uint8_t reg_spm_dvfs_req; 171 uint8_t reg_spm_emi_req; 172 uint8_t reg_spm_f26m_req; 173 uint8_t reg_spm_infra_req; 174 uint8_t reg_spm_pmic_req; 175 uint8_t reg_spm_scp_mailbox_req; 176 uint8_t reg_spm_sspm_mailbox_req; 177 uint8_t reg_spm_sw_mailbox_req; 178 uint8_t reg_spm_vcore_req; 179 uint8_t reg_spm_vrf18_req; 180 uint8_t adsp_mailbox_state; 181 uint8_t apsrc_state; 182 uint8_t ddren_state; 183 uint8_t dvfs_state; 184 uint8_t emi_state; 185 uint8_t f26m_state; 186 uint8_t infra_state; 187 uint8_t pmic_state; 188 uint8_t scp_mailbox_state; 189 uint8_t sspm_mailbox_state; 190 uint8_t sw_mailbox_state; 191 uint8_t vcore_state; 192 uint8_t vrf18_state; 193 194 /* SPM_SRC_MASK_0 */ 195 uint8_t reg_apifr_apsrc_rmb; 196 uint8_t reg_apifr_ddren_rmb; 197 uint8_t reg_apifr_emi_rmb; 198 uint8_t reg_apifr_infra_rmb; 199 uint8_t reg_apifr_pmic_rmb; 200 uint8_t reg_apifr_srcclkena_mb; 201 uint8_t reg_apifr_vcore_rmb; 202 uint8_t reg_apifr_vrf18_rmb; 203 uint8_t reg_apu_apsrc_rmb; 204 uint8_t reg_apu_ddren_rmb; 205 uint8_t reg_apu_emi_rmb; 206 uint8_t reg_apu_infra_rmb; 207 uint8_t reg_apu_pmic_rmb; 208 uint8_t reg_apu_srcclkena_mb; 209 uint8_t reg_apu_vcore_rmb; 210 uint8_t reg_apu_vrf18_rmb; 211 uint8_t reg_audio_apsrc_rmb; 212 uint8_t reg_audio_ddren_rmb; 213 uint8_t reg_audio_emi_rmb; 214 uint8_t reg_audio_infra_rmb; 215 uint8_t reg_audio_pmic_rmb; 216 uint8_t reg_audio_srcclkena_mb; 217 uint8_t reg_audio_vcore_rmb; 218 uint8_t reg_audio_vrf18_rmb; 219 220 /* SPM_SRC_MASK_1 */ 221 uint8_t reg_audio_dsp_apsrc_rmb; 222 uint8_t reg_audio_dsp_ddren_rmb; 223 uint8_t reg_audio_dsp_emi_rmb; 224 uint8_t reg_audio_dsp_infra_rmb; 225 uint8_t reg_audio_dsp_pmic_rmb; 226 uint8_t reg_audio_dsp_srcclkena_mb; 227 uint8_t reg_audio_dsp_vcore_rmb; 228 uint8_t reg_audio_dsp_vrf18_rmb; 229 uint8_t reg_cam_apsrc_rmb; 230 uint8_t reg_cam_ddren_rmb; 231 uint8_t reg_cam_emi_rmb; 232 uint8_t reg_cam_infra_rmb; 233 uint8_t reg_cam_pmic_rmb; 234 uint8_t reg_cam_srcclkena_mb; 235 uint8_t reg_cam_vrf18_rmb; 236 uint32_t reg_ccif_apsrc_rmb; 237 238 /* SPM_SRC_MASK_2 */ 239 uint32_t reg_ccif_emi_rmb; 240 uint32_t reg_ccif_infra_rmb; 241 242 /* SPM_SRC_MASK_3 */ 243 uint32_t reg_ccif_pmic_rmb; 244 uint32_t reg_ccif_srcclkena_mb; 245 246 /* SPM_SRC_MASK_4 */ 247 uint32_t reg_ccif_vcore_rmb; 248 uint32_t reg_ccif_vrf18_rmb; 249 uint8_t reg_ccu_apsrc_rmb; 250 uint8_t reg_ccu_ddren_rmb; 251 uint8_t reg_ccu_emi_rmb; 252 uint8_t reg_ccu_infra_rmb; 253 uint8_t reg_ccu_pmic_rmb; 254 uint8_t reg_ccu_srcclkena_mb; 255 uint8_t reg_ccu_vrf18_rmb; 256 uint8_t reg_cg_check_apsrc_rmb; 257 258 /* SPM_SRC_MASK_5 */ 259 uint8_t reg_cg_check_ddren_rmb; 260 uint8_t reg_cg_check_emi_rmb; 261 uint8_t reg_cg_check_infra_rmb; 262 uint8_t reg_cg_check_pmic_rmb; 263 uint8_t reg_cg_check_srcclkena_mb; 264 uint8_t reg_cg_check_vcore_rmb; 265 uint8_t reg_cg_check_vrf18_rmb; 266 uint8_t reg_cksys_apsrc_rmb; 267 uint8_t reg_cksys_ddren_rmb; 268 uint8_t reg_cksys_emi_rmb; 269 uint8_t reg_cksys_infra_rmb; 270 uint8_t reg_cksys_pmic_rmb; 271 uint8_t reg_cksys_srcclkena_mb; 272 uint8_t reg_cksys_vcore_rmb; 273 uint8_t reg_cksys_vrf18_rmb; 274 uint8_t reg_cksys_1_apsrc_rmb; 275 uint8_t reg_cksys_1_ddren_rmb; 276 uint8_t reg_cksys_1_emi_rmb; 277 uint8_t reg_cksys_1_infra_rmb; 278 uint8_t reg_cksys_1_pmic_rmb; 279 uint8_t reg_cksys_1_srcclkena_mb; 280 uint8_t reg_cksys_1_vcore_rmb; 281 uint8_t reg_cksys_1_vrf18_rmb; 282 283 /* SPM_SRC_MASK_6 */ 284 uint8_t reg_cksys_2_apsrc_rmb; 285 uint8_t reg_cksys_2_ddren_rmb; 286 uint8_t reg_cksys_2_emi_rmb; 287 uint8_t reg_cksys_2_infra_rmb; 288 uint8_t reg_cksys_2_pmic_rmb; 289 uint8_t reg_cksys_2_srcclkena_mb; 290 uint8_t reg_cksys_2_vcore_rmb; 291 uint8_t reg_cksys_2_vrf18_rmb; 292 uint8_t reg_conn_apsrc_rmb; 293 uint8_t reg_conn_ddren_rmb; 294 uint8_t reg_conn_emi_rmb; 295 uint8_t reg_conn_infra_rmb; 296 uint8_t reg_conn_pmic_rmb; 297 uint8_t reg_conn_srcclkena_mb; 298 uint8_t reg_conn_srcclkenb_mb; 299 uint8_t reg_conn_vcore_rmb; 300 uint8_t reg_conn_vrf18_rmb; 301 uint8_t reg_corecfg_apsrc_rmb; 302 uint8_t reg_corecfg_ddren_rmb; 303 uint8_t reg_corecfg_emi_rmb; 304 uint8_t reg_corecfg_infra_rmb; 305 uint8_t reg_corecfg_pmic_rmb; 306 uint8_t reg_corecfg_srcclkena_mb; 307 uint8_t reg_corecfg_vcore_rmb; 308 uint8_t reg_corecfg_vrf18_rmb; 309 310 /* SPM_SRC_MASK_7 */ 311 uint8_t reg_cpueb_apsrc_rmb; 312 uint8_t reg_cpueb_ddren_rmb; 313 uint8_t reg_cpueb_emi_rmb; 314 uint8_t reg_cpueb_infra_rmb; 315 uint8_t reg_cpueb_pmic_rmb; 316 uint8_t reg_cpueb_srcclkena_mb; 317 uint8_t reg_cpueb_vcore_rmb; 318 uint8_t reg_cpueb_vrf18_rmb; 319 uint8_t reg_disp0_apsrc_rmb; 320 uint8_t reg_disp0_ddren_rmb; 321 uint8_t reg_disp0_emi_rmb; 322 uint8_t reg_disp0_infra_rmb; 323 uint8_t reg_disp0_pmic_rmb; 324 uint8_t reg_disp0_srcclkena_mb; 325 uint8_t reg_disp0_vrf18_rmb; 326 uint8_t reg_disp1_apsrc_rmb; 327 uint8_t reg_disp1_ddren_rmb; 328 uint8_t reg_disp1_emi_rmb; 329 uint8_t reg_disp1_infra_rmb; 330 uint8_t reg_disp1_pmic_rmb; 331 uint8_t reg_disp1_srcclkena_mb; 332 uint8_t reg_disp1_vrf18_rmb; 333 uint8_t reg_dpm_apsrc_rmb; 334 uint8_t reg_dpm_ddren_rmb; 335 336 /* SPM_SRC_MASK_8 */ 337 uint8_t reg_dpm_emi_rmb; 338 uint8_t reg_dpm_infra_rmb; 339 uint8_t reg_dpm_pmic_rmb; 340 uint8_t reg_dpm_srcclkena_mb; 341 uint8_t reg_dpm_vcore_rmb; 342 uint8_t reg_dpm_vrf18_rmb; 343 uint8_t reg_dpmaif_apsrc_rmb; 344 uint8_t reg_dpmaif_ddren_rmb; 345 uint8_t reg_dpmaif_emi_rmb; 346 uint8_t reg_dpmaif_infra_rmb; 347 uint8_t reg_dpmaif_pmic_rmb; 348 uint8_t reg_dpmaif_srcclkena_mb; 349 uint8_t reg_dpmaif_vcore_rmb; 350 uint8_t reg_dpmaif_vrf18_rmb; 351 352 /* SPM_SRC_MASK_9 */ 353 uint8_t reg_dvfsrc_level_rmb; 354 uint8_t reg_emisys_apsrc_rmb; 355 uint8_t reg_emisys_ddren_rmb; 356 uint8_t reg_emisys_emi_rmb; 357 uint8_t reg_emisys_infra_rmb; 358 uint8_t reg_emisys_pmic_rmb; 359 uint8_t reg_emisys_srcclkena_mb; 360 uint8_t reg_emisys_vcore_rmb; 361 uint8_t reg_emisys_vrf18_rmb; 362 uint8_t reg_gce_apsrc_rmb; 363 uint8_t reg_gce_ddren_rmb; 364 uint8_t reg_gce_emi_rmb; 365 uint8_t reg_gce_infra_rmb; 366 uint8_t reg_gce_pmic_rmb; 367 uint8_t reg_gce_srcclkena_mb; 368 uint8_t reg_gce_vcore_rmb; 369 uint8_t reg_gce_vrf18_rmb; 370 uint8_t reg_gpueb_apsrc_rmb; 371 uint8_t reg_gpueb_ddren_rmb; 372 uint8_t reg_gpueb_emi_rmb; 373 uint8_t reg_gpueb_infra_rmb; 374 uint8_t reg_gpueb_pmic_rmb; 375 uint8_t reg_gpueb_srcclkena_mb; 376 uint8_t reg_gpueb_vcore_rmb; 377 uint8_t reg_gpueb_vrf18_rmb; 378 uint8_t reg_hwccf_apsrc_rmb; 379 uint8_t reg_hwccf_ddren_rmb; 380 uint8_t reg_hwccf_emi_rmb; 381 uint8_t reg_hwccf_infra_rmb; 382 uint8_t reg_hwccf_pmic_rmb; 383 uint8_t reg_hwccf_srcclkena_mb; 384 uint8_t reg_hwccf_vcore_rmb; 385 386 /* SPM_SRC_MASK_10 */ 387 uint8_t reg_hwccf_vrf18_rmb; 388 uint8_t reg_img_apsrc_rmb; 389 uint8_t reg_img_ddren_rmb; 390 uint8_t reg_img_emi_rmb; 391 uint8_t reg_img_infra_rmb; 392 uint8_t reg_img_pmic_rmb; 393 uint8_t reg_img_srcclkena_mb; 394 uint8_t reg_img_vrf18_rmb; 395 uint8_t reg_infrasys_apsrc_rmb; 396 uint8_t reg_infrasys_ddren_rmb; 397 uint8_t reg_infrasys_emi_rmb; 398 uint8_t reg_infrasys_infra_rmb; 399 uint8_t reg_infrasys_pmic_rmb; 400 uint8_t reg_infrasys_srcclkena_mb; 401 uint8_t reg_infrasys_vcore_rmb; 402 uint8_t reg_infrasys_vrf18_rmb; 403 uint8_t reg_ipic_infra_rmb; 404 uint8_t reg_ipic_vrf18_rmb; 405 uint8_t reg_mcu_apsrc_rmb; 406 uint8_t reg_mcu_ddren_rmb; 407 uint8_t reg_mcu_emi_rmb; 408 uint8_t reg_mcu_infra_rmb; 409 uint8_t reg_mcu_pmic_rmb; 410 uint8_t reg_mcu_srcclkena_mb; 411 uint8_t reg_mcu_vcore_rmb; 412 uint8_t reg_mcu_vrf18_rmb; 413 uint8_t reg_md_apsrc_rmb; 414 uint8_t reg_md_ddren_rmb; 415 uint8_t reg_md_emi_rmb; 416 uint8_t reg_md_infra_rmb; 417 uint8_t reg_md_pmic_rmb; 418 uint8_t reg_md_srcclkena_mb; 419 420 /* SPM_SRC_MASK_11 */ 421 uint8_t reg_md_srcclkena1_mb; 422 uint8_t reg_md_vcore_rmb; 423 uint8_t reg_md_vrf18_rmb; 424 uint8_t reg_mm_proc_apsrc_rmb; 425 uint8_t reg_mm_proc_ddren_rmb; 426 uint8_t reg_mm_proc_emi_rmb; 427 uint8_t reg_mm_proc_infra_rmb; 428 uint8_t reg_mm_proc_pmic_rmb; 429 uint8_t reg_mm_proc_srcclkena_mb; 430 uint8_t reg_mm_proc_vcore_rmb; 431 uint8_t reg_mm_proc_vrf18_rmb; 432 uint8_t reg_mml0_apsrc_rmb; 433 uint8_t reg_mml0_ddren_rmb; 434 uint8_t reg_mml0_emi_rmb; 435 uint8_t reg_mml0_infra_rmb; 436 uint8_t reg_mml0_pmic_rmb; 437 uint8_t reg_mml0_srcclkena_mb; 438 uint8_t reg_mml0_vrf18_rmb; 439 uint8_t reg_mml1_apsrc_rmb; 440 uint8_t reg_mml1_ddren_rmb; 441 uint8_t reg_mml1_emi_rmb; 442 uint8_t reg_mml1_infra_rmb; 443 uint8_t reg_mml1_pmic_rmb; 444 uint8_t reg_mml1_srcclkena_mb; 445 uint8_t reg_mml1_vrf18_rmb; 446 uint8_t reg_ovl0_apsrc_rmb; 447 uint8_t reg_ovl0_ddren_rmb; 448 uint8_t reg_ovl0_emi_rmb; 449 uint8_t reg_ovl0_infra_rmb; 450 uint8_t reg_ovl0_pmic_rmb; 451 uint8_t reg_ovl0_srcclkena_mb; 452 uint8_t reg_ovl0_vrf18_rmb; 453 454 /* SPM_SRC_MASK_12 */ 455 uint8_t reg_ovl1_apsrc_rmb; 456 uint8_t reg_ovl1_ddren_rmb; 457 uint8_t reg_ovl1_emi_rmb; 458 uint8_t reg_ovl1_infra_rmb; 459 uint8_t reg_ovl1_pmic_rmb; 460 uint8_t reg_ovl1_srcclkena_mb; 461 uint8_t reg_ovl1_vrf18_rmb; 462 uint8_t reg_pcie0_apsrc_rmb; 463 uint8_t reg_pcie0_ddren_rmb; 464 uint8_t reg_pcie0_emi_rmb; 465 uint8_t reg_pcie0_infra_rmb; 466 uint8_t reg_pcie0_pmic_rmb; 467 uint8_t reg_pcie0_srcclkena_mb; 468 uint8_t reg_pcie0_vcore_rmb; 469 uint8_t reg_pcie0_vrf18_rmb; 470 uint8_t reg_pcie1_apsrc_rmb; 471 uint8_t reg_pcie1_ddren_rmb; 472 uint8_t reg_pcie1_emi_rmb; 473 uint8_t reg_pcie1_infra_rmb; 474 uint8_t reg_pcie1_pmic_rmb; 475 uint8_t reg_pcie1_srcclkena_mb; 476 uint8_t reg_pcie1_vcore_rmb; 477 uint8_t reg_pcie1_vrf18_rmb; 478 uint8_t reg_perisys_apsrc_rmb; 479 uint8_t reg_perisys_ddren_rmb; 480 uint8_t reg_perisys_emi_rmb; 481 uint8_t reg_perisys_infra_rmb; 482 uint8_t reg_perisys_pmic_rmb; 483 uint8_t reg_perisys_srcclkena_mb; 484 uint8_t reg_perisys_vcore_rmb; 485 uint8_t reg_perisys_vrf18_rmb; 486 uint8_t reg_pmsr_apsrc_rmb; 487 488 /* SPM_SRC_MASK_13 */ 489 uint8_t reg_pmsr_ddren_rmb; 490 uint8_t reg_pmsr_emi_rmb; 491 uint8_t reg_pmsr_infra_rmb; 492 uint8_t reg_pmsr_pmic_rmb; 493 uint8_t reg_pmsr_srcclkena_mb; 494 uint8_t reg_pmsr_vcore_rmb; 495 uint8_t reg_pmsr_vrf18_rmb; 496 uint8_t reg_scp_apsrc_rmb; 497 uint8_t reg_scp_ddren_rmb; 498 uint8_t reg_scp_emi_rmb; 499 uint8_t reg_scp_infra_rmb; 500 uint8_t reg_scp_pmic_rmb; 501 uint8_t reg_scp_srcclkena_mb; 502 uint8_t reg_scp_vcore_rmb; 503 uint8_t reg_scp_vrf18_rmb; 504 uint8_t reg_spu_hwr_apsrc_rmb; 505 uint8_t reg_spu_hwr_ddren_rmb; 506 uint8_t reg_spu_hwr_emi_rmb; 507 uint8_t reg_spu_hwr_infra_rmb; 508 uint8_t reg_spu_hwr_pmic_rmb; 509 uint8_t reg_spu_hwr_srcclkena_mb; 510 uint8_t reg_spu_hwr_vcore_rmb; 511 uint8_t reg_spu_hwr_vrf18_rmb; 512 uint8_t reg_spu_ise_apsrc_rmb; 513 uint8_t reg_spu_ise_ddren_rmb; 514 uint8_t reg_spu_ise_emi_rmb; 515 uint8_t reg_spu_ise_infra_rmb; 516 uint8_t reg_spu_ise_pmic_rmb; 517 uint8_t reg_spu_ise_srcclkena_mb; 518 uint8_t reg_spu_ise_vcore_rmb; 519 uint8_t reg_spu_ise_vrf18_rmb; 520 521 /* SPM_SRC_MASK_14 */ 522 uint8_t reg_srcclkeni_infra_rmb; 523 uint8_t reg_srcclkeni_pmic_rmb; 524 uint8_t reg_srcclkeni_srcclkena_mb; 525 uint8_t reg_srcclkeni_vcore_rmb; 526 uint8_t reg_sspm_apsrc_rmb; 527 uint8_t reg_sspm_ddren_rmb; 528 uint8_t reg_sspm_emi_rmb; 529 uint8_t reg_sspm_infra_rmb; 530 uint8_t reg_sspm_pmic_rmb; 531 uint8_t reg_sspm_srcclkena_mb; 532 uint8_t reg_sspm_vrf18_rmb; 533 uint8_t reg_ssrsys_apsrc_rmb; 534 uint8_t reg_ssrsys_ddren_rmb; 535 uint8_t reg_ssrsys_emi_rmb; 536 uint8_t reg_ssrsys_infra_rmb; 537 uint8_t reg_ssrsys_pmic_rmb; 538 uint8_t reg_ssrsys_srcclkena_mb; 539 uint8_t reg_ssrsys_vcore_rmb; 540 uint8_t reg_ssrsys_vrf18_rmb; 541 uint8_t reg_ssusb_apsrc_rmb; 542 uint8_t reg_ssusb_ddren_rmb; 543 uint8_t reg_ssusb_emi_rmb; 544 uint8_t reg_ssusb_infra_rmb; 545 uint8_t reg_ssusb_pmic_rmb; 546 uint8_t reg_ssusb_srcclkena_mb; 547 uint8_t reg_ssusb_vcore_rmb; 548 uint8_t reg_ssusb_vrf18_rmb; 549 uint8_t reg_uart_hub_infra_rmb; 550 551 /* SPM_SRC_MASK_15 */ 552 uint8_t reg_uart_hub_pmic_rmb; 553 uint8_t reg_uart_hub_srcclkena_mb; 554 uint8_t reg_uart_hub_vcore_rmb; 555 uint8_t reg_uart_hub_vrf18_rmb; 556 uint8_t reg_ufs_apsrc_rmb; 557 uint8_t reg_ufs_ddren_rmb; 558 uint8_t reg_ufs_emi_rmb; 559 uint8_t reg_ufs_infra_rmb; 560 uint8_t reg_ufs_pmic_rmb; 561 uint8_t reg_ufs_srcclkena_mb; 562 uint8_t reg_ufs_vcore_rmb; 563 uint8_t reg_ufs_vrf18_rmb; 564 uint8_t reg_vdec_apsrc_rmb; 565 uint8_t reg_vdec_ddren_rmb; 566 uint8_t reg_vdec_emi_rmb; 567 uint8_t reg_vdec_infra_rmb; 568 uint8_t reg_vdec_pmic_rmb; 569 uint8_t reg_vdec_srcclkena_mb; 570 uint8_t reg_vdec_vrf18_rmb; 571 uint8_t reg_venc_apsrc_rmb; 572 uint8_t reg_venc_ddren_rmb; 573 uint8_t reg_venc_emi_rmb; 574 uint8_t reg_venc_infra_rmb; 575 uint8_t reg_venc_pmic_rmb; 576 uint8_t reg_venc_srcclkena_mb; 577 uint8_t reg_venc_vrf18_rmb; 578 uint8_t reg_vlpcfg_apsrc_rmb; 579 uint8_t reg_vlpcfg_ddren_rmb; 580 uint8_t reg_vlpcfg_emi_rmb; 581 uint8_t reg_vlpcfg_infra_rmb; 582 uint8_t reg_vlpcfg_pmic_rmb; 583 uint8_t reg_vlpcfg_srcclkena_mb; 584 585 /* SPM_SRC_MASK_16 */ 586 uint8_t reg_vlpcfg_vcore_rmb; 587 uint8_t reg_vlpcfg_vrf18_rmb; 588 uint8_t reg_vlpcfg1_apsrc_rmb; 589 uint8_t reg_vlpcfg1_ddren_rmb; 590 uint8_t reg_vlpcfg1_emi_rmb; 591 uint8_t reg_vlpcfg1_infra_rmb; 592 uint8_t reg_vlpcfg1_pmic_rmb; 593 uint8_t reg_vlpcfg1_srcclkena_mb; 594 uint8_t reg_vlpcfg1_vcore_rmb; 595 uint8_t reg_vlpcfg1_vrf18_rmb; 596 597 /* SPM_EVENT_CON_MISC */ 598 uint8_t reg_srcclken_fast_resp; 599 uint8_t reg_csyspwrup_ack_mask; 600 601 /* SPM_SRC_MASK_17 */ 602 uint32_t reg_spm_sw_vcore_rmb; 603 uint32_t reg_spm_sw_pmic_rmb; 604 605 /* SPM_SRC_MASK_18 */ 606 uint32_t reg_spm_sw_srcclkena_mb; 607 608 /* SPM_WAKE_MASK*/ 609 uint32_t reg_wake_mask; 610 611 /* SPM_WAKEUP_EVENT_EXT_MASK */ 612 uint32_t reg_ext_wake_mask; 613 }; 614 615 enum pwr_ctrl_enum { 616 PW_PCM_FLAGS, 617 PW_PCM_FLAGS_CUST, 618 PW_PCM_FLAGS_CUST_SET, 619 PW_PCM_FLAGS_CUST_CLR, 620 PW_PCM_FLAGS1, 621 PW_PCM_FLAGS1_CUST, 622 PW_PCM_FLAGS1_CUST_SET, 623 PW_PCM_FLAGS1_CUST_CLR, 624 PW_TIMER_VAL, 625 PW_TIMER_VAL_CUST, 626 PW_TIMER_VAL_RAMP_EN, 627 PW_TIMER_VAL_RAMP_EN_SEC, 628 PW_WAKE_SRC, 629 PW_WAKE_SRC_CUST, 630 PW_WAKELOCK_TIMER_VAL, 631 PW_WDT_DISABLE, 632 633 /* SPM_SRC_REQ */ 634 PW_REG_SPM_ADSP_MAILBOX_REQ, 635 PW_REG_SPM_APSRC_REQ, 636 PW_REG_SPM_DDREN_REQ, 637 PW_REG_SPM_DVFS_REQ, 638 PW_REG_SPM_EMI_REQ, 639 PW_REG_SPM_F26M_REQ, 640 PW_REG_SPM_INFRA_REQ, 641 PW_REG_SPM_PMIC_REQ, 642 PW_REG_SPM_SCP_MAILBOX_REQ, 643 PW_REG_SPM_SSPM_MAILBOX_REQ, 644 PW_REG_SPM_SW_MAILBOX_REQ, 645 PW_REG_SPM_VCORE_REQ, 646 PW_REG_SPM_VRF18_REQ, 647 648 /* SPM_SRC_MASK_0 */ 649 PW_REG_APIFR_APSRC_RMB, 650 PW_REG_APIFR_DDREN_RMB, 651 PW_REG_APIFR_EMI_RMB, 652 PW_REG_APIFR_INFRA_RMB, 653 PW_REG_APIFR_PMIC_RMB, 654 PW_REG_APIFR_SRCCLKENA_MB, 655 PW_REG_APIFR_VCORE_RMB, 656 PW_REG_APIFR_VRF18_RMB, 657 PW_REG_APU_APSRC_RMB, 658 PW_REG_APU_DDREN_RMB, 659 PW_REG_APU_EMI_RMB, 660 PW_REG_APU_INFRA_RMB, 661 PW_REG_APU_PMIC_RMB, 662 PW_REG_APU_SRCCLKENA_MB, 663 PW_REG_APU_VCORE_RMB, 664 PW_REG_APU_VRF18_RMB, 665 PW_REG_AUDIO_APSRC_RMB, 666 PW_REG_AUDIO_DDREN_RMB, 667 PW_REG_AUDIO_EMI_RMB, 668 PW_REG_AUDIO_INFRA_RMB, 669 PW_REG_AUDIO_PMIC_RMB, 670 PW_REG_AUDIO_SRCCLKENA_MB, 671 PW_REG_AUDIO_VCORE_RMB, 672 PW_REG_AUDIO_VRF18_RMB, 673 674 /* SPM_SRC_MASK_1 */ 675 PW_REG_AUDIO_DSP_APSRC_RMB, 676 PW_REG_AUDIO_DSP_DDREN_RMB, 677 PW_REG_AUDIO_DSP_EMI_RMB, 678 PW_REG_AUDIO_DSP_INFRA_RMB, 679 PW_REG_AUDIO_DSP_PMIC_RMB, 680 PW_REG_AUDIO_DSP_SRCCLKENA_MB, 681 PW_REG_AUDIO_DSP_VCORE_RMB, 682 PW_REG_AUDIO_DSP_VRF18_RMB, 683 PW_REG_CAM_APSRC_RMB, 684 PW_REG_CAM_DDREN_RMB, 685 PW_REG_CAM_EMI_RMB, 686 PW_REG_CAM_INFRA_RMB, 687 PW_REG_CAM_PMIC_RMB, 688 PW_REG_CAM_SRCCLKENA_MB, 689 PW_REG_CAM_VRF18_RMB, 690 PW_REG_CCIF_APSRC_RMB, 691 692 /* SPM_SRC_MASK_2 */ 693 PW_REG_CCIF_EMI_RMB, 694 PW_REG_CCIF_INFRA_RMB, 695 696 /* SPM_SRC_MASK_3 */ 697 PW_REG_CCIF_PMIC_RMB, 698 PW_REG_CCIF_SRCCLKENA_MB, 699 700 /* SPM_SRC_MASK_4 */ 701 PW_REG_CCIF_VCORE_RMB, 702 PW_REG_CCIF_VRF18_RMB, 703 PW_REG_CCU_APSRC_RMB, 704 PW_REG_CCU_DDREN_RMB, 705 PW_REG_CCU_EMI_RMB, 706 PW_REG_CCU_INFRA_RMB, 707 PW_REG_CCU_PMIC_RMB, 708 PW_REG_CCU_SRCCLKENA_MB, 709 PW_REG_CCU_VRF18_RMB, 710 PW_REG_CG_CHECK_APSRC_RMB, 711 712 /* SPM_SRC_MASK_5 */ 713 PW_REG_CG_CHECK_DDREN_RMB, 714 PW_REG_CG_CHECK_EMI_RMB, 715 PW_REG_CG_CHECK_INFRA_RMB, 716 PW_REG_CG_CHECK_PMIC_RMB, 717 PW_REG_CG_CHECK_SRCCLKENA_MB, 718 PW_REG_CG_CHECK_VCORE_RMB, 719 PW_REG_CG_CHECK_VRF18_RMB, 720 PW_REG_CKSYS_APSRC_RMB, 721 PW_REG_CKSYS_DDREN_RMB, 722 PW_REG_CKSYS_EMI_RMB, 723 PW_REG_CKSYS_INFRA_RMB, 724 PW_REG_CKSYS_PMIC_RMB, 725 PW_REG_CKSYS_SRCCLKENA_MB, 726 PW_REG_CKSYS_VCORE_RMB, 727 PW_REG_CKSYS_VRF18_RMB, 728 PW_REG_CKSYS_1_APSRC_RMB, 729 PW_REG_CKSYS_1_DDREN_RMB, 730 PW_REG_CKSYS_1_EMI_RMB, 731 PW_REG_CKSYS_1_INFRA_RMB, 732 PW_REG_CKSYS_1_PMIC_RMB, 733 PW_REG_CKSYS_1_SRCCLKENA_MB, 734 PW_REG_CKSYS_1_VCORE_RMB, 735 PW_REG_CKSYS_1_VRF18_RMB, 736 737 /* SPM_SRC_MASK_6 */ 738 PW_REG_CKSYS_2_APSRC_RMB, 739 PW_REG_CKSYS_2_DDREN_RMB, 740 PW_REG_CKSYS_2_EMI_RMB, 741 PW_REG_CKSYS_2_INFRA_RMB, 742 PW_REG_CKSYS_2_PMIC_RMB, 743 PW_REG_CKSYS_2_SRCCLKENA_MB, 744 PW_REG_CKSYS_2_VCORE_RMB, 745 PW_REG_CKSYS_2_VRF18_RMB, 746 PW_REG_CONN_APSRC_RMB, 747 PW_REG_CONN_DDREN_RMB, 748 PW_REG_CONN_EMI_RMB, 749 PW_REG_CONN_INFRA_RMB, 750 PW_REG_CONN_PMIC_RMB, 751 PW_REG_CONN_SRCCLKENA_MB, 752 PW_REG_CONN_SRCCLKENB_MB, 753 PW_REG_CONN_VCORE_RMB, 754 PW_REG_CONN_VRF18_RMB, 755 PW_REG_CORECFG_APSRC_RMB, 756 PW_REG_CORECFG_DDREN_RMB, 757 PW_REG_CORECFG_EMI_RMB, 758 PW_REG_CORECFG_INFRA_RMB, 759 PW_REG_CORECFG_PMIC_RMB, 760 PW_REG_CORECFG_SRCCLKENA_MB, 761 PW_REG_CORECFG_VCORE_RMB, 762 PW_REG_CORECFG_VRF18_RMB, 763 764 /* SPM_SRC_MASK_7 */ 765 PW_REG_CPUEB_APSRC_RMB, 766 PW_REG_CPUEB_DDREN_RMB, 767 PW_REG_CPUEB_EMI_RMB, 768 PW_REG_CPUEB_INFRA_RMB, 769 PW_REG_CPUEB_PMIC_RMB, 770 PW_REG_CPUEB_SRCCLKENA_MB, 771 PW_REG_CPUEB_VCORE_RMB, 772 PW_REG_CPUEB_VRF18_RMB, 773 PW_REG_DISP0_APSRC_RMB, 774 PW_REG_DISP0_DDREN_RMB, 775 PW_REG_DISP0_EMI_RMB, 776 PW_REG_DISP0_INFRA_RMB, 777 PW_REG_DISP0_PMIC_RMB, 778 PW_REG_DISP0_SRCCLKENA_MB, 779 PW_REG_DISP0_VRF18_RMB, 780 PW_REG_DISP1_APSRC_RMB, 781 PW_REG_DISP1_DDREN_RMB, 782 PW_REG_DISP1_EMI_RMB, 783 PW_REG_DISP1_INFRA_RMB, 784 PW_REG_DISP1_PMIC_RMB, 785 PW_REG_DISP1_SRCCLKENA_MB, 786 PW_REG_DISP1_VRF18_RMB, 787 PW_REG_DPM_APSRC_RMB, 788 PW_REG_DPM_DDREN_RMB, 789 790 /* SPM_SRC_MASK_8 */ 791 PW_REG_DPM_EMI_RMB, 792 PW_REG_DPM_INFRA_RMB, 793 PW_REG_DPM_PMIC_RMB, 794 PW_REG_DPM_SRCCLKENA_MB, 795 PW_REG_DPM_VCORE_RMB, 796 PW_REG_DPM_VRF18_RMB, 797 PW_REG_DPMAIF_APSRC_RMB, 798 PW_REG_DPMAIF_DDREN_RMB, 799 PW_REG_DPMAIF_EMI_RMB, 800 PW_REG_DPMAIF_INFRA_RMB, 801 PW_REG_DPMAIF_PMIC_RMB, 802 PW_REG_DPMAIF_SRCCLKENA_MB, 803 PW_REG_DPMAIF_VCORE_RMB, 804 PW_REG_DPMAIF_VRF18_RMB, 805 806 /* SPM_SRC_MASK_9 */ 807 PW_REG_DVFSRC_LEVEL_RMB, 808 PW_REG_EMISYS_APSRC_RMB, 809 PW_REG_EMISYS_DDREN_RMB, 810 PW_REG_EMISYS_EMI_RMB, 811 PW_REG_EMISYS_INFRA_RMB, 812 PW_REG_EMISYS_PMIC_RMB, 813 PW_REG_EMISYS_SRCCLKENA_MB, 814 PW_REG_EMISYS_VCORE_RMB, 815 PW_REG_EMISYS_VRF18_RMB, 816 PW_REG_GCE_APSRC_RMB, 817 PW_REG_GCE_DDREN_RMB, 818 PW_REG_GCE_EMI_RMB, 819 PW_REG_GCE_INFRA_RMB, 820 PW_REG_GCE_PMIC_RMB, 821 PW_REG_GCE_SRCCLKENA_MB, 822 PW_REG_GCE_VCORE_RMB, 823 PW_REG_GCE_VRF18_RMB, 824 PW_REG_GPUEB_APSRC_RMB, 825 PW_REG_GPUEB_DDREN_RMB, 826 PW_REG_GPUEB_EMI_RMB, 827 PW_REG_GPUEB_INFRA_RMB, 828 PW_REG_GPUEB_PMIC_RMB, 829 PW_REG_GPUEB_SRCCLKENA_MB, 830 PW_REG_GPUEB_VCORE_RMB, 831 PW_REG_GPUEB_VRF18_RMB, 832 PW_REG_HWCCF_APSRC_RMB, 833 PW_REG_HWCCF_DDREN_RMB, 834 PW_REG_HWCCF_EMI_RMB, 835 PW_REG_HWCCF_INFRA_RMB, 836 PW_REG_HWCCF_PMIC_RMB, 837 PW_REG_HWCCF_SRCCLKENA_MB, 838 PW_REG_HWCCF_VCORE_RMB, 839 840 /* SPM_SRC_MASK_10 */ 841 PW_REG_HWCCF_VRF18_RMB, 842 PW_REG_IMG_APSRC_RMB, 843 PW_REG_IMG_DDREN_RMB, 844 PW_REG_IMG_EMI_RMB, 845 PW_REG_IMG_INFRA_RMB, 846 PW_REG_IMG_PMIC_RMB, 847 PW_REG_IMG_SRCCLKENA_MB, 848 PW_REG_IMG_VRF18_RMB, 849 PW_REG_INFRASYS_APSRC_RMB, 850 PW_REG_INFRASYS_DDREN_RMB, 851 PW_REG_INFRASYS_EMI_RMB, 852 PW_REG_INFRASYS_INFRA_RMB, 853 PW_REG_INFRASYS_PMIC_RMB, 854 PW_REG_INFRASYS_SRCCLKENA_MB, 855 PW_REG_INFRASYS_VCORE_RMB, 856 PW_REG_INFRASYS_VRF18_RMB, 857 PW_REG_IPIC_INFRA_RMB, 858 PW_REG_IPIC_VRF18_RMB, 859 PW_REG_MCU_APSRC_RMB, 860 PW_REG_MCU_DDREN_RMB, 861 PW_REG_MCU_EMI_RMB, 862 PW_REG_MCU_INFRA_RMB, 863 PW_REG_MCU_PMIC_RMB, 864 PW_REG_MCU_SRCCLKENA_MB, 865 PW_REG_MCU_VCORE_RMB, 866 PW_REG_MCU_VRF18_RMB, 867 PW_REG_MD_APSRC_RMB, 868 PW_REG_MD_DDREN_RMB, 869 PW_REG_MD_EMI_RMB, 870 PW_REG_MD_INFRA_RMB, 871 PW_REG_MD_PMIC_RMB, 872 PW_REG_MD_SRCCLKENA_MB, 873 874 /* SPM_SRC_MASK_11 */ 875 PW_REG_MD_SRCCLKENA1_MB, 876 PW_REG_MD_VCORE_RMB, 877 PW_REG_MD_VRF18_RMB, 878 PW_REG_MM_PROC_APSRC_RMB, 879 PW_REG_MM_PROC_DDREN_RMB, 880 PW_REG_MM_PROC_EMI_RMB, 881 PW_REG_MM_PROC_INFRA_RMB, 882 PW_REG_MM_PROC_PMIC_RMB, 883 PW_REG_MM_PROC_SRCCLKENA_MB, 884 PW_REG_MM_PROC_VCORE_RMB, 885 PW_REG_MM_PROC_VRF18_RMB, 886 PW_REG_MML0_APSRC_RMB, 887 PW_REG_MML0_DDREN_RMB, 888 PW_REG_MML0_EMI_RMB, 889 PW_REG_MML0_INFRA_RMB, 890 PW_REG_MML0_PMIC_RMB, 891 PW_REG_MML0_SRCCLKENA_MB, 892 PW_REG_MML0_VRF18_RMB, 893 PW_REG_MML1_APSRC_RMB, 894 PW_REG_MML1_DDREN_RMB, 895 PW_REG_MML1_EMI_RMB, 896 PW_REG_MML1_INFRA_RMB, 897 PW_REG_MML1_PMIC_RMB, 898 PW_REG_MML1_SRCCLKENA_MB, 899 PW_REG_MML1_VRF18_RMB, 900 PW_REG_OVL0_APSRC_RMB, 901 PW_REG_OVL0_DDREN_RMB, 902 PW_REG_OVL0_EMI_RMB, 903 PW_REG_OVL0_INFRA_RMB, 904 PW_REG_OVL0_PMIC_RMB, 905 PW_REG_OVL0_SRCCLKENA_MB, 906 PW_REG_OVL0_VRF18_RMB, 907 908 /* SPM_SRC_MASK_12 */ 909 PW_REG_OVL1_APSRC_RMB, 910 PW_REG_OVL1_DDREN_RMB, 911 PW_REG_OVL1_EMI_RMB, 912 PW_REG_OVL1_INFRA_RMB, 913 PW_REG_OVL1_PMIC_RMB, 914 PW_REG_OVL1_SRCCLKENA_MB, 915 PW_REG_OVL1_VRF18_RMB, 916 PW_REG_PCIE0_APSRC_RMB, 917 PW_REG_PCIE0_DDREN_RMB, 918 PW_REG_PCIE0_EMI_RMB, 919 PW_REG_PCIE0_INFRA_RMB, 920 PW_REG_PCIE0_PMIC_RMB, 921 PW_REG_PCIE0_SRCCLKENA_MB, 922 PW_REG_PCIE0_VCORE_RMB, 923 PW_REG_PCIE0_VRF18_RMB, 924 PW_REG_PCIE1_APSRC_RMB, 925 PW_REG_PCIE1_DDREN_RMB, 926 PW_REG_PCIE1_EMI_RMB, 927 PW_REG_PCIE1_INFRA_RMB, 928 PW_REG_PCIE1_PMIC_RMB, 929 PW_REG_PCIE1_SRCCLKENA_MB, 930 PW_REG_PCIE1_VCORE_RMB, 931 PW_REG_PCIE1_VRF18_RMB, 932 PW_REG_PERISYS_APSRC_RMB, 933 PW_REG_PERISYS_DDREN_RMB, 934 PW_REG_PERISYS_EMI_RMB, 935 PW_REG_PERISYS_INFRA_RMB, 936 PW_REG_PERISYS_PMIC_RMB, 937 PW_REG_PERISYS_SRCCLKENA_MB, 938 PW_REG_PERISYS_VCORE_RMB, 939 PW_REG_PERISYS_VRF18_RMB, 940 PW_REG_PMSR_APSRC_RMB, 941 942 /* SPM_SRC_MASK_13 */ 943 PW_REG_PMSR_DDREN_RMB, 944 PW_REG_PMSR_EMI_RMB, 945 PW_REG_PMSR_INFRA_RMB, 946 PW_REG_PMSR_PMIC_RMB, 947 PW_REG_PMSR_SRCCLKENA_MB, 948 PW_REG_PMSR_VCORE_RMB, 949 PW_REG_PMSR_VRF18_RMB, 950 PW_REG_SCP_APSRC_RMB, 951 PW_REG_SCP_DDREN_RMB, 952 PW_REG_SCP_EMI_RMB, 953 PW_REG_SCP_INFRA_RMB, 954 PW_REG_SCP_PMIC_RMB, 955 PW_REG_SCP_SRCCLKENA_MB, 956 PW_REG_SCP_VCORE_RMB, 957 PW_REG_SCP_VRF18_RMB, 958 PW_REG_SPU_HWR_APSRC_RMB, 959 PW_REG_SPU_HWR_DDREN_RMB, 960 PW_REG_SPU_HWR_EMI_RMB, 961 PW_REG_SPU_HWR_INFRA_RMB, 962 PW_REG_SPU_HWR_PMIC_RMB, 963 PW_REG_SPU_HWR_SRCCLKENA_MB, 964 PW_REG_SPU_HWR_VCORE_RMB, 965 PW_REG_SPU_HWR_VRF18_RMB, 966 PW_REG_SPU_ISE_APSRC_RMB, 967 PW_REG_SPU_ISE_DDREN_RMB, 968 PW_REG_SPU_ISE_EMI_RMB, 969 PW_REG_SPU_ISE_INFRA_RMB, 970 PW_REG_SPU_ISE_PMIC_RMB, 971 PW_REG_SPU_ISE_SRCCLKENA_MB, 972 PW_REG_SPU_ISE_VCORE_RMB, 973 PW_REG_SPU_ISE_VRF18_RMB, 974 975 /* SPM_SRC_MASK_14 */ 976 PW_REG_SRCCLKENI_INFRA_RMB, 977 PW_REG_SRCCLKENI_PMIC_RMB, 978 PW_REG_SRCCLKENI_SRCCLKENA_MB, 979 PW_REG_SRCCLKENI_VCORE_RMB, 980 PW_REG_SSPM_APSRC_RMB, 981 PW_REG_SSPM_DDREN_RMB, 982 PW_REG_SSPM_EMI_RMB, 983 PW_REG_SSPM_INFRA_RMB, 984 PW_REG_SSPM_PMIC_RMB, 985 PW_REG_SSPM_SRCCLKENA_MB, 986 PW_REG_SSPM_VRF18_RMB, 987 PW_REG_SSRSYS_APSRC_RMB, 988 PW_REG_SSRSYS_DDREN_RMB, 989 PW_REG_SSRSYS_EMI_RMB, 990 PW_REG_SSRSYS_INFRA_RMB, 991 PW_REG_SSRSYS_PMIC_RMB, 992 PW_REG_SSRSYS_SRCCLKENA_MB, 993 PW_REG_SSRSYS_VCORE_RMB, 994 PW_REG_SSRSYS_VRF18_RMB, 995 PW_REG_SSUSB_APSRC_RMB, 996 PW_REG_SSUSB_DDREN_RMB, 997 PW_REG_SSUSB_EMI_RMB, 998 PW_REG_SSUSB_INFRA_RMB, 999 PW_REG_SSUSB_PMIC_RMB, 1000 PW_REG_SSUSB_SRCCLKENA_MB, 1001 PW_REG_SSUSB_VCORE_RMB, 1002 PW_REG_SSUSB_VRF18_RMB, 1003 PW_REG_UART_HUB_INFRA_RMB, 1004 1005 /* SPM_SRC_MASK_15 */ 1006 PW_REG_UART_HUB_PMIC_RMB, 1007 PW_REG_UART_HUB_SRCCLKENA_MB, 1008 PW_REG_UART_HUB_VCORE_RMB, 1009 PW_REG_UART_HUB_VRF18_RMB, 1010 PW_REG_UFS_APSRC_RMB, 1011 PW_REG_UFS_DDREN_RMB, 1012 PW_REG_UFS_EMI_RMB, 1013 PW_REG_UFS_INFRA_RMB, 1014 PW_REG_UFS_PMIC_RMB, 1015 PW_REG_UFS_SRCCLKENA_MB, 1016 PW_REG_UFS_VCORE_RMB, 1017 PW_REG_UFS_VRF18_RMB, 1018 PW_REG_VDEC_APSRC_RMB, 1019 PW_REG_VDEC_DDREN_RMB, 1020 PW_REG_VDEC_EMI_RMB, 1021 PW_REG_VDEC_INFRA_RMB, 1022 PW_REG_VDEC_PMIC_RMB, 1023 PW_REG_VDEC_SRCCLKENA_MB, 1024 PW_REG_VDEC_VRF18_RMB, 1025 PW_REG_VENC_APSRC_RMB, 1026 PW_REG_VENC_DDREN_RMB, 1027 PW_REG_VENC_EMI_RMB, 1028 PW_REG_VENC_INFRA_RMB, 1029 PW_REG_VENC_PMIC_RMB, 1030 PW_REG_VENC_SRCCLKENA_MB, 1031 PW_REG_VENC_VRF18_RMB, 1032 PW_REG_VLPCFG_APSRC_RMB, 1033 PW_REG_VLPCFG_DDREN_RMB, 1034 PW_REG_VLPCFG_EMI_RMB, 1035 PW_REG_VLPCFG_INFRA_RMB, 1036 PW_REG_VLPCFG_PMIC_RMB, 1037 PW_REG_VLPCFG_SRCCLKENA_MB, 1038 1039 /* SPM_SRC_MASK_16 */ 1040 PW_REG_VLPCFG_VCORE_RMB, 1041 PW_REG_VLPCFG_VRF18_RMB, 1042 PW_REG_VLPCFG1_APSRC_RMB, 1043 PW_REG_VLPCFG1_DDREN_RMB, 1044 PW_REG_VLPCFG1_EMI_RMB, 1045 PW_REG_VLPCFG1_INFRA_RMB, 1046 PW_REG_VLPCFG1_PMIC_RMB, 1047 PW_REG_VLPCFG1_SRCCLKENA_MB, 1048 PW_REG_VLPCFG1_VCORE_RMB, 1049 PW_REG_VLPCFG1_VRF18_RMB, 1050 1051 /* SPM_EVENT_CON_MISC */ 1052 PW_REG_SRCCLKEN_FAST_RESP, 1053 PW_REG_CSYSPWRUP_ACK_MASK, 1054 1055 /* SPM_SRC_MASK_17 */ 1056 PW_REG_SPM_SW_VCORE_RMB, 1057 PW_REG_SPM_SW_PMIC_RMB, 1058 1059 /* SPM_SRC_MASK_18 */ 1060 PW_REG_SPM_SW_SRCCLKENA_MB, 1061 1062 /* SPM_WAKE_MASK*/ 1063 PW_REG_WAKEUP_EVENT_MASK, 1064 1065 /* SPM_WAKEUP_EVENT_EXT_MASK */ 1066 PW_REG_EXT_WAKEUP_EVENT_MASK, 1067 1068 PW_MAX_COUNT, 1069 }; 1070 1071 /* spm_internal.c internal status */ 1072 #define SPM_INTERNAL_STATUS_HW_S1 BIT(0) 1073 1074 /* 1075 * HW_TARG_GROUP_SEL_3 : 3b'1 (pcm_reg_13) 1076 * HW_TARG_SIGNAL_SEL_3 : 5b'10101 1077 * HW_TRIG_GROUP_SEL_3 : 3'b100 (trig_reserve) 1078 * HW_TRIG_SIGNAL_SEL_3 : 5'b1100 (trig_reserve[24]=sc_hw_s1_req) 1079 */ 1080 #define SPM_ACK_CHK_3_SEL_HW_S1 (0x00350098) 1081 #define SPM_ACK_CHK_3_HW_S1_CNT (1) 1082 1083 #define SPM_ACK_CHK_3_CON_HW_MODE_TRIG (0x800) 1084 /* BIT[0]: SW_EN, BIT[4]: STA_EN, BIT[8]: HW_EN */ 1085 #define SPM_ACK_CHK_3_CON_EN (0x110) 1086 #define SPM_ACK_CHK_3_CON_CLR_ALL (0x2) 1087 /* BIT[15]: RESULT */ 1088 #define SPM_ACK_CHK_3_CON_RESULT (0x8000) 1089 1090 struct wake_status_trace_comm { 1091 uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */ 1092 uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */ 1093 uint32_t timer_out; /* SPM_SW_RSV_6*/ 1094 uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */ 1095 uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */ 1096 uint32_t r12; /* SPM_SW_RSV_0 */ 1097 uint32_t r13; /* PCM_REG13_DATA */ 1098 uint32_t req_sta0; /* SRC_REQ_STA_0 */ 1099 uint32_t req_sta1; /* SRC_REQ_STA_1 */ 1100 uint32_t req_sta2; /* SRC_REQ_STA_2 */ 1101 uint32_t req_sta3; /* SRC_REQ_STA_3 */ 1102 uint32_t req_sta4; /* SRC_REQ_STA_4 */ 1103 uint32_t req_sta5; /* SRC_REQ_STA_5 */ 1104 uint32_t req_sta6; /* SRC_REQ_STA_6 */ 1105 uint32_t req_sta7; /* SRC_REQ_STA_7 */ 1106 uint32_t req_sta8; /* SRC_REQ_STA_8 */ 1107 uint32_t req_sta9; /* SRC_REQ_STA_9 */ 1108 uint32_t req_sta10; /* SRC_REQ_STA_10 */ 1109 uint32_t req_sta11; /* SRC_REQ_STA_11 */ 1110 uint32_t req_sta12; /* SRC_REQ_STA_12 */ 1111 uint32_t req_sta13; /* SRC_REQ_STA_13 */ 1112 uint32_t req_sta14; /* SRC_REQ_STA_14 */ 1113 uint32_t req_sta15; /* SRC_REQ_STA_15 */ 1114 uint32_t req_sta16; /* SRC_REQ_STA_16 */ 1115 uint32_t raw_sta; /* SPM_WAKEUP_STA */ 1116 uint32_t times_h; /* Timestamp high bits */ 1117 uint32_t times_l; /* Timestamp low bits */ 1118 uint32_t resumetime; /* Timestamp low bits */ 1119 }; 1120 1121 struct wake_status_trace { 1122 struct wake_status_trace_comm comm; 1123 /* Add suspend or idle part bellow */ 1124 }; 1125 1126 struct wake_status { 1127 struct wake_status_trace tr; 1128 uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */ 1129 uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */ 1130 uint32_t md32pcm_wakeup_sta; /* MD32PCM_WAKEUP_STA */ 1131 uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */ 1132 uint32_t wake_misc; /* SPM_SW_RSV_5 */ 1133 uint32_t sw_flag0; /* SPM_SW_FLAG_0 */ 1134 uint32_t sw_flag1; /* SPM_SW_FLAG_1 */ 1135 uint32_t isr; /* SPM_IRQ_STA */ 1136 uint32_t log_index; 1137 uint32_t is_abort; 1138 }; 1139 1140 struct spm_lp_scen { 1141 struct pcm_desc *pcmdesc; 1142 struct pwr_ctrl *pwrctrl; 1143 struct dbg_ctrl *dbgctrl; 1144 struct spm_lp_stat *lpstat; 1145 }; 1146 1147 extern struct spm_lp_scen __spm_vcorefs; 1148 typedef uint32_t u32; 1149 1150 void __spm_init_pcm_register(void); /* init r0 and r7 */ 1151 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl, 1152 uint32_t resource_usage); 1153 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); 1154 void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl); 1155 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl); 1156 void __spm_send_cpu_wakeup_event(void); 1157 1158 void __spm_get_wakeup_status(struct wake_status *wakesta, 1159 uint32_t ext_status); 1160 void __spm_clean_after_wakeup(void); 1161 wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta); 1162 1163 void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl, 1164 const struct pwr_ctrl *src_pwr_ctrl); 1165 void __spm_sync_vcore_dvfs_pcm_flags(uint32_t *dest_pcm_flags, 1166 const uint32_t *src_pcm_flags); 1167 1168 void __spm_set_pcm_wdt(int en); 1169 uint32_t __spm_get_pcm_timer_val(void); 1170 uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr); 1171 void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl); 1172 void __spm_ext_int_wakeup_req_clr(void); 1173 1174 static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl, 1175 uint32_t flags) 1176 { 1177 if (pwrctrl->pcm_flags_cust == 0) 1178 pwrctrl->pcm_flags = flags; 1179 else 1180 pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust; 1181 } 1182 1183 static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl, 1184 uint32_t flags) 1185 { 1186 if (pwrctrl->pcm_flags1_cust == 0) 1187 pwrctrl->pcm_flags1 = flags; 1188 else 1189 pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust; 1190 } 1191 1192 void __spm_hw_s1_state_monitor(int en, uint32_t *status); 1193 1194 static inline void spm_hw_s1_state_monitor_resume(void) 1195 { 1196 __spm_hw_s1_state_monitor(1, NULL); 1197 } 1198 static inline void spm_hw_s1_state_monitor_pause(uint32_t *status) 1199 { 1200 __spm_hw_s1_state_monitor(0, status); 1201 } 1202 1203 int32_t __spm_wait_spm_request_ack(uint32_t spm_resource_req, 1204 uint32_t timeout_us); 1205 1206 #endif /* MT_SPM_INTERNAL */ 1207