1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_INTERNAL_H 8 #define MT_SPM_INTERNAL_H 9 10 #include <dbg_ctrl.h> 11 #include <mt_spm.h> 12 #include <mt_spm_stats.h> 13 14 /************************************** 15 * Config and Parameter 16 **************************************/ 17 #define POWER_ON_VAL0_DEF 0x0000F100 18 /* SPM_POWER_ON_VAL1 */ 19 #define POWER_ON_VAL1_DEF 0x003FFE20 20 /* SPM_WAKE_MASK*/ 21 #define SPM_WAKEUP_EVENT_MASK_DEF 0xEFFFFFFF 22 23 #define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ 24 #define PCM_TIMER_MAX (0xFFFFFFFF) 25 /************************************** 26 * Define and Declare 27 **************************************/ 28 /* MD32PCM ADDR for SPM code fetch */ 29 #define MD32PCM_BASE (SPM_BASE + 0x0A00) 30 #define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000) 31 #define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200) 32 #define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204) 33 #define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208) 34 #define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C) 35 #define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210) 36 #define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214) 37 #define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218) 38 #define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224) 39 #define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C) 40 41 /* ABORT MASK for DEBUG FOORTPRINT */ 42 #define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \ 43 SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN) 44 45 #define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_0 | \ 46 SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_1 | \ 47 SPM_DBG1_DEBUG_IDX_VCORE_SLEEP_ABORT_0 | \ 48 SPM_DBG1_DEBUG_IDX_VCORE_SLEEP_ABORT_1 | \ 49 SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_LOW_ABORT | \ 50 SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_HIGH_ABORT | \ 51 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \ 52 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \ 53 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \ 54 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \ 55 SPM_DBG1_DEBUG_IDX_SPM_PMIF_CMD_RDY_ABORT) 56 57 struct pwr_ctrl { 58 59 /* For SPM */ 60 uint32_t pcm_flags; 61 uint32_t pcm_flags_cust; 62 uint32_t pcm_flags_cust_set; 63 uint32_t pcm_flags_cust_clr; 64 uint32_t pcm_flags1; 65 uint32_t pcm_flags1_cust; 66 uint32_t pcm_flags1_cust_set; 67 uint32_t pcm_flags1_cust_clr; 68 uint32_t timer_val; 69 uint32_t timer_val_cust; 70 uint32_t timer_val_ramp_en; 71 uint32_t timer_val_ramp_en_sec; 72 uint32_t wake_src; 73 uint32_t wake_src_cust; 74 uint32_t wakelock_timer_val; 75 uint8_t wdt_disable; 76 /* Auto-gen Start */ 77 78 /* SPM_CLK_CON */ 79 uint8_t reg_spm_lock_infra_dcm_lsb; 80 uint8_t reg_cxo32k_remove_en_lsb; 81 uint8_t reg_spm_leave_suspend_merge_mask_lsb; 82 uint8_t reg_sysclk0_src_mb_lsb; 83 uint8_t reg_sysclk1_src_mb_lsb; 84 uint8_t reg_sysclk2_src_mb_lsb; 85 86 /* SPM_AP_STANDBY_CON */ 87 uint8_t reg_wfi_op; 88 uint8_t reg_wfi_type; 89 uint8_t reg_mp0_cputop_idle_mask; 90 uint8_t reg_mp1_cputop_idle_mask; 91 uint8_t reg_mcusys_idle_mask; 92 uint8_t reg_csyspwrup_req_mask_lsb; 93 uint8_t reg_wfi_af_sel; 94 uint8_t reg_cpu_sleep_wfi; 95 96 /* SPM_SRC_REQ */ 97 uint8_t reg_spm_adsp_mailbox_req; 98 uint8_t reg_spm_apsrc_req; 99 uint8_t reg_spm_ddren_req; 100 uint8_t reg_spm_dvfs_req; 101 uint8_t reg_spm_emi_req; 102 uint8_t reg_spm_f26m_req; 103 uint8_t reg_spm_infra_req; 104 uint8_t reg_spm_pmic_req; 105 uint8_t reg_spm_scp_mailbox_req; 106 uint8_t reg_spm_sspm_mailbox_req; 107 uint8_t reg_spm_sw_mailbox_req; 108 uint8_t reg_spm_vcore_req; 109 uint8_t reg_spm_vrf18_req; 110 uint8_t adsp_mailbox_state; 111 uint8_t apsrc_state; 112 uint8_t ddren_state; 113 uint8_t dvfs_state; 114 uint8_t emi_state; 115 uint8_t f26m_state; 116 uint8_t infra_state; 117 uint8_t pmic_state; 118 uint8_t scp_mailbox_state; 119 uint8_t sspm_mailbox_state; 120 uint8_t sw_mailbox_state; 121 uint8_t vcore_state; 122 uint8_t vrf18_state; 123 124 /* SPM_SRC_MASK_0 */ 125 uint8_t reg_apifr_apsrc_rmb; 126 uint8_t reg_apifr_ddren_rmb; 127 uint8_t reg_apifr_emi_rmb; 128 uint8_t reg_apifr_infra_rmb; 129 uint8_t reg_apifr_pmic_rmb; 130 uint8_t reg_apifr_srcclkena_mb; 131 uint8_t reg_apifr_vcore_rmb; 132 uint8_t reg_apifr_vrf18_rmb; 133 uint8_t reg_apu_apsrc_rmb; 134 uint8_t reg_apu_ddren_rmb; 135 uint8_t reg_apu_emi_rmb; 136 uint8_t reg_apu_infra_rmb; 137 uint8_t reg_apu_pmic_rmb; 138 uint8_t reg_apu_srcclkena_mb; 139 uint8_t reg_apu_vcore_rmb; 140 uint8_t reg_apu_vrf18_rmb; 141 uint8_t reg_audio_apsrc_rmb; 142 uint8_t reg_audio_ddren_rmb; 143 uint8_t reg_audio_emi_rmb; 144 uint8_t reg_audio_infra_rmb; 145 uint8_t reg_audio_pmic_rmb; 146 uint8_t reg_audio_srcclkena_mb; 147 uint8_t reg_audio_vcore_rmb; 148 uint8_t reg_audio_vrf18_rmb; 149 150 /* SPM_SRC_MASK_1 */ 151 uint8_t reg_audio_dsp_apsrc_rmb; 152 uint8_t reg_audio_dsp_ddren_rmb; 153 uint8_t reg_audio_dsp_emi_rmb; 154 uint8_t reg_audio_dsp_infra_rmb; 155 uint8_t reg_audio_dsp_pmic_rmb; 156 uint8_t reg_audio_dsp_srcclkena_mb; 157 uint8_t reg_audio_dsp_vcore_rmb; 158 uint8_t reg_audio_dsp_vrf18_rmb; 159 uint8_t reg_cam_apsrc_rmb; 160 uint8_t reg_cam_ddren_rmb; 161 uint8_t reg_cam_emi_rmb; 162 uint8_t reg_cam_infra_rmb; 163 uint8_t reg_cam_pmic_rmb; 164 uint8_t reg_cam_srcclkena_mb; 165 uint8_t reg_cam_vrf18_rmb; 166 uint32_t reg_ccif_apsrc_rmb; 167 168 /* SPM_SRC_MASK_2 */ 169 uint32_t reg_ccif_emi_rmb; 170 uint32_t reg_ccif_infra_rmb; 171 172 /* SPM_SRC_MASK_3 */ 173 uint32_t reg_ccif_pmic_rmb; 174 uint32_t reg_ccif_srcclkena_mb; 175 176 /* SPM_SRC_MASK_4 */ 177 uint32_t reg_ccif_vcore_rmb; 178 uint32_t reg_ccif_vrf18_rmb; 179 uint8_t reg_ccu_apsrc_rmb; 180 uint8_t reg_ccu_ddren_rmb; 181 uint8_t reg_ccu_emi_rmb; 182 uint8_t reg_ccu_infra_rmb; 183 uint8_t reg_ccu_pmic_rmb; 184 uint8_t reg_ccu_srcclkena_mb; 185 uint8_t reg_ccu_vrf18_rmb; 186 uint8_t reg_cg_check_apsrc_rmb; 187 188 /* SPM_SRC_MASK_5 */ 189 uint8_t reg_cg_check_ddren_rmb; 190 uint8_t reg_cg_check_emi_rmb; 191 uint8_t reg_cg_check_infra_rmb; 192 uint8_t reg_cg_check_pmic_rmb; 193 uint8_t reg_cg_check_srcclkena_mb; 194 uint8_t reg_cg_check_vcore_rmb; 195 uint8_t reg_cg_check_vrf18_rmb; 196 uint8_t reg_cksys_apsrc_rmb; 197 uint8_t reg_cksys_ddren_rmb; 198 uint8_t reg_cksys_emi_rmb; 199 uint8_t reg_cksys_infra_rmb; 200 uint8_t reg_cksys_pmic_rmb; 201 uint8_t reg_cksys_srcclkena_mb; 202 uint8_t reg_cksys_vcore_rmb; 203 uint8_t reg_cksys_vrf18_rmb; 204 uint8_t reg_cksys_1_apsrc_rmb; 205 uint8_t reg_cksys_1_ddren_rmb; 206 uint8_t reg_cksys_1_emi_rmb; 207 uint8_t reg_cksys_1_infra_rmb; 208 uint8_t reg_cksys_1_pmic_rmb; 209 uint8_t reg_cksys_1_srcclkena_mb; 210 uint8_t reg_cksys_1_vcore_rmb; 211 uint8_t reg_cksys_1_vrf18_rmb; 212 213 /* SPM_SRC_MASK_6 */ 214 uint8_t reg_cksys_2_apsrc_rmb; 215 uint8_t reg_cksys_2_ddren_rmb; 216 uint8_t reg_cksys_2_emi_rmb; 217 uint8_t reg_cksys_2_infra_rmb; 218 uint8_t reg_cksys_2_pmic_rmb; 219 uint8_t reg_cksys_2_srcclkena_mb; 220 uint8_t reg_cksys_2_vcore_rmb; 221 uint8_t reg_cksys_2_vrf18_rmb; 222 uint8_t reg_conn_apsrc_rmb; 223 uint8_t reg_conn_ddren_rmb; 224 uint8_t reg_conn_emi_rmb; 225 uint8_t reg_conn_infra_rmb; 226 uint8_t reg_conn_pmic_rmb; 227 uint8_t reg_conn_srcclkena_mb; 228 uint8_t reg_conn_srcclkenb_mb; 229 uint8_t reg_conn_vcore_rmb; 230 uint8_t reg_conn_vrf18_rmb; 231 uint8_t reg_corecfg_apsrc_rmb; 232 uint8_t reg_corecfg_ddren_rmb; 233 uint8_t reg_corecfg_emi_rmb; 234 uint8_t reg_corecfg_infra_rmb; 235 uint8_t reg_corecfg_pmic_rmb; 236 uint8_t reg_corecfg_srcclkena_mb; 237 uint8_t reg_corecfg_vcore_rmb; 238 uint8_t reg_corecfg_vrf18_rmb; 239 240 /* SPM_SRC_MASK_7 */ 241 uint8_t reg_cpueb_apsrc_rmb; 242 uint8_t reg_cpueb_ddren_rmb; 243 uint8_t reg_cpueb_emi_rmb; 244 uint8_t reg_cpueb_infra_rmb; 245 uint8_t reg_cpueb_pmic_rmb; 246 uint8_t reg_cpueb_srcclkena_mb; 247 uint8_t reg_cpueb_vcore_rmb; 248 uint8_t reg_cpueb_vrf18_rmb; 249 uint8_t reg_disp0_apsrc_rmb; 250 uint8_t reg_disp0_ddren_rmb; 251 uint8_t reg_disp0_emi_rmb; 252 uint8_t reg_disp0_infra_rmb; 253 uint8_t reg_disp0_pmic_rmb; 254 uint8_t reg_disp0_srcclkena_mb; 255 uint8_t reg_disp0_vrf18_rmb; 256 uint8_t reg_disp1_apsrc_rmb; 257 uint8_t reg_disp1_ddren_rmb; 258 uint8_t reg_disp1_emi_rmb; 259 uint8_t reg_disp1_infra_rmb; 260 uint8_t reg_disp1_pmic_rmb; 261 uint8_t reg_disp1_srcclkena_mb; 262 uint8_t reg_disp1_vrf18_rmb; 263 uint8_t reg_dpm_apsrc_rmb; 264 uint8_t reg_dpm_ddren_rmb; 265 266 /* SPM_SRC_MASK_8 */ 267 uint8_t reg_dpm_emi_rmb; 268 uint8_t reg_dpm_infra_rmb; 269 uint8_t reg_dpm_pmic_rmb; 270 uint8_t reg_dpm_srcclkena_mb; 271 uint8_t reg_dpm_vcore_rmb; 272 uint8_t reg_dpm_vrf18_rmb; 273 uint8_t reg_dpmaif_apsrc_rmb; 274 uint8_t reg_dpmaif_ddren_rmb; 275 uint8_t reg_dpmaif_emi_rmb; 276 uint8_t reg_dpmaif_infra_rmb; 277 uint8_t reg_dpmaif_pmic_rmb; 278 uint8_t reg_dpmaif_srcclkena_mb; 279 uint8_t reg_dpmaif_vcore_rmb; 280 uint8_t reg_dpmaif_vrf18_rmb; 281 282 /* SPM_SRC_MASK_9 */ 283 uint8_t reg_dvfsrc_level_rmb; 284 uint8_t reg_emisys_apsrc_rmb; 285 uint8_t reg_emisys_ddren_rmb; 286 uint8_t reg_emisys_emi_rmb; 287 uint8_t reg_emisys_infra_rmb; 288 uint8_t reg_emisys_pmic_rmb; 289 uint8_t reg_emisys_srcclkena_mb; 290 uint8_t reg_emisys_vcore_rmb; 291 uint8_t reg_emisys_vrf18_rmb; 292 uint8_t reg_gce_apsrc_rmb; 293 uint8_t reg_gce_ddren_rmb; 294 uint8_t reg_gce_emi_rmb; 295 uint8_t reg_gce_infra_rmb; 296 uint8_t reg_gce_pmic_rmb; 297 uint8_t reg_gce_srcclkena_mb; 298 uint8_t reg_gce_vcore_rmb; 299 uint8_t reg_gce_vrf18_rmb; 300 uint8_t reg_gpueb_apsrc_rmb; 301 uint8_t reg_gpueb_ddren_rmb; 302 uint8_t reg_gpueb_emi_rmb; 303 uint8_t reg_gpueb_infra_rmb; 304 uint8_t reg_gpueb_pmic_rmb; 305 uint8_t reg_gpueb_srcclkena_mb; 306 uint8_t reg_gpueb_vcore_rmb; 307 uint8_t reg_gpueb_vrf18_rmb; 308 uint8_t reg_hwccf_apsrc_rmb; 309 uint8_t reg_hwccf_ddren_rmb; 310 uint8_t reg_hwccf_emi_rmb; 311 uint8_t reg_hwccf_infra_rmb; 312 uint8_t reg_hwccf_pmic_rmb; 313 uint8_t reg_hwccf_srcclkena_mb; 314 uint8_t reg_hwccf_vcore_rmb; 315 316 /* SPM_SRC_MASK_10 */ 317 uint8_t reg_hwccf_vrf18_rmb; 318 uint8_t reg_img_apsrc_rmb; 319 uint8_t reg_img_ddren_rmb; 320 uint8_t reg_img_emi_rmb; 321 uint8_t reg_img_infra_rmb; 322 uint8_t reg_img_pmic_rmb; 323 uint8_t reg_img_srcclkena_mb; 324 uint8_t reg_img_vrf18_rmb; 325 uint8_t reg_infrasys_apsrc_rmb; 326 uint8_t reg_infrasys_ddren_rmb; 327 uint8_t reg_infrasys_emi_rmb; 328 uint8_t reg_infrasys_infra_rmb; 329 uint8_t reg_infrasys_pmic_rmb; 330 uint8_t reg_infrasys_srcclkena_mb; 331 uint8_t reg_infrasys_vcore_rmb; 332 uint8_t reg_infrasys_vrf18_rmb; 333 uint8_t reg_ipic_infra_rmb; 334 uint8_t reg_ipic_vrf18_rmb; 335 uint8_t reg_mcu_apsrc_rmb; 336 uint8_t reg_mcu_ddren_rmb; 337 uint8_t reg_mcu_emi_rmb; 338 uint8_t reg_mcu_infra_rmb; 339 uint8_t reg_mcu_pmic_rmb; 340 uint8_t reg_mcu_srcclkena_mb; 341 uint8_t reg_mcu_vcore_rmb; 342 uint8_t reg_mcu_vrf18_rmb; 343 uint8_t reg_md_apsrc_rmb; 344 uint8_t reg_md_ddren_rmb; 345 uint8_t reg_md_emi_rmb; 346 uint8_t reg_md_infra_rmb; 347 uint8_t reg_md_pmic_rmb; 348 uint8_t reg_md_srcclkena_mb; 349 350 /* SPM_SRC_MASK_11 */ 351 uint8_t reg_md_srcclkena1_mb; 352 uint8_t reg_md_vcore_rmb; 353 uint8_t reg_md_vrf18_rmb; 354 uint8_t reg_mm_proc_apsrc_rmb; 355 uint8_t reg_mm_proc_ddren_rmb; 356 uint8_t reg_mm_proc_emi_rmb; 357 uint8_t reg_mm_proc_infra_rmb; 358 uint8_t reg_mm_proc_pmic_rmb; 359 uint8_t reg_mm_proc_srcclkena_mb; 360 uint8_t reg_mm_proc_vcore_rmb; 361 uint8_t reg_mm_proc_vrf18_rmb; 362 uint8_t reg_mml0_apsrc_rmb; 363 uint8_t reg_mml0_ddren_rmb; 364 uint8_t reg_mml0_emi_rmb; 365 uint8_t reg_mml0_infra_rmb; 366 uint8_t reg_mml0_pmic_rmb; 367 uint8_t reg_mml0_srcclkena_mb; 368 uint8_t reg_mml0_vrf18_rmb; 369 uint8_t reg_mml1_apsrc_rmb; 370 uint8_t reg_mml1_ddren_rmb; 371 uint8_t reg_mml1_emi_rmb; 372 uint8_t reg_mml1_infra_rmb; 373 uint8_t reg_mml1_pmic_rmb; 374 uint8_t reg_mml1_srcclkena_mb; 375 uint8_t reg_mml1_vrf18_rmb; 376 uint8_t reg_ovl0_apsrc_rmb; 377 uint8_t reg_ovl0_ddren_rmb; 378 uint8_t reg_ovl0_emi_rmb; 379 uint8_t reg_ovl0_infra_rmb; 380 uint8_t reg_ovl0_pmic_rmb; 381 uint8_t reg_ovl0_srcclkena_mb; 382 uint8_t reg_ovl0_vrf18_rmb; 383 384 /* SPM_SRC_MASK_12 */ 385 uint8_t reg_ovl1_apsrc_rmb; 386 uint8_t reg_ovl1_ddren_rmb; 387 uint8_t reg_ovl1_emi_rmb; 388 uint8_t reg_ovl1_infra_rmb; 389 uint8_t reg_ovl1_pmic_rmb; 390 uint8_t reg_ovl1_srcclkena_mb; 391 uint8_t reg_ovl1_vrf18_rmb; 392 uint8_t reg_pcie0_apsrc_rmb; 393 uint8_t reg_pcie0_ddren_rmb; 394 uint8_t reg_pcie0_emi_rmb; 395 uint8_t reg_pcie0_infra_rmb; 396 uint8_t reg_pcie0_pmic_rmb; 397 uint8_t reg_pcie0_srcclkena_mb; 398 uint8_t reg_pcie0_vcore_rmb; 399 uint8_t reg_pcie0_vrf18_rmb; 400 uint8_t reg_pcie1_apsrc_rmb; 401 uint8_t reg_pcie1_ddren_rmb; 402 uint8_t reg_pcie1_emi_rmb; 403 uint8_t reg_pcie1_infra_rmb; 404 uint8_t reg_pcie1_pmic_rmb; 405 uint8_t reg_pcie1_srcclkena_mb; 406 uint8_t reg_pcie1_vcore_rmb; 407 uint8_t reg_pcie1_vrf18_rmb; 408 uint8_t reg_perisys_apsrc_rmb; 409 uint8_t reg_perisys_ddren_rmb; 410 uint8_t reg_perisys_emi_rmb; 411 uint8_t reg_perisys_infra_rmb; 412 uint8_t reg_perisys_pmic_rmb; 413 uint8_t reg_perisys_srcclkena_mb; 414 uint8_t reg_perisys_vcore_rmb; 415 uint8_t reg_perisys_vrf18_rmb; 416 uint8_t reg_pmsr_apsrc_rmb; 417 418 /* SPM_SRC_MASK_13 */ 419 uint8_t reg_pmsr_ddren_rmb; 420 uint8_t reg_pmsr_emi_rmb; 421 uint8_t reg_pmsr_infra_rmb; 422 uint8_t reg_pmsr_pmic_rmb; 423 uint8_t reg_pmsr_srcclkena_mb; 424 uint8_t reg_pmsr_vcore_rmb; 425 uint8_t reg_pmsr_vrf18_rmb; 426 uint8_t reg_scp_apsrc_rmb; 427 uint8_t reg_scp_ddren_rmb; 428 uint8_t reg_scp_emi_rmb; 429 uint8_t reg_scp_infra_rmb; 430 uint8_t reg_scp_pmic_rmb; 431 uint8_t reg_scp_srcclkena_mb; 432 uint8_t reg_scp_vcore_rmb; 433 uint8_t reg_scp_vrf18_rmb; 434 uint8_t reg_spu_hwr_apsrc_rmb; 435 uint8_t reg_spu_hwr_ddren_rmb; 436 uint8_t reg_spu_hwr_emi_rmb; 437 uint8_t reg_spu_hwr_infra_rmb; 438 uint8_t reg_spu_hwr_pmic_rmb; 439 uint8_t reg_spu_hwr_srcclkena_mb; 440 uint8_t reg_spu_hwr_vcore_rmb; 441 uint8_t reg_spu_hwr_vrf18_rmb; 442 uint8_t reg_spu_ise_apsrc_rmb; 443 uint8_t reg_spu_ise_ddren_rmb; 444 uint8_t reg_spu_ise_emi_rmb; 445 uint8_t reg_spu_ise_infra_rmb; 446 uint8_t reg_spu_ise_pmic_rmb; 447 uint8_t reg_spu_ise_srcclkena_mb; 448 uint8_t reg_spu_ise_vcore_rmb; 449 uint8_t reg_spu_ise_vrf18_rmb; 450 451 /* SPM_SRC_MASK_14 */ 452 uint8_t reg_srcclkeni_infra_rmb; 453 uint8_t reg_srcclkeni_pmic_rmb; 454 uint8_t reg_srcclkeni_srcclkena_mb; 455 uint8_t reg_srcclkeni_vcore_rmb; 456 uint8_t reg_sspm_apsrc_rmb; 457 uint8_t reg_sspm_ddren_rmb; 458 uint8_t reg_sspm_emi_rmb; 459 uint8_t reg_sspm_infra_rmb; 460 uint8_t reg_sspm_pmic_rmb; 461 uint8_t reg_sspm_srcclkena_mb; 462 uint8_t reg_sspm_vrf18_rmb; 463 uint8_t reg_ssrsys_apsrc_rmb; 464 uint8_t reg_ssrsys_ddren_rmb; 465 uint8_t reg_ssrsys_emi_rmb; 466 uint8_t reg_ssrsys_infra_rmb; 467 uint8_t reg_ssrsys_pmic_rmb; 468 uint8_t reg_ssrsys_srcclkena_mb; 469 uint8_t reg_ssrsys_vcore_rmb; 470 uint8_t reg_ssrsys_vrf18_rmb; 471 uint8_t reg_ssusb_apsrc_rmb; 472 uint8_t reg_ssusb_ddren_rmb; 473 uint8_t reg_ssusb_emi_rmb; 474 uint8_t reg_ssusb_infra_rmb; 475 uint8_t reg_ssusb_pmic_rmb; 476 uint8_t reg_ssusb_srcclkena_mb; 477 uint8_t reg_ssusb_vcore_rmb; 478 uint8_t reg_ssusb_vrf18_rmb; 479 uint8_t reg_uart_hub_infra_rmb; 480 481 /* SPM_SRC_MASK_15 */ 482 uint8_t reg_uart_hub_pmic_rmb; 483 uint8_t reg_uart_hub_srcclkena_mb; 484 uint8_t reg_uart_hub_vcore_rmb; 485 uint8_t reg_uart_hub_vrf18_rmb; 486 uint8_t reg_ufs_apsrc_rmb; 487 uint8_t reg_ufs_ddren_rmb; 488 uint8_t reg_ufs_emi_rmb; 489 uint8_t reg_ufs_infra_rmb; 490 uint8_t reg_ufs_pmic_rmb; 491 uint8_t reg_ufs_srcclkena_mb; 492 uint8_t reg_ufs_vcore_rmb; 493 uint8_t reg_ufs_vrf18_rmb; 494 uint8_t reg_vdec_apsrc_rmb; 495 uint8_t reg_vdec_ddren_rmb; 496 uint8_t reg_vdec_emi_rmb; 497 uint8_t reg_vdec_infra_rmb; 498 uint8_t reg_vdec_pmic_rmb; 499 uint8_t reg_vdec_srcclkena_mb; 500 uint8_t reg_vdec_vrf18_rmb; 501 uint8_t reg_venc_apsrc_rmb; 502 uint8_t reg_venc_ddren_rmb; 503 uint8_t reg_venc_emi_rmb; 504 uint8_t reg_venc_infra_rmb; 505 uint8_t reg_venc_pmic_rmb; 506 uint8_t reg_venc_srcclkena_mb; 507 uint8_t reg_venc_vrf18_rmb; 508 uint8_t reg_vlpcfg_apsrc_rmb; 509 uint8_t reg_vlpcfg_ddren_rmb; 510 uint8_t reg_vlpcfg_emi_rmb; 511 uint8_t reg_vlpcfg_infra_rmb; 512 uint8_t reg_vlpcfg_pmic_rmb; 513 uint8_t reg_vlpcfg_srcclkena_mb; 514 515 /* SPM_SRC_MASK_16 */ 516 uint8_t reg_vlpcfg_vcore_rmb; 517 uint8_t reg_vlpcfg_vrf18_rmb; 518 uint8_t reg_vlpcfg1_apsrc_rmb; 519 uint8_t reg_vlpcfg1_ddren_rmb; 520 uint8_t reg_vlpcfg1_emi_rmb; 521 uint8_t reg_vlpcfg1_infra_rmb; 522 uint8_t reg_vlpcfg1_pmic_rmb; 523 uint8_t reg_vlpcfg1_srcclkena_mb; 524 uint8_t reg_vlpcfg1_vcore_rmb; 525 uint8_t reg_vlpcfg1_vrf18_rmb; 526 527 /* SPM_EVENT_CON_MISC */ 528 uint8_t reg_srcclken_fast_resp; 529 uint8_t reg_csyspwrup_ack_mask; 530 531 /* SPM_SRC_MASK_17 */ 532 uint32_t reg_spm_sw_vcore_rmb; 533 uint32_t reg_spm_sw_pmic_rmb; 534 535 /* SPM_SRC_MASK_18 */ 536 uint32_t reg_spm_sw_srcclkena_mb; 537 538 /* SPM_WAKE_MASK*/ 539 uint32_t reg_wake_mask; 540 541 /* SPM_WAKEUP_EVENT_EXT_MASK */ 542 uint32_t reg_ext_wake_mask; 543 }; 544 545 enum pwr_ctrl_enum { 546 PW_PCM_FLAGS, 547 PW_PCM_FLAGS_CUST, 548 PW_PCM_FLAGS_CUST_SET, 549 PW_PCM_FLAGS_CUST_CLR, 550 PW_PCM_FLAGS1, 551 PW_PCM_FLAGS1_CUST, 552 PW_PCM_FLAGS1_CUST_SET, 553 PW_PCM_FLAGS1_CUST_CLR, 554 PW_TIMER_VAL, 555 PW_TIMER_VAL_CUST, 556 PW_TIMER_VAL_RAMP_EN, 557 PW_TIMER_VAL_RAMP_EN_SEC, 558 PW_WAKE_SRC, 559 PW_WAKE_SRC_CUST, 560 PW_WAKELOCK_TIMER_VAL, 561 PW_WDT_DISABLE, 562 563 /* SPM_SRC_REQ */ 564 PW_REG_SPM_ADSP_MAILBOX_REQ, 565 PW_REG_SPM_APSRC_REQ, 566 PW_REG_SPM_DDREN_REQ, 567 PW_REG_SPM_DVFS_REQ, 568 PW_REG_SPM_EMI_REQ, 569 PW_REG_SPM_F26M_REQ, 570 PW_REG_SPM_INFRA_REQ, 571 PW_REG_SPM_PMIC_REQ, 572 PW_REG_SPM_SCP_MAILBOX_REQ, 573 PW_REG_SPM_SSPM_MAILBOX_REQ, 574 PW_REG_SPM_SW_MAILBOX_REQ, 575 PW_REG_SPM_VCORE_REQ, 576 PW_REG_SPM_VRF18_REQ, 577 578 /* SPM_SRC_MASK_0 */ 579 PW_REG_APIFR_APSRC_RMB, 580 PW_REG_APIFR_DDREN_RMB, 581 PW_REG_APIFR_EMI_RMB, 582 PW_REG_APIFR_INFRA_RMB, 583 PW_REG_APIFR_PMIC_RMB, 584 PW_REG_APIFR_SRCCLKENA_MB, 585 PW_REG_APIFR_VCORE_RMB, 586 PW_REG_APIFR_VRF18_RMB, 587 PW_REG_APU_APSRC_RMB, 588 PW_REG_APU_DDREN_RMB, 589 PW_REG_APU_EMI_RMB, 590 PW_REG_APU_INFRA_RMB, 591 PW_REG_APU_PMIC_RMB, 592 PW_REG_APU_SRCCLKENA_MB, 593 PW_REG_APU_VCORE_RMB, 594 PW_REG_APU_VRF18_RMB, 595 PW_REG_AUDIO_APSRC_RMB, 596 PW_REG_AUDIO_DDREN_RMB, 597 PW_REG_AUDIO_EMI_RMB, 598 PW_REG_AUDIO_INFRA_RMB, 599 PW_REG_AUDIO_PMIC_RMB, 600 PW_REG_AUDIO_SRCCLKENA_MB, 601 PW_REG_AUDIO_VCORE_RMB, 602 PW_REG_AUDIO_VRF18_RMB, 603 604 /* SPM_SRC_MASK_1 */ 605 PW_REG_AUDIO_DSP_APSRC_RMB, 606 PW_REG_AUDIO_DSP_DDREN_RMB, 607 PW_REG_AUDIO_DSP_EMI_RMB, 608 PW_REG_AUDIO_DSP_INFRA_RMB, 609 PW_REG_AUDIO_DSP_PMIC_RMB, 610 PW_REG_AUDIO_DSP_SRCCLKENA_MB, 611 PW_REG_AUDIO_DSP_VCORE_RMB, 612 PW_REG_AUDIO_DSP_VRF18_RMB, 613 PW_REG_CAM_APSRC_RMB, 614 PW_REG_CAM_DDREN_RMB, 615 PW_REG_CAM_EMI_RMB, 616 PW_REG_CAM_INFRA_RMB, 617 PW_REG_CAM_PMIC_RMB, 618 PW_REG_CAM_SRCCLKENA_MB, 619 PW_REG_CAM_VRF18_RMB, 620 PW_REG_CCIF_APSRC_RMB, 621 622 /* SPM_SRC_MASK_2 */ 623 PW_REG_CCIF_EMI_RMB, 624 PW_REG_CCIF_INFRA_RMB, 625 626 /* SPM_SRC_MASK_3 */ 627 PW_REG_CCIF_PMIC_RMB, 628 PW_REG_CCIF_SRCCLKENA_MB, 629 630 /* SPM_SRC_MASK_4 */ 631 PW_REG_CCIF_VCORE_RMB, 632 PW_REG_CCIF_VRF18_RMB, 633 PW_REG_CCU_APSRC_RMB, 634 PW_REG_CCU_DDREN_RMB, 635 PW_REG_CCU_EMI_RMB, 636 PW_REG_CCU_INFRA_RMB, 637 PW_REG_CCU_PMIC_RMB, 638 PW_REG_CCU_SRCCLKENA_MB, 639 PW_REG_CCU_VRF18_RMB, 640 PW_REG_CG_CHECK_APSRC_RMB, 641 642 /* SPM_SRC_MASK_5 */ 643 PW_REG_CG_CHECK_DDREN_RMB, 644 PW_REG_CG_CHECK_EMI_RMB, 645 PW_REG_CG_CHECK_INFRA_RMB, 646 PW_REG_CG_CHECK_PMIC_RMB, 647 PW_REG_CG_CHECK_SRCCLKENA_MB, 648 PW_REG_CG_CHECK_VCORE_RMB, 649 PW_REG_CG_CHECK_VRF18_RMB, 650 PW_REG_CKSYS_APSRC_RMB, 651 PW_REG_CKSYS_DDREN_RMB, 652 PW_REG_CKSYS_EMI_RMB, 653 PW_REG_CKSYS_INFRA_RMB, 654 PW_REG_CKSYS_PMIC_RMB, 655 PW_REG_CKSYS_SRCCLKENA_MB, 656 PW_REG_CKSYS_VCORE_RMB, 657 PW_REG_CKSYS_VRF18_RMB, 658 PW_REG_CKSYS_1_APSRC_RMB, 659 PW_REG_CKSYS_1_DDREN_RMB, 660 PW_REG_CKSYS_1_EMI_RMB, 661 PW_REG_CKSYS_1_INFRA_RMB, 662 PW_REG_CKSYS_1_PMIC_RMB, 663 PW_REG_CKSYS_1_SRCCLKENA_MB, 664 PW_REG_CKSYS_1_VCORE_RMB, 665 PW_REG_CKSYS_1_VRF18_RMB, 666 667 /* SPM_SRC_MASK_6 */ 668 PW_REG_CKSYS_2_APSRC_RMB, 669 PW_REG_CKSYS_2_DDREN_RMB, 670 PW_REG_CKSYS_2_EMI_RMB, 671 PW_REG_CKSYS_2_INFRA_RMB, 672 PW_REG_CKSYS_2_PMIC_RMB, 673 PW_REG_CKSYS_2_SRCCLKENA_MB, 674 PW_REG_CKSYS_2_VCORE_RMB, 675 PW_REG_CKSYS_2_VRF18_RMB, 676 PW_REG_CONN_APSRC_RMB, 677 PW_REG_CONN_DDREN_RMB, 678 PW_REG_CONN_EMI_RMB, 679 PW_REG_CONN_INFRA_RMB, 680 PW_REG_CONN_PMIC_RMB, 681 PW_REG_CONN_SRCCLKENA_MB, 682 PW_REG_CONN_SRCCLKENB_MB, 683 PW_REG_CONN_VCORE_RMB, 684 PW_REG_CONN_VRF18_RMB, 685 PW_REG_CORECFG_APSRC_RMB, 686 PW_REG_CORECFG_DDREN_RMB, 687 PW_REG_CORECFG_EMI_RMB, 688 PW_REG_CORECFG_INFRA_RMB, 689 PW_REG_CORECFG_PMIC_RMB, 690 PW_REG_CORECFG_SRCCLKENA_MB, 691 PW_REG_CORECFG_VCORE_RMB, 692 PW_REG_CORECFG_VRF18_RMB, 693 694 /* SPM_SRC_MASK_7 */ 695 PW_REG_CPUEB_APSRC_RMB, 696 PW_REG_CPUEB_DDREN_RMB, 697 PW_REG_CPUEB_EMI_RMB, 698 PW_REG_CPUEB_INFRA_RMB, 699 PW_REG_CPUEB_PMIC_RMB, 700 PW_REG_CPUEB_SRCCLKENA_MB, 701 PW_REG_CPUEB_VCORE_RMB, 702 PW_REG_CPUEB_VRF18_RMB, 703 PW_REG_DISP0_APSRC_RMB, 704 PW_REG_DISP0_DDREN_RMB, 705 PW_REG_DISP0_EMI_RMB, 706 PW_REG_DISP0_INFRA_RMB, 707 PW_REG_DISP0_PMIC_RMB, 708 PW_REG_DISP0_SRCCLKENA_MB, 709 PW_REG_DISP0_VRF18_RMB, 710 PW_REG_DISP1_APSRC_RMB, 711 PW_REG_DISP1_DDREN_RMB, 712 PW_REG_DISP1_EMI_RMB, 713 PW_REG_DISP1_INFRA_RMB, 714 PW_REG_DISP1_PMIC_RMB, 715 PW_REG_DISP1_SRCCLKENA_MB, 716 PW_REG_DISP1_VRF18_RMB, 717 PW_REG_DPM_APSRC_RMB, 718 PW_REG_DPM_DDREN_RMB, 719 720 /* SPM_SRC_MASK_8 */ 721 PW_REG_DPM_EMI_RMB, 722 PW_REG_DPM_INFRA_RMB, 723 PW_REG_DPM_PMIC_RMB, 724 PW_REG_DPM_SRCCLKENA_MB, 725 PW_REG_DPM_VCORE_RMB, 726 PW_REG_DPM_VRF18_RMB, 727 PW_REG_DPMAIF_APSRC_RMB, 728 PW_REG_DPMAIF_DDREN_RMB, 729 PW_REG_DPMAIF_EMI_RMB, 730 PW_REG_DPMAIF_INFRA_RMB, 731 PW_REG_DPMAIF_PMIC_RMB, 732 PW_REG_DPMAIF_SRCCLKENA_MB, 733 PW_REG_DPMAIF_VCORE_RMB, 734 PW_REG_DPMAIF_VRF18_RMB, 735 736 /* SPM_SRC_MASK_9 */ 737 PW_REG_DVFSRC_LEVEL_RMB, 738 PW_REG_EMISYS_APSRC_RMB, 739 PW_REG_EMISYS_DDREN_RMB, 740 PW_REG_EMISYS_EMI_RMB, 741 PW_REG_EMISYS_INFRA_RMB, 742 PW_REG_EMISYS_PMIC_RMB, 743 PW_REG_EMISYS_SRCCLKENA_MB, 744 PW_REG_EMISYS_VCORE_RMB, 745 PW_REG_EMISYS_VRF18_RMB, 746 PW_REG_GCE_APSRC_RMB, 747 PW_REG_GCE_DDREN_RMB, 748 PW_REG_GCE_EMI_RMB, 749 PW_REG_GCE_INFRA_RMB, 750 PW_REG_GCE_PMIC_RMB, 751 PW_REG_GCE_SRCCLKENA_MB, 752 PW_REG_GCE_VCORE_RMB, 753 PW_REG_GCE_VRF18_RMB, 754 PW_REG_GPUEB_APSRC_RMB, 755 PW_REG_GPUEB_DDREN_RMB, 756 PW_REG_GPUEB_EMI_RMB, 757 PW_REG_GPUEB_INFRA_RMB, 758 PW_REG_GPUEB_PMIC_RMB, 759 PW_REG_GPUEB_SRCCLKENA_MB, 760 PW_REG_GPUEB_VCORE_RMB, 761 PW_REG_GPUEB_VRF18_RMB, 762 PW_REG_HWCCF_APSRC_RMB, 763 PW_REG_HWCCF_DDREN_RMB, 764 PW_REG_HWCCF_EMI_RMB, 765 PW_REG_HWCCF_INFRA_RMB, 766 PW_REG_HWCCF_PMIC_RMB, 767 PW_REG_HWCCF_SRCCLKENA_MB, 768 PW_REG_HWCCF_VCORE_RMB, 769 770 /* SPM_SRC_MASK_10 */ 771 PW_REG_HWCCF_VRF18_RMB, 772 PW_REG_IMG_APSRC_RMB, 773 PW_REG_IMG_DDREN_RMB, 774 PW_REG_IMG_EMI_RMB, 775 PW_REG_IMG_INFRA_RMB, 776 PW_REG_IMG_PMIC_RMB, 777 PW_REG_IMG_SRCCLKENA_MB, 778 PW_REG_IMG_VRF18_RMB, 779 PW_REG_INFRASYS_APSRC_RMB, 780 PW_REG_INFRASYS_DDREN_RMB, 781 PW_REG_INFRASYS_EMI_RMB, 782 PW_REG_INFRASYS_INFRA_RMB, 783 PW_REG_INFRASYS_PMIC_RMB, 784 PW_REG_INFRASYS_SRCCLKENA_MB, 785 PW_REG_INFRASYS_VCORE_RMB, 786 PW_REG_INFRASYS_VRF18_RMB, 787 PW_REG_IPIC_INFRA_RMB, 788 PW_REG_IPIC_VRF18_RMB, 789 PW_REG_MCU_APSRC_RMB, 790 PW_REG_MCU_DDREN_RMB, 791 PW_REG_MCU_EMI_RMB, 792 PW_REG_MCU_INFRA_RMB, 793 PW_REG_MCU_PMIC_RMB, 794 PW_REG_MCU_SRCCLKENA_MB, 795 PW_REG_MCU_VCORE_RMB, 796 PW_REG_MCU_VRF18_RMB, 797 PW_REG_MD_APSRC_RMB, 798 PW_REG_MD_DDREN_RMB, 799 PW_REG_MD_EMI_RMB, 800 PW_REG_MD_INFRA_RMB, 801 PW_REG_MD_PMIC_RMB, 802 PW_REG_MD_SRCCLKENA_MB, 803 804 /* SPM_SRC_MASK_11 */ 805 PW_REG_MD_SRCCLKENA1_MB, 806 PW_REG_MD_VCORE_RMB, 807 PW_REG_MD_VRF18_RMB, 808 PW_REG_MM_PROC_APSRC_RMB, 809 PW_REG_MM_PROC_DDREN_RMB, 810 PW_REG_MM_PROC_EMI_RMB, 811 PW_REG_MM_PROC_INFRA_RMB, 812 PW_REG_MM_PROC_PMIC_RMB, 813 PW_REG_MM_PROC_SRCCLKENA_MB, 814 PW_REG_MM_PROC_VCORE_RMB, 815 PW_REG_MM_PROC_VRF18_RMB, 816 PW_REG_MML0_APSRC_RMB, 817 PW_REG_MML0_DDREN_RMB, 818 PW_REG_MML0_EMI_RMB, 819 PW_REG_MML0_INFRA_RMB, 820 PW_REG_MML0_PMIC_RMB, 821 PW_REG_MML0_SRCCLKENA_MB, 822 PW_REG_MML0_VRF18_RMB, 823 PW_REG_MML1_APSRC_RMB, 824 PW_REG_MML1_DDREN_RMB, 825 PW_REG_MML1_EMI_RMB, 826 PW_REG_MML1_INFRA_RMB, 827 PW_REG_MML1_PMIC_RMB, 828 PW_REG_MML1_SRCCLKENA_MB, 829 PW_REG_MML1_VRF18_RMB, 830 PW_REG_OVL0_APSRC_RMB, 831 PW_REG_OVL0_DDREN_RMB, 832 PW_REG_OVL0_EMI_RMB, 833 PW_REG_OVL0_INFRA_RMB, 834 PW_REG_OVL0_PMIC_RMB, 835 PW_REG_OVL0_SRCCLKENA_MB, 836 PW_REG_OVL0_VRF18_RMB, 837 838 /* SPM_SRC_MASK_12 */ 839 PW_REG_OVL1_APSRC_RMB, 840 PW_REG_OVL1_DDREN_RMB, 841 PW_REG_OVL1_EMI_RMB, 842 PW_REG_OVL1_INFRA_RMB, 843 PW_REG_OVL1_PMIC_RMB, 844 PW_REG_OVL1_SRCCLKENA_MB, 845 PW_REG_OVL1_VRF18_RMB, 846 PW_REG_PCIE0_APSRC_RMB, 847 PW_REG_PCIE0_DDREN_RMB, 848 PW_REG_PCIE0_EMI_RMB, 849 PW_REG_PCIE0_INFRA_RMB, 850 PW_REG_PCIE0_PMIC_RMB, 851 PW_REG_PCIE0_SRCCLKENA_MB, 852 PW_REG_PCIE0_VCORE_RMB, 853 PW_REG_PCIE0_VRF18_RMB, 854 PW_REG_PCIE1_APSRC_RMB, 855 PW_REG_PCIE1_DDREN_RMB, 856 PW_REG_PCIE1_EMI_RMB, 857 PW_REG_PCIE1_INFRA_RMB, 858 PW_REG_PCIE1_PMIC_RMB, 859 PW_REG_PCIE1_SRCCLKENA_MB, 860 PW_REG_PCIE1_VCORE_RMB, 861 PW_REG_PCIE1_VRF18_RMB, 862 PW_REG_PERISYS_APSRC_RMB, 863 PW_REG_PERISYS_DDREN_RMB, 864 PW_REG_PERISYS_EMI_RMB, 865 PW_REG_PERISYS_INFRA_RMB, 866 PW_REG_PERISYS_PMIC_RMB, 867 PW_REG_PERISYS_SRCCLKENA_MB, 868 PW_REG_PERISYS_VCORE_RMB, 869 PW_REG_PERISYS_VRF18_RMB, 870 PW_REG_PMSR_APSRC_RMB, 871 872 /* SPM_SRC_MASK_13 */ 873 PW_REG_PMSR_DDREN_RMB, 874 PW_REG_PMSR_EMI_RMB, 875 PW_REG_PMSR_INFRA_RMB, 876 PW_REG_PMSR_PMIC_RMB, 877 PW_REG_PMSR_SRCCLKENA_MB, 878 PW_REG_PMSR_VCORE_RMB, 879 PW_REG_PMSR_VRF18_RMB, 880 PW_REG_SCP_APSRC_RMB, 881 PW_REG_SCP_DDREN_RMB, 882 PW_REG_SCP_EMI_RMB, 883 PW_REG_SCP_INFRA_RMB, 884 PW_REG_SCP_PMIC_RMB, 885 PW_REG_SCP_SRCCLKENA_MB, 886 PW_REG_SCP_VCORE_RMB, 887 PW_REG_SCP_VRF18_RMB, 888 PW_REG_SPU_HWR_APSRC_RMB, 889 PW_REG_SPU_HWR_DDREN_RMB, 890 PW_REG_SPU_HWR_EMI_RMB, 891 PW_REG_SPU_HWR_INFRA_RMB, 892 PW_REG_SPU_HWR_PMIC_RMB, 893 PW_REG_SPU_HWR_SRCCLKENA_MB, 894 PW_REG_SPU_HWR_VCORE_RMB, 895 PW_REG_SPU_HWR_VRF18_RMB, 896 PW_REG_SPU_ISE_APSRC_RMB, 897 PW_REG_SPU_ISE_DDREN_RMB, 898 PW_REG_SPU_ISE_EMI_RMB, 899 PW_REG_SPU_ISE_INFRA_RMB, 900 PW_REG_SPU_ISE_PMIC_RMB, 901 PW_REG_SPU_ISE_SRCCLKENA_MB, 902 PW_REG_SPU_ISE_VCORE_RMB, 903 PW_REG_SPU_ISE_VRF18_RMB, 904 905 /* SPM_SRC_MASK_14 */ 906 PW_REG_SRCCLKENI_INFRA_RMB, 907 PW_REG_SRCCLKENI_PMIC_RMB, 908 PW_REG_SRCCLKENI_SRCCLKENA_MB, 909 PW_REG_SRCCLKENI_VCORE_RMB, 910 PW_REG_SSPM_APSRC_RMB, 911 PW_REG_SSPM_DDREN_RMB, 912 PW_REG_SSPM_EMI_RMB, 913 PW_REG_SSPM_INFRA_RMB, 914 PW_REG_SSPM_PMIC_RMB, 915 PW_REG_SSPM_SRCCLKENA_MB, 916 PW_REG_SSPM_VRF18_RMB, 917 PW_REG_SSRSYS_APSRC_RMB, 918 PW_REG_SSRSYS_DDREN_RMB, 919 PW_REG_SSRSYS_EMI_RMB, 920 PW_REG_SSRSYS_INFRA_RMB, 921 PW_REG_SSRSYS_PMIC_RMB, 922 PW_REG_SSRSYS_SRCCLKENA_MB, 923 PW_REG_SSRSYS_VCORE_RMB, 924 PW_REG_SSRSYS_VRF18_RMB, 925 PW_REG_SSUSB_APSRC_RMB, 926 PW_REG_SSUSB_DDREN_RMB, 927 PW_REG_SSUSB_EMI_RMB, 928 PW_REG_SSUSB_INFRA_RMB, 929 PW_REG_SSUSB_PMIC_RMB, 930 PW_REG_SSUSB_SRCCLKENA_MB, 931 PW_REG_SSUSB_VCORE_RMB, 932 PW_REG_SSUSB_VRF18_RMB, 933 PW_REG_UART_HUB_INFRA_RMB, 934 935 /* SPM_SRC_MASK_15 */ 936 PW_REG_UART_HUB_PMIC_RMB, 937 PW_REG_UART_HUB_SRCCLKENA_MB, 938 PW_REG_UART_HUB_VCORE_RMB, 939 PW_REG_UART_HUB_VRF18_RMB, 940 PW_REG_UFS_APSRC_RMB, 941 PW_REG_UFS_DDREN_RMB, 942 PW_REG_UFS_EMI_RMB, 943 PW_REG_UFS_INFRA_RMB, 944 PW_REG_UFS_PMIC_RMB, 945 PW_REG_UFS_SRCCLKENA_MB, 946 PW_REG_UFS_VCORE_RMB, 947 PW_REG_UFS_VRF18_RMB, 948 PW_REG_VDEC_APSRC_RMB, 949 PW_REG_VDEC_DDREN_RMB, 950 PW_REG_VDEC_EMI_RMB, 951 PW_REG_VDEC_INFRA_RMB, 952 PW_REG_VDEC_PMIC_RMB, 953 PW_REG_VDEC_SRCCLKENA_MB, 954 PW_REG_VDEC_VRF18_RMB, 955 PW_REG_VENC_APSRC_RMB, 956 PW_REG_VENC_DDREN_RMB, 957 PW_REG_VENC_EMI_RMB, 958 PW_REG_VENC_INFRA_RMB, 959 PW_REG_VENC_PMIC_RMB, 960 PW_REG_VENC_SRCCLKENA_MB, 961 PW_REG_VENC_VRF18_RMB, 962 PW_REG_VLPCFG_APSRC_RMB, 963 PW_REG_VLPCFG_DDREN_RMB, 964 PW_REG_VLPCFG_EMI_RMB, 965 PW_REG_VLPCFG_INFRA_RMB, 966 PW_REG_VLPCFG_PMIC_RMB, 967 PW_REG_VLPCFG_SRCCLKENA_MB, 968 969 /* SPM_SRC_MASK_16 */ 970 PW_REG_VLPCFG_VCORE_RMB, 971 PW_REG_VLPCFG_VRF18_RMB, 972 PW_REG_VLPCFG1_APSRC_RMB, 973 PW_REG_VLPCFG1_DDREN_RMB, 974 PW_REG_VLPCFG1_EMI_RMB, 975 PW_REG_VLPCFG1_INFRA_RMB, 976 PW_REG_VLPCFG1_PMIC_RMB, 977 PW_REG_VLPCFG1_SRCCLKENA_MB, 978 PW_REG_VLPCFG1_VCORE_RMB, 979 PW_REG_VLPCFG1_VRF18_RMB, 980 981 /* SPM_EVENT_CON_MISC */ 982 PW_REG_SRCCLKEN_FAST_RESP, 983 PW_REG_CSYSPWRUP_ACK_MASK, 984 985 /* SPM_SRC_MASK_17 */ 986 PW_REG_SPM_SW_VCORE_RMB, 987 PW_REG_SPM_SW_PMIC_RMB, 988 989 /* SPM_SRC_MASK_18 */ 990 PW_REG_SPM_SW_SRCCLKENA_MB, 991 992 /* SPM_WAKE_MASK*/ 993 PW_REG_WAKEUP_EVENT_MASK, 994 995 /* SPM_WAKEUP_EVENT_EXT_MASK */ 996 PW_REG_EXT_WAKEUP_EVENT_MASK, 997 998 PW_MAX_COUNT, 999 }; 1000 1001 /* 1002 * HW_TARG_GROUP_SEL_3 : 3b'1 (pcm_reg_13) 1003 * HW_TARG_SIGNAL_SEL_3 : 5b'10101 1004 * HW_TRIG_GROUP_SEL_3 : 3'b100 (trig_reserve) 1005 * HW_TRIG_SIGNAL_SEL_3 : 5'b1100 (trig_reserve[24]=sc_hw_s1_req) 1006 */ 1007 #define SPM_ACK_CHK_3_SEL_HW_S1 (0x00350098) 1008 #define SPM_ACK_CHK_3_HW_S1_CNT (1) 1009 1010 #define SPM_ACK_CHK_3_CON_HW_MODE_TRIG (0x800) 1011 /* BIT[0]: SW_EN, BIT[4]: STA_EN, BIT[8]: HW_EN */ 1012 #define SPM_ACK_CHK_3_CON_EN (0x110) 1013 #define SPM_ACK_CHK_3_CON_CLR_ALL (0x2) 1014 /* BIT[15]: RESULT */ 1015 #define SPM_ACK_CHK_3_CON_RESULT (0x8000) 1016 1017 struct wake_status_trace_comm { 1018 uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */ 1019 uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */ 1020 uint32_t timer_out; /* SPM_SW_RSV_6*/ 1021 uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */ 1022 uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */ 1023 uint32_t r12; /* SPM_SW_RSV_0 */ 1024 uint32_t r13; /* PCM_REG13_DATA */ 1025 uint32_t req_sta0; /* SRC_REQ_STA_0 */ 1026 uint32_t req_sta1; /* SRC_REQ_STA_1 */ 1027 uint32_t req_sta2; /* SRC_REQ_STA_2 */ 1028 uint32_t req_sta3; /* SRC_REQ_STA_3 */ 1029 uint32_t req_sta4; /* SRC_REQ_STA_4 */ 1030 uint32_t req_sta5; /* SRC_REQ_STA_5 */ 1031 uint32_t req_sta6; /* SRC_REQ_STA_6 */ 1032 uint32_t req_sta7; /* SRC_REQ_STA_7 */ 1033 uint32_t req_sta8; /* SRC_REQ_STA_8 */ 1034 uint32_t req_sta9; /* SRC_REQ_STA_9 */ 1035 uint32_t req_sta10; /* SRC_REQ_STA_10 */ 1036 uint32_t req_sta11; /* SRC_REQ_STA_11 */ 1037 uint32_t req_sta12; /* SRC_REQ_STA_12 */ 1038 uint32_t req_sta13; /* SRC_REQ_STA_13 */ 1039 uint32_t req_sta14; /* SRC_REQ_STA_14 */ 1040 uint32_t req_sta15; /* SRC_REQ_STA_15 */ 1041 uint32_t req_sta16; /* SRC_REQ_STA_16 */ 1042 uint32_t raw_sta; /* SPM_WAKEUP_STA */ 1043 uint32_t times_h; /* Timestamp high bits */ 1044 uint32_t times_l; /* Timestamp low bits */ 1045 uint32_t resumetime; /* Timestamp low bits */ 1046 }; 1047 1048 struct wake_status_trace { 1049 struct wake_status_trace_comm comm; 1050 /* Add suspend or idle part bellow */ 1051 }; 1052 1053 struct wake_status { 1054 struct wake_status_trace tr; 1055 uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */ 1056 uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */ 1057 uint32_t md32pcm_wakeup_sta; /* MD32PCM_WAKEUP_STA */ 1058 uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */ 1059 uint32_t wake_misc; /* SPM_SW_RSV_5 */ 1060 uint32_t sw_flag0; /* SPM_SW_FLAG_0 */ 1061 uint32_t sw_flag1; /* SPM_SW_FLAG_1 */ 1062 uint32_t isr; /* SPM_IRQ_STA */ 1063 uint32_t log_index; 1064 uint32_t is_abort; 1065 }; 1066 1067 struct spm_lp_scen { 1068 struct pcm_desc *pcmdesc; 1069 struct pwr_ctrl *pwrctrl; 1070 struct dbg_ctrl *dbgctrl; 1071 struct spm_lp_stat *lpstat; 1072 }; 1073 1074 extern struct spm_lp_scen __spm_vcorefs; 1075 typedef uint32_t u32; 1076 1077 void __spm_init_pcm_register(void); /* init r0 and r7 */ 1078 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl, 1079 uint32_t resource_usage); 1080 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); 1081 void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl); 1082 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl); 1083 void __spm_send_cpu_wakeup_event(void); 1084 1085 void __spm_get_wakeup_status(struct wake_status *wakesta, 1086 uint32_t ext_status); 1087 void __spm_clean_after_wakeup(void); 1088 wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta); 1089 1090 void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl, 1091 const struct pwr_ctrl *src_pwr_ctrl); 1092 void __spm_sync_vcore_dvfs_pcm_flags(uint32_t *dest_pcm_flags, 1093 const uint32_t *src_pcm_flags); 1094 1095 void __spm_set_pcm_wdt(int en); 1096 uint32_t __spm_get_pcm_timer_val(void); 1097 uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr); 1098 void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl); 1099 void __spm_ext_int_wakeup_req_clr(void); 1100 1101 static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl, 1102 uint32_t flags) 1103 { 1104 if (pwrctrl->pcm_flags_cust == 0) 1105 pwrctrl->pcm_flags = flags; 1106 else 1107 pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust; 1108 } 1109 1110 static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl, 1111 uint32_t flags) 1112 { 1113 if (pwrctrl->pcm_flags1_cust == 0) 1114 pwrctrl->pcm_flags1 = flags; 1115 else 1116 pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust; 1117 } 1118 1119 void __spm_hw_s1_state_monitor(int en, uint32_t *status); 1120 1121 static inline void spm_hw_s1_state_monitor_resume(void) 1122 { 1123 __spm_hw_s1_state_monitor(1, NULL); 1124 } 1125 static inline void spm_hw_s1_state_monitor_pause(uint32_t *status) 1126 { 1127 __spm_hw_s1_state_monitor(0, status); 1128 } 1129 1130 int32_t __spm_wait_spm_request_ack(uint32_t spm_resource_req, 1131 uint32_t timeout_us); 1132 1133 #endif /* MT_SPM_INTERNAL */ 1134