1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_HWREQ_H 8 #define MT_SPM_HWREQ_H 9 10 #include <drivers/spm/mt_spm_resource_req.h> 11 12 /* Resource requirement which HW CG support */ 13 enum { 14 HWCG_DDREN = 0, 15 HWCG_VRF18, 16 HWCG_INFRA, 17 HWCG_PMIC, 18 HWCG_F26M, 19 HWCG_VCORE, 20 HWCG_MAX 21 }; 22 23 /* Signal that monitor by HW CG */ 24 enum spm_hwcg_setting { 25 HWCG_PWR, 26 HWCG_PWR_MSB, 27 HWCG_MODULE_BUSY, 28 HWCG_SETTING_MAX 29 }; 30 31 enum spm_pwr_status { 32 HWCG_PWR_MD1 = 0, 33 HWCG_PWR_CONN, 34 HWCG_PWR_APIFR_IO, 35 HWCG_PWR_APIFR_MEM, 36 HWCG_PWR_PERI, 37 HWCG_PWR_PERI_ETHER, 38 HWCG_PWR_SSUSB_PD_PHY_P0, 39 HWCG_PWR_SSUSB_P0, 40 HWCG_PWR_SSUSB_P1, 41 HWCG_PWR_SSUSB_P23, 42 HWCG_PWR_SSUSB_PHY_P2, 43 HWCG_PWR_UFS0, 44 HWCG_PWR_UFS0_PHY, 45 HWCG_PWR_PEXTP_MAC0, 46 HWCG_PWR_PEXTP_MAC1, 47 HWCG_PWR_PEXTP_MAC2, 48 HWCG_PWR_PEXTP_PHY0, 49 HWCG_PWR_PEXTP_PHY1, 50 HWCG_PWR_PEXTP_PHY3, 51 HWCG_PWR_AUDIO, 52 HWCG_PWR_ADSP_CORE1, 53 HWCG_PWR_ADSP_TOP, 54 HWCG_PWR_ADSP_INFRA, 55 HWCG_PWR_ADSP_AO, 56 HWCG_PWR_MM_PROC, 57 HWCG_PWR_SCP, 58 HWCG_PWR_SCP2, 59 HWCG_PWR_DPYD0, 60 HWCG_PWR_DPYD1, 61 HWCG_PWR_DPYD2, 62 HWCG_PWR_DPYD3, 63 HWCG_PWR_DPYA0 64 }; 65 66 CASSERT(HWCG_PWR_SSUSB_P1 == 8, spm_pwr_status_err); 67 CASSERT(HWCG_PWR_PEXTP_PHY0 == 16, spm_pwr_status_err); 68 CASSERT(HWCG_PWR_MM_PROC == 24, spm_pwr_status_err); 69 70 enum spm_hwcg_module_busy { 71 HWCG_MODULE_ADSP = 0, 72 HWCG_MODULE_MMPLL, 73 HWCG_MODULE_TVDPLL, 74 HWCG_MODULE_MSDCPLL, 75 HWCG_MODULE_UNIVPLL 76 }; 77 78 enum spm_hwcg_sta_type { 79 HWCG_STA_DEFAULT_MASK, 80 HWCG_STA_MASK 81 }; 82 83 /* Signal that monitor by HW CG */ 84 enum spm_peri_req_setting { 85 PERI_REQ_EN = 0, 86 PERI_REQ_SETTING_MAX 87 }; 88 89 /* Resource requirement which PERI REQ support */ 90 enum spm_peri_req { 91 PERI_REQ_F26M = 0, 92 PERI_REQ_INFRA, 93 PERI_REQ_SYSPLL, 94 PERI_REQ_APSRC, 95 PERI_REQ_EMI, 96 PERI_REQ_DDREN, 97 PERI_REQ_MAX 98 }; 99 100 enum spm_peri_req_sta_type { 101 PERI_REQ_STA_DEFAULT_MASK, 102 PERI_REQ_STA_MASK, 103 PERI_REQ_STA_MAX 104 }; 105 106 enum spm_peri_req_status { 107 PERI_RES_REQ_EN, 108 PERI_REQ_STATUS_MAX 109 }; 110 111 enum spm_peri_req_status_raw { 112 PERI_REQ_STATUS_RAW_NUM, 113 PERI_REQ_STATUS_RAW_NAME, 114 PERI_REQ_STATUS_RAW_STA, 115 PERI_REQ_STATUS_RAW_MAX 116 }; 117 118 enum spm_peri_req_en { 119 PERI_REQ_EN_FLASHIF = 0, 120 PERI_REQ_EN_AP_DMA, 121 PERI_REQ_EN_UART0, 122 PERI_REQ_EN_UART1, 123 PERI_REQ_EN_UART2, 124 PERI_REQ_EN_UART3, 125 PERI_REQ_EN_UART4, 126 PERI_REQ_EN_UART5, 127 PERI_REQ_EN_PWM, 128 PERI_REQ_EN_SPI0, 129 PERI_REQ_EN_SPI0_INCR16, 130 PERI_REQ_EN_SPI1, 131 PERI_REQ_EN_SPI2, 132 PERI_REQ_EN_SPI3, 133 PERI_REQ_EN_SPI4, 134 PERI_REQ_EN_SPI5, 135 PERI_REQ_EN_SPI6, 136 PERI_REQ_EN_SPI7, 137 PERI_REQ_EN_IMP_IIC, 138 PERI_REQ_EN_MSDC1, 139 PERI_REQ_EN_MSDC2, 140 PERI_REQ_EN_USB, 141 PERI_REQ_EN_UFS0, 142 PERI_REQ_EN_PEXTP1, 143 PERI_REQ_EN_PEXTP0, 144 PERI_REQ_EN_RSV_DUMMY0, 145 PERI_REQ_EN_PERI_BUS_TRAFFIC, 146 PERI_REQ_EN_RSV_DUMMY1, 147 PERI_REQ_EN_RSV_FOR_MSDC, 148 PERI_REQ_EN_MAX 149 }; 150 151 CASSERT(PERI_REQ_EN_PWM == 8, spm_peri_req_en_err); 152 CASSERT(PERI_REQ_EN_SPI6 == 16, spm_peri_req_en_err); 153 CASSERT(PERI_REQ_EN_PEXTP0 == 24, spm_peri_req_en_err); 154 155 struct spm_peri_req_sta { 156 uint32_t sta; 157 }; 158 159 struct spm_peri_req_info { 160 uint32_t req_en; 161 uint32_t req_sta; 162 }; 163 164 struct spm_hwcg_sta { 165 uint32_t sta; 166 }; 167 168 #define MT_SPM_HW_CG_STA_INIT(_x) ({ if (_x) _x->sta = 0; }) 169 170 #define INFRA_AO_OFFSET(offset) (INFRACFG_AO_BASE + offset) 171 #define INFRA_SW_CG_MASK INFRA_AO_OFFSET(0x060) 172 173 #define REG_PERI_REQ_EN(N) (PERICFG_AO_BASE + 0x070 + 0x4 * (N)) 174 #define REG_PERI_REQ_STA(N) (PERICFG_AO_BASE + 0x0A0 + 0x4 * (N)) 175 176 void spm_hwreq_init(void); 177 178 /* Res: 179 * Please refer the mt_spm_resource_req.h. 180 * Section of SPM resource request internal bit_mask. 181 */ 182 void spm_hwcg_ctrl(uint32_t res, enum spm_hwcg_setting type, 183 uint32_t is_set, uint32_t val); 184 185 /* Idx: 186 * index of HWCG setting. 187 */ 188 void spm_hwcg_ctrl_by_index(uint32_t idx, enum spm_hwcg_setting type, 189 uint32_t is_set, uint32_t val); 190 191 /* Res: 192 * Please refer the mt_spm_resource_req.h. 193 * Section of SPM resource request internal bit_mask. 194 */ 195 int spm_hwcg_get_setting(uint32_t res, enum spm_hwcg_sta_type sta_type, 196 enum spm_hwcg_setting type, 197 struct spm_hwcg_sta *sta); 198 199 /* Idx: 200 * index of HWCG setting. 201 */ 202 int spm_hwcg_get_setting_by_index(uint32_t idx, 203 enum spm_hwcg_sta_type sta_type, 204 enum spm_hwcg_setting type, 205 struct spm_hwcg_sta *sta); 206 207 uint32_t spm_hwcg_get_status(uint32_t idx, enum spm_hwcg_setting type); 208 209 int spm_hwcg_name(uint32_t idex, char *name, size_t sz); 210 211 static inline uint32_t spm_hwcg_num(void) 212 { 213 return HWCG_MAX; 214 } 215 216 static inline uint32_t spm_hwcg_setting_num(void) 217 { 218 return HWCG_SETTING_MAX; 219 } 220 221 uint32_t spm_peri_req_get_status(uint32_t idx, enum spm_peri_req_status type); 222 uint32_t spm_peri_req_get_status_raw(enum spm_peri_req_status_raw type, 223 uint32_t idx, 224 char *name, size_t sz); 225 226 static inline uint32_t spm_peri_req_num(void) 227 { 228 return PERI_REQ_MAX; 229 } 230 231 static inline uint32_t spm_peri_req_setting_num(void) 232 { 233 return PERI_REQ_SETTING_MAX; 234 } 235 236 int spm_peri_req_get_setting_by_index(uint32_t idx, 237 enum spm_peri_req_sta_type sta_type, 238 struct spm_peri_req_sta *sta); 239 240 void spm_peri_req_ctrl_by_index(uint32_t idx, 241 uint32_t is_set, uint32_t val); 242 243 int spm_peri_req_name(uint32_t idex, char *name, size_t sz); 244 245 #endif /* MT_SPM_HWREQ_H */ 246