1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_HWREQ_H 8 #define MT_SPM_HWREQ_H 9 10 #include <drivers/spm/mt_spm_resource_req.h> 11 #include <mt_spm_common_v1.h> 12 13 /* ddren, apsrc and emi resource have become hw resource_req. 14 * So we don't need to use HW CG for request resource. 15 */ 16 #define SPM_HWCG_DDREN_PWR_MB 0 17 #define SPM_HWCG_DDREN_PWR_MSB_MB 0 18 #define SPM_HWCG_DDREN_MODULE_BUSY_MB 0 19 20 /* VRF18 */ 21 #define SPM_HWCG_VRF18_PWR_MB 0 22 #define SPM_HWCG_VRF18_PWR_MSB_MB 0 23 #define SPM_HWCG_VRF18_MODULE_BUSY_MB 0 24 25 /* INFRA */ 26 #define SPM_HWCG_INFRA_PWR_MB SPM_HWCG_VRF18_PWR_MB 27 #define SPM_HWCG_INFRA_PWR_MSB_MB SPM_HWCG_VRF18_PWR_MSB_MB 28 #define SPM_HWCG_INFRA_MODULE_BUSY_MB 0 29 30 /* PMIC */ 31 #define SPM_HWCG_PMIC_PWR_MB SPM_HWCG_VRF18_PWR_MB 32 #define SPM_HWCG_PMIC_PWR_MSB_MB SPM_HWCG_VRF18_PWR_MSB_MB 33 #define SPM_HWCG_PMIC_MODULE_BUSY_MB 0 34 35 /* F26M */ 36 #define SPM_HWCG_F26M_PWR_MB SPM_HWCG_PMIC_PWR_MB 37 #define SPM_HWCG_F26M_PWR_MSB_MB SPM_HWCG_PMIC_PWR_MSB_MB 38 #define SPM_HWCG_F26M_MODULE_BUSY_MB 0 39 40 /* VCORE */ 41 #define SPM_HWCG_VCORE_PWR_MB SPM_HWCG_F26M_PWR_MB 42 #define SPM_HWCG_VCORE_PWR_MSB_MB SPM_HWCG_F26M_PWR_MSB_MB 43 #define SPM_HWCG_VCORE_MODULE_BUSY_MB SPM_HWCG_F26M_MODULE_BUSY_MB 44 45 #define INFRA_SW_CG_MB 0 46 47 #define PERI_REQ_EN_MASK 0x3FFFFF 48 49 /* Resource requirement which HW CG support */ 50 enum { 51 HWCG_DDREN = 0, 52 HWCG_VRF18, 53 HWCG_INFRA, 54 HWCG_PMIC, 55 HWCG_F26M, 56 HWCG_VCORE, 57 HWCG_MAX 58 }; 59 60 enum spm_pwr_status { 61 HWCG_PWR_MD1 = 0, 62 HWCG_PWR_CONN, 63 HWCG_PWR_APIFR_IO, 64 HWCG_PWR_APIFR_MEM, 65 HWCG_PWR_PERI, 66 HWCG_PWR_PERI_ETHER, 67 HWCG_PWR_SSUSB_PD_PHY_P0, 68 HWCG_PWR_SSUSB_P0, 69 HWCG_PWR_SSUSB_P1, 70 HWCG_PWR_SSUSB_P23, 71 HWCG_PWR_SSUSB_PHY_P2, 72 HWCG_PWR_UFS0, 73 HWCG_PWR_UFS0_PHY, 74 HWCG_PWR_PEXTP_MAC0, 75 HWCG_PWR_PEXTP_MAC1, 76 HWCG_PWR_PEXTP_MAC2, 77 HWCG_PWR_PEXTP_PHY0, 78 HWCG_PWR_PEXTP_PHY1, 79 HWCG_PWR_PEXTP_PHY3, 80 HWCG_PWR_AUDIO, 81 HWCG_PWR_ADSP_CORE1, 82 HWCG_PWR_ADSP_TOP, 83 HWCG_PWR_ADSP_INFRA, 84 HWCG_PWR_ADSP_AO, 85 HWCG_PWR_MM_PROC, 86 HWCG_PWR_SCP, 87 HWCG_PWR_SCP2, 88 HWCG_PWR_DPYD0, 89 HWCG_PWR_DPYD1, 90 HWCG_PWR_DPYD2, 91 HWCG_PWR_DPYD3, 92 HWCG_PWR_DPYA0 93 }; 94 95 CASSERT(HWCG_PWR_SSUSB_P1 == 8, spm_pwr_status_err); 96 CASSERT(HWCG_PWR_PEXTP_PHY0 == 16, spm_pwr_status_err); 97 CASSERT(HWCG_PWR_MM_PROC == 24, spm_pwr_status_err); 98 99 enum spm_hwcg_module_busy { 100 HWCG_MODULE_ADSP = 0, 101 HWCG_MODULE_MMPLL, 102 HWCG_MODULE_TVDPLL, 103 HWCG_MODULE_MSDCPLL, 104 HWCG_MODULE_UNIVPLL 105 }; 106 107 /* Resource requirement which PERI REQ support */ 108 enum spm_peri_req { 109 PERI_REQ_F26M = 0, 110 PERI_REQ_INFRA, 111 PERI_REQ_SYSPLL, 112 PERI_REQ_APSRC, 113 PERI_REQ_EMI, 114 PERI_REQ_DDREN, 115 PERI_REQ_MAX 116 }; 117 118 enum spm_peri_req_en { 119 PERI_REQ_EN_FLASHIF = 0, 120 PERI_REQ_EN_AP_DMA, 121 PERI_REQ_EN_UART0, 122 PERI_REQ_EN_UART1, 123 PERI_REQ_EN_UART2, 124 PERI_REQ_EN_UART3, 125 PERI_REQ_EN_UART4, 126 PERI_REQ_EN_UART5, 127 PERI_REQ_EN_PWM, 128 PERI_REQ_EN_SPI0, 129 PERI_REQ_EN_SPI0_INCR16, 130 PERI_REQ_EN_SPI1, 131 PERI_REQ_EN_SPI2, 132 PERI_REQ_EN_SPI3, 133 PERI_REQ_EN_SPI4, 134 PERI_REQ_EN_SPI5, 135 PERI_REQ_EN_SPI6, 136 PERI_REQ_EN_SPI7, 137 PERI_REQ_EN_IMP_IIC, 138 PERI_REQ_EN_MSDC1, 139 PERI_REQ_EN_MSDC2, 140 PERI_REQ_EN_USB, 141 PERI_REQ_EN_UFS0, 142 PERI_REQ_EN_PEXTP1, 143 PERI_REQ_EN_PEXTP0, 144 PERI_REQ_EN_RSV_DUMMY0, 145 PERI_REQ_EN_PERI_BUS_TRAFFIC, 146 PERI_REQ_EN_RSV_DUMMY1, 147 PERI_REQ_EN_RSV_FOR_MSDC, 148 PERI_REQ_EN_MAX 149 }; 150 151 CASSERT(PERI_REQ_EN_PWM == 8, spm_peri_req_en_err); 152 CASSERT(PERI_REQ_EN_SPI6 == 16, spm_peri_req_en_err); 153 CASSERT(PERI_REQ_EN_PEXTP0 == 24, spm_peri_req_en_err); 154 155 #define INFRA_AO_OFFSET(offset) (INFRACFG_AO_BASE + offset) 156 #define INFRA_SW_CG_MASK INFRA_AO_OFFSET(0x060) 157 158 #define REG_PERI_REQ_EN(N) (PERICFG_AO_BASE + 0x070 + 0x4 * (N)) 159 #define REG_PERI_REQ_STA(N) (PERICFG_AO_BASE + 0x0A0 + 0x4 * (N)) 160 161 static inline uint32_t spm_hwcg_num(void) 162 { 163 return HWCG_MAX; 164 } 165 166 static inline uint32_t spm_peri_req_num(void) 167 { 168 return PERI_REQ_MAX; 169 } 170 171 #endif /* MT_SPM_HWREQ_H */ 172