1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_H 8 #define MT_SPM_H 9 10 #include <stdint.h> 11 #include <stdio.h> 12 13 #include <lib/pm/mtk_pm.h> 14 #include <lpm_v2/mt_lp_rq.h> 15 16 #ifdef __GNUC__ 17 #define spm_likely(x) __builtin_expect(!!(x), 1) 18 #define spm_unlikely(x) __builtin_expect(!!(x), 0) 19 #else 20 #define spm_likely(x) (x) 21 #define spm_unlikely(x) (x) 22 #endif 23 24 #define CLK_SCP_CFG_0 (CKSYS_BASE + 0x1A0) 25 #define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x070) 26 #define RG_AXI_DCM_DIS_EN BIT(21) 27 #define RG_PLLCK_SEL_NO_SPM BIT(22) 28 29 #define MT_SPM_TIME_GET(tm) ({ (tm) = el3_uptime(); }) 30 31 #define MT_SPM_VERSION_ES 0x0 32 #define MT_SPM_VERSION_CS 0x1 33 34 #define SPM_FW_NO_RESUME 1 35 #define MCUSYS_MTCMOS_ON 0 36 #define WAKEUP_LOG_ON 0 37 38 #define MT_SPM_USING_SRCLKEN_RC 39 /* SPM extern operand definition */ 40 #define MT_SPM_EX_OP_CLR_26M_RECORD BIT(0) 41 #define MT_SPM_EX_OP_SET_WDT BIT(1) 42 #define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ BIT(2) 43 #define MT_SPM_EX_OP_SET_SUSPEND_MODE BIT(3) 44 #define MT_SPM_EX_OP_SET_IS_ADSP BIT(4) 45 #define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM BIT(5) 46 #define MT_SPM_EX_OP_HW_S1_DETECT BIT(6) 47 #define MT_SPM_EX_OP_TRACE_LP BIT(7) 48 #define MT_SPM_EX_OP_TRACE_SUSPEND BIT(8) 49 #define MT_SPM_EX_OP_TRACE_TIMESTAMP_EN BIT(9) 50 #define MT_SPM_EX_OP_TIME_CHECK BIT(10) 51 #define MT_SPM_EX_OP_TIME_OBS BIT(11) 52 #define MT_SPM_EX_OP_SET_IS_USB_HEADSET BIT(12) 53 #define MT_SPM_EX_OP_SET_IS_FM_AUDIO BIT(13) 54 #define MT_SPM_EX_OP_DEVICES_SAVE BIT(14) 55 #define MT_SPM_EX_OP_NOTIFY_INFRA_OFF BIT(15) 56 57 #define MT_BUS26M_EXT_LP_26M_ON_MODE (MT_SPM_EX_OP_SET_IS_ADSP | \ 58 MT_SPM_EX_OP_SET_IS_FM_AUDIO) 59 60 #define MT_VCORE_EXT_LP_VCORE_ON_MODE (MT_SPM_EX_OP_SET_IS_ADSP | \ 61 MT_SPM_EX_OP_SET_IS_FM_AUDIO) 62 63 /* EN SPM INFRA DEBUG OUT */ 64 #define DEBUGSYS_DEBUG_EN_REG (DBGSYS_DEM_BASE + 0x94) 65 66 /* INFRA_AO_DEBUG_CON */ 67 #define INFRA_AO_DBG_CON0 (INFRACFG_AO_BASE + 0x500) 68 #define INFRA_AO_DBG_CON1 (INFRACFG_AO_BASE + 0x504) 69 #define INFRA_AO_DBG_CON2 (INFRACFG_AO_BASE + 0x508) 70 #define INFRA_AO_DBG_CON3 (INFRACFG_AO_BASE + 0x50C) 71 72 /* SPM init. related registers */ 73 #define VLP_AO_APC_CON (VLP_AO_DEVAPC_APB_BASE + 0xF00) 74 #define VLP_AO_MAS_SEC_0 (VLP_AO_DEVAPC_APB_BASE + 0xA00) 75 #define SCP_CFGREG_PERI_BUS_CTRL0 (SCP_CFGREG_BASE + 0x24) 76 #define MODULE_SW_CG_0_MASK (INFRACFG_AO_BASE + 0x060) 77 #define VLP_DBG_MON_SEL0_ADDR (VLPCFG_BUS_BASE + 0x108) 78 #define VLP_DBG_MON_SEL1_ADDR (VLPCFG_BUS_BASE + 0x10C) 79 #define VLP_CLKSQ_CON1 (VLP_CKSYS_BASE + 0x224) 80 #define VLP_AP_PLL_CON3 (VLP_CKSYS_BASE + 0x264) 81 82 /* SPM SRAM Data */ 83 #define SPM_SRAM_TIMESTAMP_START (SPM_SRAM_BASE + 0xF80) 84 #define SPM_SRAM_TIMESTAMP_END (SPM_SRAM_BASE + 0xFFC) 85 #define SPM_SRAM_TIMESTAMP_SIZE \ 86 (((SPM_SRAM_TIMESTAMP_END - SPM_SRAM_TIMESTAMP_START) >> 2) + 1) 87 88 /* AP_MDSRC_REQ MD 26M ON settle time (3ms) */ 89 #define AP_MDSRC_REQ_MD_26M_SETTLE 3 90 91 /* Setting the SPM settle time*/ 92 #define SPM_SYSCLK_SETTLE 0x60FE /* 1685us */ 93 94 /* Setting the SPM req/ack time*/ 95 #define SPM_ACK_TIMEOUT_US 1000 96 97 /* Settine the firmware status check for SPM PC */ 98 #define SPM_PC_CHECKABLE 99 100 enum { 101 SPM_ARGS_SPMFW_IDX_KICK = 0, 102 SPM_ARGS_SPMFW_INIT, 103 SPM_ARGS_SUSPEND, 104 SPM_ARGS_SUSPEND_FINISH, 105 SPM_ARGS_SODI, 106 SPM_ARGS_SODI_FINISH, 107 SPM_ARGS_DPIDLE, 108 SPM_ARGS_DPIDLE_FINISH, 109 SPM_ARGS_PCM_WDT, 110 SPM_ARGS_SUSPEND_CALLBACK, 111 SPM_ARGS_HARDWARE_CG_CHECK, 112 SPM_ARGS_NUM, 113 }; 114 115 typedef enum { 116 WR_NONE = 0, 117 WR_UART_BUSY, 118 WR_ABORT, 119 WR_PCM_TIMER, 120 WR_WAKE_SRC, 121 WR_DVFSRC, 122 WR_TWAM, 123 WR_PMSR, 124 WR_SPM_ACK_CHK, 125 WR_UNKNOWN, 126 } wake_reason_t; 127 128 struct pwr_ctrl; 129 struct spm_lp_scen; 130 131 void spm_set_irq_num(uint32_t num); 132 void spm_irq0_handler(uint64_t x1, uint64_t x2); 133 struct mt_lp_resource_user *get_spm_res_user(void); 134 int mt_spm_common_sodi_get_spm_pcm_flag(uint32_t *lp, uint32_t idx); 135 void mt_spm_common_sodi_en(bool en); 136 int mt_spm_common_sodi_get_spm_lp(struct spm_lp_scen **lp); 137 void mt_spm_set_common_sodi_pwrctr(void); 138 void mt_spm_set_common_sodi_pcm_flags(void); 139 int spm_boot_init(void); 140 void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue); 141 extern uint32_t mt_spm_version; 142 extern struct pwr_ctrl spm_init_ctrl; 143 /* Support by bl31_plat_setup.c */ 144 uint32_t is_abnormal_boot(void); 145 146 #endif /* MT_SPM_H */ 147