1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PCM_DEF_H 8 #define PCM_DEF_H 9 10 /*-- MD32PCM_STA1 define */ 11 #define R12_PCM_TIMER_B BIT(0) 12 #define R12_TWAM_PMSR_DVFSRC BIT(1) 13 #define R12_KP_IRQ_B BIT(2) 14 #define R12_APWDT_EVENT_B BIT(3) 15 #define R12_APXGPT_EVENT_B BIT(4) 16 #define R12_CONN2AP_WAKEUP_B BIT(5) 17 #define R12_EINT_EVENT_B BIT(6) 18 #define R12_CONN_WDT_IRQ_B BIT(7) 19 #define R12_CCIF0_EVENT_B BIT(8) 20 #define R12_CCIF1_EVENT_B BIT(9) 21 #define R12_SSPM2SPM_WAKEUP_B BIT(10) 22 #define R12_SCP2SPM_WAKEUP_B BIT(11) 23 #define R12_VADSP2SPM_WAKEUP_B BIT(12) 24 #define R12_PCM_WDT_WAKEUP_B BIT(13) 25 #define R12_USB0_CDSC_B BIT(14) 26 #define R12_USB0_POWERDWN_B BIT(15) 27 #define R12_SBD_INTR_B BIT(16) 28 #define R12_UART2SPM_IRQ_B BIT(17) 29 #define R12_SYS_TIMER_EVENT_B BIT(18) 30 #define R12_EINT_EVENT_SECURE_B BIT(19) 31 #define R12_AFE_IRQ_MCU_B BIT(20) 32 #define R12_THERM_CTRL_EVENT_B BIT(21) 33 #define R12_SYS_CIRQ_IRQ_B BIT(22) 34 #define R12_MD2AP_PEER_EVENT_B BIT(23) 35 #define R12_CSYSPWREQ_B BIT(24) 36 #define R12_MD_WDT_B BIT(25) 37 #define R12_AP2AP_PEER_WAKEUP_B BIT(26) 38 #define R12_SEJ_B BIT(27) 39 #define R12_CPU_WAKEUP BIT(28) 40 #define R12_APUSYS_WAKE_HOST_B BIT(29) 41 #define R12_PCIE_MAC_IRQ_WAKE_B BIT(30) 42 #define R12_MSDC_WAKEUP_EVENT_B BIT(31) 43 44 /*-- MD32PCM_STA2 define */ 45 #define EVENT_F26M_WAKE BIT(0) 46 #define EVENT_F26M_SLEEP BIT(1) 47 #define EVENT_INFRA_WAKE BIT(2) 48 #define EVENT_INFRA_SLEEP BIT(3) 49 #define EVENT_EMI_WAKE BIT(4) 50 #define EVENT_EMI_SLEEP BIT(5) 51 #define EVENT_APSRC_WAKE BIT(6) 52 #define EVENT_APSRC_SLEEP BIT(7) 53 #define EVENT_VRF18_WAKE BIT(8) 54 #define EVENT_VRF18_SLEEP BIT(9) 55 #define EVENT_DVFS_WAKE BIT(10) 56 #define EVENT_DDREN_WAKE BIT(11) 57 #define EVENT_DDREN_SLEEP BIT(12) 58 #define EVENT_VCORE_WAKE BIT(13) 59 #define EVENT_VCORE_SLEEP BIT(14) 60 #define EVENT_PMIC_WAKE BIT(15) 61 #define EVENT_PMIC_SLEEP BIT(16) 62 #define EVENT_CPUEB_STATE BIT(17) 63 #define EVENT_SSPM_STATE BIT(18) 64 #define EVENT_DPM_STATE BIT(19) 65 #define EVENT_CONN_SRCCLKENB_D2T BIT(20) 66 #define EVENT_SW_MAILBOX_WAKE BIT(21) 67 #define EVENT_SPM_LEAVE_SUSPEND_ACK BIT(22) 68 #define EVENT_SPM_LEAVE_DEEPIDLE_ACK BIT(23) 69 #define EVENT_CROSS_REQ_APU_l3 BIT(24) 70 #define EVENT_DFD_SOC_MTCMOS_REQ BIT(25) 71 #define EVENT_AOVBUS_WAKE BIT(26) 72 #define EVENT_AOVBUS_SLEEP BIT(27) 73 74 enum SPM_WAKE_SRC_LIST { 75 WAKE_SRC_STA1_PCM_TIMER = BIT(0), 76 WAKE_SRC_STA1_TWAM_PMSR_DVFSRC = BIT(1), 77 WAKE_SRC_STA1_KP_IRQ_B = BIT(2), 78 WAKE_SRC_STA1_APWDT_EVENT_B = BIT(3), 79 WAKE_SRC_STA1_APXGPT1_EVENT_B = BIT(4), 80 WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B = BIT(5), 81 WAKE_SRC_STA1_EINT_EVENT_B = BIT(6), 82 WAKE_SRC_STA1_CONN_WDT_IRQ_B = BIT(7), 83 WAKE_SRC_STA1_CCIF0_EVENT_B = BIT(8), 84 WAKE_SRC_STA1_CCIF1_EVENT_B = BIT(9), 85 WAKE_SRC_STA1_SC_SSPM2SPM_WAKEUP_B = BIT(10), 86 WAKE_SRC_STA1_SC_SCP2SPM_WAKEUP_B = BIT(11), 87 WAKE_SRC_STA1_VADSP2SPM_WAKEUP_B = BIT(12), 88 WAKE_SRC_STA1_PCM_WDT_WAKEUP_B = BIT(13), 89 WAKE_SRC_STA1_USB_CDSC_B = BIT(14), 90 WAKE_SRC_STA1_USB_POWERDWN_B = BIT(15), 91 WAKE_SRC_STA1_SBD_INTR_B = BIT(16), 92 WAKE_SRC_STA1_UART2SPM_IRQ_B = BIT(17), 93 WAKE_SRC_STA1_SYS_TIMER_EVENT_B = BIT(18), 94 WAKE_SRC_STA1_EINT_EVENT_SECURE_B = BIT(19), 95 WAKE_SRC_STA1_AFE_IRQ_MCU_B = BIT(20), 96 WAKE_SRC_STA1_THERM_CTRL_EVENT_B = BIT(21), 97 WAKE_SRC_STA1_SYS_CIRQ_IRQ_B = BIT(22), 98 WAKE_SRC_STA1_MD2AP_PEER_EVENT_B = BIT(23), 99 WAKE_SRC_STA1_CSYSPWREQ_B = BIT(24), 100 WAKE_SRC_STA1_MD1_WDT_B = BIT(25), 101 WAKE_SRC_STA1_AP2AP_PEER_WAKEUPEVENT_B = BIT(26), 102 WAKE_SRC_STA1_SEJ_EVENT_B = BIT(27), 103 WAKE_SRC_STA1_SPM_CPU_WAKEUPEVENT_B = BIT(28), 104 WAKE_SRC_STA1_APUSYS_WAKE_HOST_B = BIT(29), 105 WAKE_SRC_STA1_PCIE_MAC_IRQ_WAKE_B = BIT(30), 106 WAKE_SRC_STA1_MSDC_WAKEUP_EVENT_B = BIT(31), 107 }; 108 109 extern const char *wakesrc_str[32]; 110 111 #endif /* PCM_DEF_H */ 112