1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_INTERNAL_H 8 #define MT_SPM_INTERNAL_H 9 10 #include <dbg_ctrl.h> 11 #include <inc/mt_spm_ver.h> 12 #include <mt_spm.h> 13 #include <mt_spm_stats.h> 14 15 /************************************** 16 * Config and Parameter 17 **************************************/ 18 #define POWER_ON_VAL0_DEF 0x0000F100 19 /* SPM_POWER_ON_VAL1 */ 20 #define POWER_ON_VAL1_DEF 0x003FFE20 21 /* SPM_WAKEUP_EVENT_MASK */ 22 #define SPM_WAKEUP_EVENT_MASK_DEF 0xF97FFCFF 23 24 /* PCM_WDT_VAL */ 25 #define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ 26 /* AP WDT setting */ 27 #define AP_WDT_TIMEOUT (31) /* 31s */ 28 #define AP_WDT_TIMEOUT_SUSPEND (5400) /* 90min */ 29 /* PCM_TIMER_VAL */ 30 #define PCM_TIMER_SUSPEND \ 31 ((AP_WDT_TIMEOUT_SUSPEND - 30) * 32768) /* 90min - 30sec */ 32 #define PCM_TIMER_MAX (PCM_TIMER_SUSPEND) 33 34 /************************************** 35 * Define and Declare 36 **************************************/ 37 /* MD32PCM ADDR for SPM code fetch */ 38 #define MD32PCM_BASE (SPM_BASE + 0x0A00) 39 #define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000) 40 #define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200) 41 #define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204) 42 #define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208) 43 #define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C) 44 #define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210) 45 #define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214) 46 #define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218) 47 #define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224) 48 #define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C) 49 50 /* ABORT MASK for DEBUG FOORTPRINT */ 51 #define DEBUG_ABORT_MASK \ 52 (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \ 53 SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN) 54 55 #define DEBUG_ABORT_MASK_1 \ 56 (SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_0 | \ 57 SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_1 | \ 58 SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_LOW_ABORT | \ 59 SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_HIGH_ABORT | \ 60 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \ 61 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \ 62 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \ 63 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \ 64 SPM_DBG1_DEBUG_IDX_SPM_PMIF_CMD_RDY_ABORT) 65 66 struct pwr_ctrl { 67 /* for SPM */ 68 uint32_t pcm_flags; 69 uint32_t pcm_flags_cust; 70 uint32_t pcm_flags_cust_set; 71 uint32_t pcm_flags_cust_clr; 72 uint32_t pcm_flags1; 73 uint32_t pcm_flags1_cust; 74 uint32_t pcm_flags1_cust_set; 75 uint32_t pcm_flags1_cust_clr; 76 uint32_t timer_val; 77 uint32_t timer_val_cust; 78 uint32_t timer_val_ramp_en; 79 uint32_t timer_val_ramp_en_sec; 80 uint32_t wake_src; 81 uint32_t wake_src_cust; 82 uint32_t wakelock_timer_val; 83 uint8_t wdt_disable; 84 /* Auto-gen Start */ 85 86 /* SPM_CLK_CON */ 87 uint8_t reg_spm_lock_infra_dcm_lsb; 88 uint8_t reg_cxo32k_remove_en_lsb; 89 uint8_t reg_spm_leave_suspend_merge_mask_lsb; 90 uint8_t reg_sysclk0_src_mask_b_lsb; 91 uint8_t reg_sysclk1_src_mask_b_lsb; 92 uint8_t reg_sysclk2_src_mask_b_lsb; 93 94 /* SPM_AP_STANDBY_CON */ 95 uint8_t reg_wfi_op; 96 uint8_t reg_wfi_type; 97 uint8_t reg_mp0_cputop_idle_mask; 98 uint8_t reg_mp1_cputop_idle_mask; 99 uint8_t reg_mcusys_idle_mask; 100 uint8_t reg_csyspwrup_req_mask_lsb; 101 uint8_t reg_wfi_af_sel; 102 uint8_t reg_cpu_sleep_wfi; 103 104 /* SPM_SRC_REQ */ 105 uint8_t reg_spm_adsp_mailbox_req; 106 uint8_t reg_spm_apsrc_req; 107 uint8_t reg_spm_ddren_req; 108 uint8_t reg_spm_dvfs_req; 109 uint8_t reg_spm_emi_req; 110 uint8_t reg_spm_f26m_req; 111 uint8_t reg_spm_infra_req; 112 uint8_t reg_spm_pmic_req; 113 uint8_t reg_spm_scp_mailbox_req; 114 uint8_t reg_spm_sspm_mailbox_req; 115 uint8_t reg_spm_sw_mailbox_req; 116 uint8_t reg_spm_vcore_req; 117 uint8_t reg_spm_vrf18_req; 118 uint8_t adsp_mailbox_state; 119 uint8_t apsrc_state; 120 uint8_t ddren_state; 121 uint8_t dvfs_state; 122 uint8_t emi_state; 123 uint8_t f26m_state; 124 uint8_t infra_state; 125 uint8_t pmic_state; 126 uint8_t scp_mailbox_state; 127 uint8_t sspm_mailbox_state; 128 uint8_t sw_mailbox_state; 129 uint8_t vcore_state; 130 uint8_t vrf18_state; 131 132 /* SPM_SRC_MASK_0 */ 133 uint8_t reg_apu_apsrc_req_mask_b; 134 uint8_t reg_apu_ddren_req_mask_b; 135 uint8_t reg_apu_emi_req_mask_b; 136 uint8_t reg_apu_infra_req_mask_b; 137 uint8_t reg_apu_pmic_req_mask_b; 138 uint8_t reg_apu_srcclkena_mask_b; 139 uint8_t reg_apu_vrf18_req_mask_b; 140 uint8_t reg_audio_dsp_apsrc_req_mask_b; 141 uint8_t reg_audio_dsp_ddren_req_mask_b; 142 uint8_t reg_audio_dsp_emi_req_mask_b; 143 uint8_t reg_audio_dsp_infra_req_mask_b; 144 uint8_t reg_audio_dsp_pmic_req_mask_b; 145 uint8_t reg_audio_dsp_srcclkena_mask_b; 146 uint8_t reg_audio_dsp_vcore_req_mask_b; 147 uint8_t reg_audio_dsp_vrf18_req_mask_b; 148 uint8_t reg_cam_apsrc_req_mask_b; 149 uint8_t reg_cam_ddren_req_mask_b; 150 uint8_t reg_cam_emi_req_mask_b; 151 uint8_t reg_cam_infra_req_mask_b; 152 uint8_t reg_cam_pmic_req_mask_b; 153 uint8_t reg_cam_srcclkena_mask_b; 154 uint8_t reg_cam_vrf18_req_mask_b; 155 uint8_t reg_mdp_emi_req_mask_b; 156 157 /* SPM_SRC_MASK_1 */ 158 uint32_t reg_ccif_apsrc_req_mask_b; 159 uint32_t reg_ccif_emi_req_mask_b; 160 161 /* SPM_SRC_MASK_2 */ 162 uint32_t reg_ccif_infra_req_mask_b; 163 uint32_t reg_ccif_pmic_req_mask_b; 164 165 /* SPM_SRC_MASK_3 */ 166 uint32_t reg_ccif_srcclkena_mask_b; 167 uint32_t reg_ccif_vrf18_req_mask_b; 168 uint8_t reg_ccu_apsrc_req_mask_b; 169 uint8_t reg_ccu_ddren_req_mask_b; 170 uint8_t reg_ccu_emi_req_mask_b; 171 uint8_t reg_ccu_infra_req_mask_b; 172 uint8_t reg_ccu_pmic_req_mask_b; 173 uint8_t reg_ccu_srcclkena_mask_b; 174 uint8_t reg_ccu_vrf18_req_mask_b; 175 uint8_t reg_cg_check_apsrc_req_mask_b; 176 177 /* SPM_SRC_MASK_4 */ 178 uint8_t reg_cg_check_ddren_req_mask_b; 179 uint8_t reg_cg_check_emi_req_mask_b; 180 uint8_t reg_cg_check_infra_req_mask_b; 181 uint8_t reg_cg_check_pmic_req_mask_b; 182 uint8_t reg_cg_check_srcclkena_mask_b; 183 uint8_t reg_cg_check_vcore_req_mask_b; 184 uint8_t reg_cg_check_vrf18_req_mask_b; 185 uint8_t reg_conn_apsrc_req_mask_b; 186 uint8_t reg_conn_ddren_req_mask_b; 187 uint8_t reg_conn_emi_req_mask_b; 188 uint8_t reg_conn_infra_req_mask_b; 189 uint8_t reg_conn_pmic_req_mask_b; 190 uint8_t reg_conn_srcclkena_mask_b; 191 uint8_t reg_conn_srcclkenb_mask_b; 192 uint8_t reg_conn_vcore_req_mask_b; 193 uint8_t reg_conn_vrf18_req_mask_b; 194 uint8_t reg_cpueb_apsrc_req_mask_b; 195 uint8_t reg_cpueb_ddren_req_mask_b; 196 uint8_t reg_cpueb_emi_req_mask_b; 197 uint8_t reg_cpueb_infra_req_mask_b; 198 uint8_t reg_cpueb_pmic_req_mask_b; 199 uint8_t reg_cpueb_srcclkena_mask_b; 200 uint8_t reg_cpueb_vrf18_req_mask_b; 201 uint8_t reg_disp0_apsrc_req_mask_b; 202 uint8_t reg_disp0_ddren_req_mask_b; 203 uint8_t reg_disp0_emi_req_mask_b; 204 uint8_t reg_disp0_infra_req_mask_b; 205 uint8_t reg_disp0_pmic_req_mask_b; 206 uint8_t reg_disp0_srcclkena_mask_b; 207 uint8_t reg_disp0_vrf18_req_mask_b; 208 uint8_t reg_disp1_apsrc_req_mask_b; 209 uint8_t reg_disp1_ddren_req_mask_b; 210 211 /* SPM_SRC_MASK_5 */ 212 uint8_t reg_disp1_emi_req_mask_b; 213 uint8_t reg_disp1_infra_req_mask_b; 214 uint8_t reg_disp1_pmic_req_mask_b; 215 uint8_t reg_disp1_srcclkena_mask_b; 216 uint8_t reg_disp1_vrf18_req_mask_b; 217 uint8_t reg_dpm_apsrc_req_mask_b; 218 uint8_t reg_dpm_ddren_req_mask_b; 219 uint8_t reg_dpm_emi_req_mask_b; 220 uint8_t reg_dpm_infra_req_mask_b; 221 uint8_t reg_dpm_pmic_req_mask_b; 222 uint8_t reg_dpm_srcclkena_mask_b; 223 224 /* SPM_SRC_MASK_6 */ 225 uint8_t reg_dpm_vcore_req_mask_b; 226 uint8_t reg_dpm_vrf18_req_mask_b; 227 uint8_t reg_dpmaif_apsrc_req_mask_b; 228 uint8_t reg_dpmaif_ddren_req_mask_b; 229 uint8_t reg_dpmaif_emi_req_mask_b; 230 uint8_t reg_dpmaif_infra_req_mask_b; 231 uint8_t reg_dpmaif_pmic_req_mask_b; 232 uint8_t reg_dpmaif_srcclkena_mask_b; 233 uint8_t reg_dpmaif_vrf18_req_mask_b; 234 uint8_t reg_dvfsrc_level_req_mask_b; 235 uint8_t reg_emisys_apsrc_req_mask_b; 236 uint8_t reg_emisys_ddren_req_mask_b; 237 uint8_t reg_emisys_emi_req_mask_b; 238 uint8_t reg_gce_d_apsrc_req_mask_b; 239 uint8_t reg_gce_d_ddren_req_mask_b; 240 uint8_t reg_gce_d_emi_req_mask_b; 241 uint8_t reg_gce_d_infra_req_mask_b; 242 uint8_t reg_gce_d_pmic_req_mask_b; 243 uint8_t reg_gce_d_srcclkena_mask_b; 244 uint8_t reg_gce_d_vrf18_req_mask_b; 245 uint8_t reg_gce_m_apsrc_req_mask_b; 246 uint8_t reg_gce_m_ddren_req_mask_b; 247 uint8_t reg_gce_m_emi_req_mask_b; 248 uint8_t reg_gce_m_infra_req_mask_b; 249 uint8_t reg_gce_m_pmic_req_mask_b; 250 uint8_t reg_gce_m_srcclkena_mask_b; 251 252 /* SPM_SRC_MASK_7 */ 253 uint8_t reg_gce_m_vrf18_req_mask_b; 254 uint8_t reg_gpueb_apsrc_req_mask_b; 255 uint8_t reg_gpueb_ddren_req_mask_b; 256 uint8_t reg_gpueb_emi_req_mask_b; 257 uint8_t reg_gpueb_infra_req_mask_b; 258 uint8_t reg_gpueb_pmic_req_mask_b; 259 uint8_t reg_gpueb_srcclkena_mask_b; 260 uint8_t reg_gpueb_vrf18_req_mask_b; 261 uint8_t reg_hwccf_apsrc_req_mask_b; 262 uint8_t reg_hwccf_ddren_req_mask_b; 263 uint8_t reg_hwccf_emi_req_mask_b; 264 uint8_t reg_hwccf_infra_req_mask_b; 265 uint8_t reg_hwccf_pmic_req_mask_b; 266 uint8_t reg_hwccf_srcclkena_mask_b; 267 uint8_t reg_hwccf_vcore_req_mask_b; 268 uint8_t reg_hwccf_vrf18_req_mask_b; 269 uint8_t reg_img_apsrc_req_mask_b; 270 uint8_t reg_img_ddren_req_mask_b; 271 uint8_t reg_img_emi_req_mask_b; 272 uint8_t reg_img_infra_req_mask_b; 273 uint8_t reg_img_pmic_req_mask_b; 274 uint8_t reg_img_srcclkena_mask_b; 275 uint8_t reg_img_vrf18_req_mask_b; 276 uint8_t reg_infrasys_apsrc_req_mask_b; 277 uint8_t reg_infrasys_ddren_req_mask_b; 278 uint8_t reg_infrasys_emi_req_mask_b; 279 uint8_t reg_ipic_infra_req_mask_b; 280 uint8_t reg_ipic_vrf18_req_mask_b; 281 uint8_t reg_mcu_apsrc_req_mask_b; 282 uint8_t reg_mcu_ddren_req_mask_b; 283 uint8_t reg_mcu_emi_req_mask_b; 284 285 /* SPM_SRC_MASK_8 */ 286 uint8_t reg_mcusys_apsrc_req_mask_b; 287 uint8_t reg_mcusys_ddren_req_mask_b; 288 uint8_t reg_mcusys_emi_req_mask_b; 289 uint8_t reg_mcusys_infra_req_mask_b; 290 291 /* SPM_SRC_MASK_9 */ 292 uint8_t reg_mcusys_pmic_req_mask_b; 293 uint8_t reg_mcusys_srcclkena_mask_b; 294 uint8_t reg_mcusys_vrf18_req_mask_b; 295 uint8_t reg_md_apsrc_req_mask_b; 296 uint8_t reg_md_ddren_req_mask_b; 297 uint8_t reg_md_emi_req_mask_b; 298 uint8_t reg_md_infra_req_mask_b; 299 uint8_t reg_md_pmic_req_mask_b; 300 uint8_t reg_md_srcclkena_mask_b; 301 uint8_t reg_md_srcclkena1_mask_b; 302 uint8_t reg_md_vcore_req_mask_b; 303 304 /* SPM_SRC_MASK_10 */ 305 uint8_t reg_md_vrf18_req_mask_b; 306 uint8_t reg_mdp_apsrc_req_mask_b; 307 uint8_t reg_mdp_ddren_req_mask_b; 308 uint8_t reg_mm_proc_apsrc_req_mask_b; 309 uint8_t reg_mm_proc_ddren_req_mask_b; 310 uint8_t reg_mm_proc_emi_req_mask_b; 311 uint8_t reg_mm_proc_infra_req_mask_b; 312 uint8_t reg_mm_proc_pmic_req_mask_b; 313 uint8_t reg_mm_proc_srcclkena_mask_b; 314 uint8_t reg_mm_proc_vrf18_req_mask_b; 315 uint8_t reg_mmsys_apsrc_req_mask_b; 316 uint8_t reg_mmsys_ddren_req_mask_b; 317 uint8_t reg_mmsys_vrf18_req_mask_b; 318 uint8_t reg_pcie0_apsrc_req_mask_b; 319 uint8_t reg_pcie0_ddren_req_mask_b; 320 uint8_t reg_pcie0_infra_req_mask_b; 321 uint8_t reg_pcie0_srcclkena_mask_b; 322 uint8_t reg_pcie0_vrf18_req_mask_b; 323 uint8_t reg_pcie1_apsrc_req_mask_b; 324 uint8_t reg_pcie1_ddren_req_mask_b; 325 uint8_t reg_pcie1_infra_req_mask_b; 326 uint8_t reg_pcie1_srcclkena_mask_b; 327 uint8_t reg_pcie1_vrf18_req_mask_b; 328 uint8_t reg_perisys_apsrc_req_mask_b; 329 uint8_t reg_perisys_ddren_req_mask_b; 330 uint8_t reg_perisys_emi_req_mask_b; 331 uint8_t reg_perisys_infra_req_mask_b; 332 uint8_t reg_perisys_pmic_req_mask_b; 333 uint8_t reg_perisys_srcclkena_mask_b; 334 uint8_t reg_perisys_vcore_req_mask_b; 335 uint8_t reg_perisys_vrf18_req_mask_b; 336 uint8_t reg_scp_apsrc_req_mask_b; 337 338 /* SPM_SRC_MASK_11 */ 339 uint8_t reg_scp_ddren_req_mask_b; 340 uint8_t reg_scp_emi_req_mask_b; 341 uint8_t reg_scp_infra_req_mask_b; 342 uint8_t reg_scp_pmic_req_mask_b; 343 uint8_t reg_scp_srcclkena_mask_b; 344 uint8_t reg_scp_vcore_req_mask_b; 345 uint8_t reg_scp_vrf18_req_mask_b; 346 uint8_t reg_srcclkeni_infra_req_mask_b; 347 uint8_t reg_srcclkeni_pmic_req_mask_b; 348 uint8_t reg_srcclkeni_srcclkena_mask_b; 349 uint8_t reg_sspm_apsrc_req_mask_b; 350 uint8_t reg_sspm_ddren_req_mask_b; 351 uint8_t reg_sspm_emi_req_mask_b; 352 uint8_t reg_sspm_infra_req_mask_b; 353 uint8_t reg_sspm_pmic_req_mask_b; 354 uint8_t reg_sspm_srcclkena_mask_b; 355 uint8_t reg_sspm_vrf18_req_mask_b; 356 uint8_t reg_ssr_apsrc_req_mask_b; 357 uint8_t reg_ssr_ddren_req_mask_b; 358 uint8_t reg_ssr_emi_req_mask_b; 359 uint8_t reg_ssr_infra_req_mask_b; 360 uint8_t reg_ssr_pmic_req_mask_b; 361 uint8_t reg_ssr_srcclkena_mask_b; 362 uint8_t reg_ssr_vrf18_req_mask_b; 363 uint8_t reg_ufs_apsrc_req_mask_b; 364 uint8_t reg_ufs_ddren_req_mask_b; 365 uint8_t reg_ufs_emi_req_mask_b; 366 uint8_t reg_ufs_infra_req_mask_b; 367 uint8_t reg_ufs_pmic_req_mask_b; 368 369 /* SPM_SRC_MASK_12 */ 370 uint8_t reg_ufs_srcclkena_mask_b; 371 uint8_t reg_ufs_vrf18_req_mask_b; 372 uint8_t reg_vdec_apsrc_req_mask_b; 373 uint8_t reg_vdec_ddren_req_mask_b; 374 uint8_t reg_vdec_emi_req_mask_b; 375 uint8_t reg_vdec_infra_req_mask_b; 376 uint8_t reg_vdec_pmic_req_mask_b; 377 uint8_t reg_vdec_srcclkena_mask_b; 378 uint8_t reg_vdec_vrf18_req_mask_b; 379 uint8_t reg_venc_apsrc_req_mask_b; 380 uint8_t reg_venc_ddren_req_mask_b; 381 uint8_t reg_venc_emi_req_mask_b; 382 uint8_t reg_venc_infra_req_mask_b; 383 uint8_t reg_venc_pmic_req_mask_b; 384 uint8_t reg_venc_srcclkena_mask_b; 385 uint8_t reg_venc_vrf18_req_mask_b; 386 uint8_t reg_ipe_apsrc_req_mask_b; 387 uint8_t reg_ipe_ddren_req_mask_b; 388 uint8_t reg_ipe_emi_req_mask_b; 389 uint8_t reg_ipe_infra_req_mask_b; 390 uint8_t reg_ipe_pmic_req_mask_b; 391 uint8_t reg_ipe_srcclkena_mask_b; 392 uint8_t reg_ipe_vrf18_req_mask_b; 393 uint8_t reg_ufs_vcore_req_mask_b; 394 395 /* SPM_EVENT_CON_MISC */ 396 uint8_t reg_srcclken_fast_resp; 397 uint8_t reg_csyspwrup_ack_mask; 398 399 /* SPM_WAKEUP_EVENT_MASK */ 400 uint32_t reg_wakeup_event_mask; 401 402 /* SPM_WAKEUP_EVENT_EXT_MASK */ 403 uint32_t reg_ext_wakeup_event_mask; 404 405 /* Auto-gen End */ 406 }; 407 408 /* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */ 409 enum pwr_ctrl_enum { 410 PW_PCM_FLAGS, 411 PW_PCM_FLAGS_CUST, 412 PW_PCM_FLAGS_CUST_SET, 413 PW_PCM_FLAGS_CUST_CLR, 414 PW_PCM_FLAGS1, 415 PW_PCM_FLAGS1_CUST, 416 PW_PCM_FLAGS1_CUST_SET, 417 PW_PCM_FLAGS1_CUST_CLR, 418 PW_TIMER_VAL, 419 PW_TIMER_VAL_CUST, 420 PW_TIMER_VAL_RAMP_EN, 421 PW_TIMER_VAL_RAMP_EN_SEC, 422 PW_WAKE_SRC, 423 PW_WAKE_SRC_CUST, 424 PW_WAKELOCK_TIMER_VAL, 425 PW_WDT_DISABLE, 426 427 /* SPM_SRC_REQ */ 428 PW_REG_SPM_ADSP_MAILBOX_REQ, 429 PW_REG_SPM_APSRC_REQ, 430 PW_REG_SPM_DDREN_REQ, 431 PW_REG_SPM_DVFS_REQ, 432 PW_REG_SPM_EMI_REQ, 433 PW_REG_SPM_F26M_REQ, 434 PW_REG_SPM_INFRA_REQ, 435 PW_REG_SPM_PMIC_REQ, 436 PW_REG_SPM_SCP_MAILBOX_REQ, 437 PW_REG_SPM_SSPM_MAILBOX_REQ, 438 PW_REG_SPM_SW_MAILBOX_REQ, 439 PW_REG_SPM_VCORE_REQ, 440 PW_REG_SPM_VRF18_REQ, 441 442 /* SPM_SRC_MASK_0 */ 443 PW_REG_APU_APSRC_REQ_MASK_B, 444 PW_REG_APU_DDREN_REQ_MASK_B, 445 PW_REG_APU_EMI_REQ_MASK_B, 446 PW_REG_APU_INFRA_REQ_MASK_B, 447 PW_REG_APU_PMIC_REQ_MASK_B, 448 PW_REG_APU_SRCCLKENA_MASK_B, 449 PW_REG_APU_VRF18_REQ_MASK_B, 450 PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B, 451 PW_REG_AUDIO_DSP_DDREN_REQ_MASK_B, 452 PW_REG_AUDIO_DSP_EMI_REQ_MASK_B, 453 PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B, 454 PW_REG_AUDIO_DSP_PMIC_REQ_MASK_B, 455 PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B, 456 PW_REG_AUDIO_DSP_VCORE_REQ_MASK_B, 457 PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B, 458 PW_REG_CAM_APSRC_REQ_MASK_B, 459 PW_REG_CAM_DDREN_REQ_MASK_B, 460 PW_REG_CAM_EMI_REQ_MASK_B, 461 PW_REG_CAM_INFRA_REQ_MASK_B, 462 PW_REG_CAM_PMIC_REQ_MASK_B, 463 PW_REG_CAM_SRCCLKENA_MASK_B, 464 PW_REG_CAM_VRF18_REQ_MASK_B, 465 PW_REG_MDP_EMI_REQ_MASK_B, 466 467 /* SPM_SRC_MASK_1 */ 468 PW_REG_CCIF_APSRC_REQ_MASK_B, 469 PW_REG_CCIF_EMI_REQ_MASK_B, 470 471 /* SPM_SRC_MASK_2 */ 472 PW_REG_CCIF_INFRA_REQ_MASK_B, 473 PW_REG_CCIF_PMIC_REQ_MASK_B, 474 475 /* SPM_SRC_MASK_3 */ 476 PW_REG_CCIF_SRCCLKENA_MASK_B, 477 PW_REG_CCIF_VRF18_REQ_MASK_B, 478 PW_REG_CCU_APSRC_REQ_MASK_B, 479 PW_REG_CCU_DDREN_REQ_MASK_B, 480 PW_REG_CCU_EMI_REQ_MASK_B, 481 PW_REG_CCU_INFRA_REQ_MASK_B, 482 PW_REG_CCU_PMIC_REQ_MASK_B, 483 PW_REG_CCU_SRCCLKENA_MASK_B, 484 PW_REG_CCU_VRF18_REQ_MASK_B, 485 PW_REG_CG_CHECK_APSRC_REQ_MASK_B, 486 487 /* SPM_SRC_MASK_4 */ 488 PW_REG_CG_CHECK_DDREN_REQ_MASK_B, 489 PW_REG_CG_CHECK_EMI_REQ_MASK_B, 490 PW_REG_CG_CHECK_INFRA_REQ_MASK_B, 491 PW_REG_CG_CHECK_PMIC_REQ_MASK_B, 492 PW_REG_CG_CHECK_SRCCLKENA_MASK_B, 493 PW_REG_CG_CHECK_VCORE_REQ_MASK_B, 494 PW_REG_CG_CHECK_VRF18_REQ_MASK_B, 495 PW_REG_CONN_APSRC_REQ_MASK_B, 496 PW_REG_CONN_DDREN_REQ_MASK_B, 497 PW_REG_CONN_EMI_REQ_MASK_B, 498 PW_REG_CONN_INFRA_REQ_MASK_B, 499 PW_REG_CONN_PMIC_REQ_MASK_B, 500 PW_REG_CONN_SRCCLKENA_MASK_B, 501 PW_REG_CONN_SRCCLKENB_MASK_B, 502 PW_REG_CONN_VCORE_REQ_MASK_B, 503 PW_REG_CONN_VRF18_REQ_MASK_B, 504 PW_REG_CPUEB_APSRC_REQ_MASK_B, 505 PW_REG_CPUEB_DDREN_REQ_MASK_B, 506 PW_REG_CPUEB_EMI_REQ_MASK_B, 507 PW_REG_CPUEB_INFRA_REQ_MASK_B, 508 PW_REG_CPUEB_PMIC_REQ_MASK_B, 509 PW_REG_CPUEB_SRCCLKENA_MASK_B, 510 PW_REG_CPUEB_VRF18_REQ_MASK_B, 511 PW_REG_DISP0_APSRC_REQ_MASK_B, 512 PW_REG_DISP0_DDREN_REQ_MASK_B, 513 PW_REG_DISP0_EMI_REQ_MASK_B, 514 PW_REG_DISP0_INFRA_REQ_MASK_B, 515 PW_REG_DISP0_PMIC_REQ_MASK_B, 516 PW_REG_DISP0_SRCCLKENA_MASK_B, 517 PW_REG_DISP0_VRF18_REQ_MASK_B, 518 PW_REG_DISP1_APSRC_REQ_MASK_B, 519 PW_REG_DISP1_DDREN_REQ_MASK_B, 520 521 /* SPM_SRC_MASK_5 */ 522 PW_REG_DISP1_EMI_REQ_MASK_B, 523 PW_REG_DISP1_INFRA_REQ_MASK_B, 524 PW_REG_DISP1_PMIC_REQ_MASK_B, 525 PW_REG_DISP1_SRCCLKENA_MASK_B, 526 PW_REG_DISP1_VRF18_REQ_MASK_B, 527 PW_REG_DPM_APSRC_REQ_MASK_B, 528 PW_REG_DPM_DDREN_REQ_MASK_B, 529 PW_REG_DPM_EMI_REQ_MASK_B, 530 PW_REG_DPM_INFRA_REQ_MASK_B, 531 PW_REG_DPM_PMIC_REQ_MASK_B, 532 PW_REG_DPM_SRCCLKENA_MASK_B, 533 534 /* SPM_SRC_MASK_6 */ 535 PW_REG_DPM_VCORE_REQ_MASK_B, 536 PW_REG_DPM_VRF18_REQ_MASK_B, 537 PW_REG_DPMAIF_APSRC_REQ_MASK_B, 538 PW_REG_DPMAIF_DDREN_REQ_MASK_B, 539 PW_REG_DPMAIF_EMI_REQ_MASK_B, 540 PW_REG_DPMAIF_INFRA_REQ_MASK_B, 541 PW_REG_DPMAIF_PMIC_REQ_MASK_B, 542 PW_REG_DPMAIF_SRCCLKENA_MASK_B, 543 PW_REG_DPMAIF_VRF18_REQ_MASK_B, 544 PW_REG_DVFSRC_LEVEL_REQ_MASK_B, 545 PW_REG_EMISYS_APSRC_REQ_MASK_B, 546 PW_REG_EMISYS_DDREN_REQ_MASK_B, 547 PW_REG_EMISYS_EMI_REQ_MASK_B, 548 PW_REG_GCE_D_APSRC_REQ_MASK_B, 549 PW_REG_GCE_D_DDREN_REQ_MASK_B, 550 PW_REG_GCE_D_EMI_REQ_MASK_B, 551 PW_REG_GCE_D_INFRA_REQ_MASK_B, 552 PW_REG_GCE_D_PMIC_REQ_MASK_B, 553 PW_REG_GCE_D_SRCCLKENA_MASK_B, 554 PW_REG_GCE_D_VRF18_REQ_MASK_B, 555 PW_REG_GCE_M_APSRC_REQ_MASK_B, 556 PW_REG_GCE_M_DDREN_REQ_MASK_B, 557 PW_REG_GCE_M_EMI_REQ_MASK_B, 558 PW_REG_GCE_M_INFRA_REQ_MASK_B, 559 PW_REG_GCE_M_PMIC_REQ_MASK_B, 560 PW_REG_GCE_M_SRCCLKENA_MASK_B, 561 562 /* SPM_SRC_MASK_7 */ 563 PW_REG_GCE_M_VRF18_REQ_MASK_B, 564 PW_REG_GPUEB_APSRC_REQ_MASK_B, 565 PW_REG_GPUEB_DDREN_REQ_MASK_B, 566 PW_REG_GPUEB_EMI_REQ_MASK_B, 567 PW_REG_GPUEB_INFRA_REQ_MASK_B, 568 PW_REG_GPUEB_PMIC_REQ_MASK_B, 569 PW_REG_GPUEB_SRCCLKENA_MASK_B, 570 PW_REG_GPUEB_VRF18_REQ_MASK_B, 571 PW_REG_HWCCF_APSRC_REQ_MASK_B, 572 PW_REG_HWCCF_DDREN_REQ_MASK_B, 573 PW_REG_HWCCF_EMI_REQ_MASK_B, 574 PW_REG_HWCCF_INFRA_REQ_MASK_B, 575 PW_REG_HWCCF_PMIC_REQ_MASK_B, 576 PW_REG_HWCCF_SRCCLKENA_MASK_B, 577 PW_REG_HWCCF_VCORE_REQ_MASK_B, 578 PW_REG_HWCCF_VRF18_REQ_MASK_B, 579 PW_REG_IMG_APSRC_REQ_MASK_B, 580 PW_REG_IMG_DDREN_REQ_MASK_B, 581 PW_REG_IMG_EMI_REQ_MASK_B, 582 PW_REG_IMG_INFRA_REQ_MASK_B, 583 PW_REG_IMG_PMIC_REQ_MASK_B, 584 PW_REG_IMG_SRCCLKENA_MASK_B, 585 PW_REG_IMG_VRF18_REQ_MASK_B, 586 PW_REG_INFRASYS_APSRC_REQ_MASK_B, 587 PW_REG_INFRASYS_DDREN_REQ_MASK_B, 588 PW_REG_INFRASYS_EMI_REQ_MASK_B, 589 PW_REG_IPIC_INFRA_REQ_MASK_B, 590 PW_REG_IPIC_VRF18_REQ_MASK_B, 591 PW_REG_MCU_APSRC_REQ_MASK_B, 592 PW_REG_MCU_DDREN_REQ_MASK_B, 593 PW_REG_MCU_EMI_REQ_MASK_B, 594 595 /* SPM_SRC_MASK_8 */ 596 PW_REG_MCUSYS_APSRC_REQ_MASK_B, 597 PW_REG_MCUSYS_DDREN_REQ_MASK_B, 598 PW_REG_MCUSYS_EMI_REQ_MASK_B, 599 PW_REG_MCUSYS_INFRA_REQ_MASK_B, 600 601 /* SPM_SRC_MASK_9 */ 602 PW_REG_MCUSYS_PMIC_REQ_MASK_B, 603 PW_REG_MCUSYS_SRCCLKENA_MASK_B, 604 PW_REG_MCUSYS_VRF18_REQ_MASK_B, 605 PW_REG_MD_APSRC_REQ_MASK_B, 606 PW_REG_MD_DDREN_REQ_MASK_B, 607 PW_REG_MD_EMI_REQ_MASK_B, 608 PW_REG_MD_INFRA_REQ_MASK_B, 609 PW_REG_MD_PMIC_REQ_MASK_B, 610 PW_REG_MD_SRCCLKENA_MASK_B, 611 PW_REG_MD_SRCCLKENA1_MASK_B, 612 PW_REG_MD_VCORE_REQ_MASK_B, 613 614 /* SPM_SRC_MASK_10 */ 615 PW_REG_MD_VRF18_REQ_MASK_B, 616 PW_REG_MDP_APSRC_REQ_MASK_B, 617 PW_REG_MDP_DDREN_REQ_MASK_B, 618 PW_REG_MM_PROC_APSRC_REQ_MASK_B, 619 PW_REG_MM_PROC_DDREN_REQ_MASK_B, 620 PW_REG_MM_PROC_EMI_REQ_MASK_B, 621 PW_REG_MM_PROC_INFRA_REQ_MASK_B, 622 PW_REG_MM_PROC_PMIC_REQ_MASK_B, 623 PW_REG_MM_PROC_SRCCLKENA_MASK_B, 624 PW_REG_MM_PROC_VRF18_REQ_MASK_B, 625 PW_REG_MMSYS_APSRC_REQ_MASK_B, 626 PW_REG_MMSYS_DDREN_REQ_MASK_B, 627 PW_REG_MMSYS_VRF18_REQ_MASK_B, 628 PW_REG_PCIE0_APSRC_REQ_MASK_B, 629 PW_REG_PCIE0_DDREN_REQ_MASK_B, 630 PW_REG_PCIE0_INFRA_REQ_MASK_B, 631 PW_REG_PCIE0_SRCCLKENA_MASK_B, 632 PW_REG_PCIE0_VRF18_REQ_MASK_B, 633 PW_REG_PCIE1_APSRC_REQ_MASK_B, 634 PW_REG_PCIE1_DDREN_REQ_MASK_B, 635 PW_REG_PCIE1_INFRA_REQ_MASK_B, 636 PW_REG_PCIE1_SRCCLKENA_MASK_B, 637 PW_REG_PCIE1_VRF18_REQ_MASK_B, 638 PW_REG_PERISYS_APSRC_REQ_MASK_B, 639 PW_REG_PERISYS_DDREN_REQ_MASK_B, 640 PW_REG_PERISYS_EMI_REQ_MASK_B, 641 PW_REG_PERISYS_INFRA_REQ_MASK_B, 642 PW_REG_PERISYS_PMIC_REQ_MASK_B, 643 PW_REG_PERISYS_SRCCLKENA_MASK_B, 644 PW_REG_PERISYS_VCORE_REQ_MASK_B, 645 PW_REG_PERISYS_VRF18_REQ_MASK_B, 646 PW_REG_SCP_APSRC_REQ_MASK_B, 647 648 /* SPM_SRC_MASK_11 */ 649 PW_REG_SCP_DDREN_REQ_MASK_B, 650 PW_REG_SCP_EMI_REQ_MASK_B, 651 PW_REG_SCP_INFRA_REQ_MASK_B, 652 PW_REG_SCP_PMIC_REQ_MASK_B, 653 PW_REG_SCP_SRCCLKENA_MASK_B, 654 PW_REG_SCP_VCORE_REQ_MASK_B, 655 PW_REG_SCP_VRF18_REQ_MASK_B, 656 PW_REG_SRCCLKENI_INFRA_REQ_MASK_B, 657 PW_REG_SRCCLKENI_PMIC_REQ_MASK_B, 658 PW_REG_SRCCLKENI_SRCCLKENA_MASK_B, 659 PW_REG_SSPM_APSRC_REQ_MASK_B, 660 PW_REG_SSPM_DDREN_REQ_MASK_B, 661 PW_REG_SSPM_EMI_REQ_MASK_B, 662 PW_REG_SSPM_INFRA_REQ_MASK_B, 663 PW_REG_SSPM_PMIC_REQ_MASK_B, 664 PW_REG_SSPM_SRCCLKENA_MASK_B, 665 PW_REG_SSPM_VRF18_REQ_MASK_B, 666 PW_REG_SSR_APSRC_REQ_MASK_B, 667 PW_REG_SSR_DDREN_REQ_MASK_B, 668 PW_REG_SSR_EMI_REQ_MASK_B, 669 PW_REG_SSR_INFRA_REQ_MASK_B, 670 PW_REG_SSR_PMIC_REQ_MASK_B, 671 PW_REG_SSR_SRCCLKENA_MASK_B, 672 PW_REG_SSR_VRF18_REQ_MASK_B, 673 PW_REG_UFS_APSRC_REQ_MASK_B, 674 PW_REG_UFS_DDREN_REQ_MASK_B, 675 PW_REG_UFS_EMI_REQ_MASK_B, 676 PW_REG_UFS_INFRA_REQ_MASK_B, 677 PW_REG_UFS_PMIC_REQ_MASK_B, 678 679 /* SPM_SRC_MASK_12 */ 680 PW_REG_UFS_SRCCLKENA_MASK_B, 681 PW_REG_UFS_VRF18_REQ_MASK_B, 682 PW_REG_VDEC_APSRC_REQ_MASK_B, 683 PW_REG_VDEC_DDREN_REQ_MASK_B, 684 PW_REG_VDEC_EMI_REQ_MASK_B, 685 PW_REG_VDEC_INFRA_REQ_MASK_B, 686 PW_REG_VDEC_PMIC_REQ_MASK_B, 687 PW_REG_VDEC_SRCCLKENA_MASK_B, 688 PW_REG_VDEC_VRF18_REQ_MASK_B, 689 PW_REG_VENC_APSRC_REQ_MASK_B, 690 PW_REG_VENC_DDREN_REQ_MASK_B, 691 PW_REG_VENC_EMI_REQ_MASK_B, 692 PW_REG_VENC_INFRA_REQ_MASK_B, 693 PW_REG_VENC_PMIC_REQ_MASK_B, 694 PW_REG_VENC_SRCCLKENA_MASK_B, 695 PW_REG_VENC_VRF18_REQ_MASK_B, 696 PW_REG_IPE_APSRC_REQ_MASK_B, 697 PW_REG_IPE_DDREN_REQ_MASK_B, 698 PW_REG_IPE_EMI_REQ_MASK_B, 699 PW_REG_IPE_INFRA_REQ_MASK_B, 700 PW_REG_IPE_PMIC_REQ_MASK_B, 701 PW_REG_IPE_SRCCLKENA_MASK_B, 702 PW_REG_IPE_VRF18_REQ_MASK_B, 703 PW_REG_UFS_VCORE_REQ_MASK_B, 704 705 /* SPM_EVENT_CON_MISC */ 706 PW_REG_SRCCLKEN_FAST_RESP, 707 PW_REG_CSYSPWRUP_ACK_MASK, 708 709 /* SPM_WAKEUP_EVENT_MASK */ 710 PW_REG_WAKEUP_EVENT_MASK, 711 712 /* SPM_WAKEUP_EVENT_EXT_MASK */ 713 PW_REG_EXT_WAKEUP_EVENT_MASK, 714 715 PW_MAX_COUNT, 716 }; 717 718 /* 719 * HW_TARG_GROUP_SEL_3 : 3b'1 (pcm_reg_13) 720 * HW_TARG_SIGNAL_SEL_3 : 5b'10101 (pcm_reg_13[21]=sc_emi_clk_off_ack_all) 721 * HW_TRIG_GROUP_SEL_3 : 3'b100 (trig_reserve) 722 * HW_TRIG_SIGNAL_SEL_3 : 5'b1100 (trig_reserve[24]=sc_hw_s1_req) 723 */ 724 #define SPM_ACK_CHK_3_SEL_HW_S1 (0x00350098) 725 #define SPM_ACK_CHK_3_HW_S1_CNT (1) 726 727 #define SPM_ACK_CHK_3_CON_HW_MODE_TRIG (0x800) 728 /* BIT[0]: SW_EN, BIT[4]: STA_EN, BIT[8]: HW_EN */ 729 #define SPM_ACK_CHK_3_CON_EN (0x110) 730 #define SPM_ACK_CHK_3_CON_CLR_ALL (0x2) 731 /* BIT[15]: RESULT */ 732 #define SPM_ACK_CHK_3_CON_RESULT (0x8000) 733 734 struct wake_status_trace_comm { 735 uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */ 736 uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */ 737 uint32_t timer_out; /* SPM_SW_RSV_6*/ 738 uint32_t b_sw_flag0; /* PCM_WDT_LATCH_SPARE_7 */ 739 uint32_t b_sw_flag1; /* PCM_WDT_LATCH_SPARE_5 */ 740 uint32_t r12; /* SPM_SW_RSV_0 */ 741 uint32_t r13; /* PCM_REG13_DATA */ 742 uint32_t req_sta0; /* SRC_REQ_STA_0 */ 743 uint32_t req_sta1; /* SRC_REQ_STA_1 */ 744 uint32_t req_sta2; /* SRC_REQ_STA_2 */ 745 uint32_t req_sta3; /* SRC_REQ_STA_3 */ 746 uint32_t req_sta4; /* SRC_REQ_STA_4 */ 747 uint32_t req_sta5; /* SRC_REQ_STA_5 */ 748 uint32_t req_sta6; /* SRC_REQ_STA_6 */ 749 uint32_t req_sta7; /* SRC_REQ_STA_7 */ 750 uint32_t req_sta8; /* SRC_REQ_STA_8 */ 751 uint32_t req_sta9; /* SRC_REQ_STA_9 */ 752 uint32_t req_sta10; /* SRC_REQ_STA_10 */ 753 uint32_t req_sta11; /* SRC_REQ_STA_11 */ 754 uint32_t req_sta12; /* SRC_REQ_STA_12 */ 755 uint32_t raw_sta; /* SPM_WAKEUP_STA */ 756 uint32_t times_h; /* timestamp high bits */ 757 uint32_t times_l; /* timestamp low bits */ 758 uint32_t resumetime; /* timestamp low bits */ 759 }; 760 761 struct wake_status_trace { 762 /* Common part */ 763 struct wake_status_trace_comm comm; 764 /* Add suspend or idle part bellow */ 765 }; 766 767 struct wake_status { 768 struct wake_status_trace tr; 769 uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */ 770 uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */ 771 uint32_t md32pcm_wakeup_sta; /* MD32PCM_WAKEUP_STA */ 772 uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */ 773 uint32_t wake_misc; /* SPM_SW_RSV_5 */ 774 uint32_t sw_flag0; /* SPM_SW_FLAG_0 */ 775 uint32_t sw_flag1; /* SPM_SW_FLAG_1 */ 776 uint32_t isr; /* SPM_IRQ_STA */ 777 uint32_t log_index; 778 uint32_t is_abort; 779 }; 780 781 struct spm_lp_scen { 782 struct pcm_desc *pcmdesc; 783 struct pwr_ctrl *pwrctrl; 784 struct dbg_ctrl *dbgctrl; 785 struct spm_lp_stat *lpstat; 786 }; 787 788 extern struct spm_lp_scen __spm_vcorefs; 789 790 void __spm_set_cpu_status(int cpu); 791 void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc); 792 void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc); 793 794 void __spm_init_pcm_register(void); /* init r0 and r7 */ 795 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl, 796 uint32_t resource_usage); 797 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); 798 void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl); 799 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl); 800 void __spm_send_cpu_wakeup_event(void); 801 802 void __spm_get_wakeup_status(struct wake_status *wakesta, uint32_t ext_status); 803 void __spm_clean_after_wakeup(void); 804 wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta); 805 806 void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl, 807 const struct pwr_ctrl *src_pwr_ctrl); 808 809 void __spm_set_pcm_wdt(int en); 810 uint32_t __spm_get_pcm_timer_val(void); 811 uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr); 812 void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl); 813 void __spm_ext_int_wakeup_req_clr(void); 814 815 static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl, 816 uint32_t flags) 817 { 818 if (!pwrctrl) 819 return; 820 821 if (pwrctrl->pcm_flags_cust == 0) 822 pwrctrl->pcm_flags = flags; 823 else 824 pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust; 825 } 826 827 static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl, 828 uint32_t flags) 829 { 830 if (!pwrctrl) 831 return; 832 833 if (pwrctrl->pcm_flags1_cust == 0) 834 pwrctrl->pcm_flags1 = flags; 835 else 836 pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust; 837 } 838 839 void __spm_hw_s1_state_monitor(int en, uint32_t *status); 840 841 static inline void spm_hw_s1_state_monitor_resume(void) 842 { 843 __spm_hw_s1_state_monitor(1, NULL); 844 } 845 static inline void spm_hw_s1_state_monitor_pause(uint32_t *status) 846 { 847 __spm_hw_s1_state_monitor(0, status); 848 } 849 850 void __spm_clean_before_wfi(void); 851 int32_t __spm_wait_spm_request_ack(uint32_t spm_resource_req, 852 uint32_t timeout_us); 853 #endif /* MT_SPM_INTERNAL */ 854