1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 #include <stdio.h> 10 #include <string.h> 11 12 #include <common/debug.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <plat/common/platform.h> 16 17 #include <drivers/spm/mt_spm_resource_req.h> 18 #include <mt_plat_spm_setting.h> 19 #include <mt_spm.h> 20 #include <mt_spm_internal.h> 21 #include <mt_spm_reg.h> 22 #include <platform_def.h> 23 #include <pmic_wrap/inc/mt_spm_pmic_wrap.h> 24 25 /************************************** 26 * Define and Declare 27 **************************************/ 28 #define SPM_INIT_DONE_US 20 /* Simulation result */ 29 30 /************************************** 31 * Function and API 32 **************************************/ 33 34 wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta) 35 { 36 uint32_t i; 37 wake_reason_t wr = WR_UNKNOWN; 38 39 if (!wakesta) 40 return WR_UNKNOWN; 41 42 if (wakesta->is_abort) { 43 INFO("SPM EARLY WAKE r13 = 0x%x, ", wakesta->tr.comm.r13); 44 INFO("debug_flag = 0x%x 0x%x sw_flag = 0x%x 0x%x b_sw_flag = 0x%x 0x%x\n", 45 wakesta->tr.comm.debug_flag, wakesta->tr.comm.debug_flag1, 46 wakesta->sw_flag0, wakesta->sw_flag1, 47 wakesta->tr.comm.b_sw_flag0, wakesta->tr.comm.b_sw_flag1); 48 #ifndef MTK_PLAT_SPM_PMIC_WRAP_DUMP_UNSUPPORT 49 mt_spm_dump_pmic_warp_reg(); 50 #endif 51 } 52 53 if (wakesta->tr.comm.r12 & R12_PCM_TIMER_B) { 54 if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER_EVENT) 55 wr = WR_PCM_TIMER; 56 } 57 58 if (wakesta->tr.comm.r12 & R12_TWAM_PMSR_DVFSRC) { 59 if (wakesta->wake_misc & WAKE_MISC_DVFSRC_IRQ) 60 wr = WR_DVFSRC; 61 62 if (wakesta->wake_misc & WAKE_MISC_TWAM_IRQ_B) 63 wr = WR_TWAM; 64 65 if (wakesta->wake_misc & WAKE_MISC_SPM_ACK_CHK_WAKEUP_0) 66 wr = WR_SPM_ACK_CHK; 67 68 if (wakesta->wake_misc & WAKE_MISC_SPM_ACK_CHK_WAKEUP_1) 69 wr = WR_SPM_ACK_CHK; 70 71 if (wakesta->wake_misc & WAKE_MISC_SPM_ACK_CHK_WAKEUP_2) 72 wr = WR_SPM_ACK_CHK; 73 74 if (wakesta->wake_misc & WAKE_MISC_SPM_ACK_CHK_WAKEUP_3) 75 wr = WR_SPM_ACK_CHK; 76 77 if (wakesta->wake_misc & WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL) 78 wr = WR_SPM_ACK_CHK; 79 } 80 81 for (i = 2; i < 32; i++) { 82 if (wakesta->tr.comm.r12 & (1U << i)) 83 wr = WR_WAKE_SRC; 84 } 85 86 return wr; 87 } 88 89 void __spm_set_cpu_status(int cpu) 90 { 91 } 92 93 static void spm_code_swapping(void) 94 { 95 uint32_t con1; 96 /* int retry = 0, timeout = 5000; */ 97 98 con1 = mmio_read_32(SPM_WAKEUP_EVENT_MASK); 99 100 mmio_write_32(SPM_WAKEUP_EVENT_MASK, (con1 & ~(0x1))); 101 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); 102 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); 103 mmio_write_32(SPM_WAKEUP_EVENT_MASK, con1); 104 } 105 106 void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc) 107 { 108 unsigned char first_load_fw = true; 109 110 /* check the SPM FW is run or not */ 111 if (mmio_read_32(MD32PCM_CFGREG_SW_RSTN) & 0x1) 112 first_load_fw = false; 113 114 if (!first_load_fw) { 115 /* SPM code swapping */ 116 spm_code_swapping(); 117 118 /* Backup PCM r0 -> SPM_POWER_ON_VAL0 before `reset PCM` */ 119 mmio_write_32(SPM_POWER_ON_VAL0, 120 mmio_read_32(MD32PCM_SCU_CTRL0)); 121 } 122 123 /* disable r0 and r7 to control power */ 124 mmio_write_32(PCM_PWR_IO_EN, 0); 125 126 /* disable pcm timer after leaving FW */ 127 mmio_clrsetbits_32(PCM_CON1, SPM_REGWR_CFG_KEY, REG_PCM_TIMER_EN_LSB); 128 129 /* reset PCM */ 130 mmio_write_32(PCM_CON0, 131 SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); 132 mmio_write_32(PCM_CON0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); 133 134 /* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ 135 mmio_clrsetbits_32(PCM_CON1, REG_PCM_WDT_WAKE_LSB, 136 SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | 137 REG_SSPM_APB_P2P_EN_LSB); 138 } 139 140 void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) 141 { 142 uint32_t pmem_words; 143 uint32_t total_words; 144 uint32_t pmem_start; 145 uint32_t dmem_start; 146 uint32_t ptr; 147 148 /* tell IM where is PCM code (use slave mode if code existed) */ 149 ptr = pcmdesc->base_dma + 0x40000000; 150 pmem_words = pcmdesc->pmem_words; 151 total_words = pcmdesc->total_words; 152 pmem_start = pcmdesc->pmem_start; 153 dmem_start = pcmdesc->dmem_start; 154 155 if (mmio_read_32(MD32PCM_DMA0_SRC) != ptr || 156 mmio_read_32(MD32PCM_DMA0_DST) != pmem_start || 157 mmio_read_32(MD32PCM_DMA0_WPPT) != pmem_words || 158 mmio_read_32(MD32PCM_DMA0_WPTO) != dmem_start || 159 mmio_read_32(MD32PCM_DMA0_COUNT) != total_words || 160 mmio_read_32(MD32PCM_DMA0_CON) != 0x0003820E) { 161 mmio_write_32(MD32PCM_DMA0_SRC, ptr); 162 mmio_write_32(MD32PCM_DMA0_DST, pmem_start); 163 mmio_write_32(MD32PCM_DMA0_WPPT, pmem_words); 164 mmio_write_32(MD32PCM_DMA0_WPTO, dmem_start); 165 mmio_write_32(MD32PCM_DMA0_COUNT, total_words); 166 mmio_write_32(MD32PCM_DMA0_CON, 0x0003820E); 167 mmio_write_32(MD32PCM_DMA0_START, 0x00008000); 168 } 169 170 /* kick IM to fetch (only toggle IM_KICK) */ 171 mmio_setbits_32(PCM_CON0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); 172 } 173 174 void __spm_init_pcm_register(void) 175 { 176 /* disable r0 and r7 to control power */ 177 mmio_write_32(PCM_PWR_IO_EN, 0); 178 } 179 180 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl, 181 uint32_t resource_usage) 182 { 183 /* Auto-gen Start */ 184 185 /* SPM_SRC_REQ */ 186 mmio_write_32(SPM_SRC_REQ, 187 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 0) | 188 (((pwrctrl->reg_spm_apsrc_req | 189 !!(resource_usage & MT_SPM_DRAM_S0)) & 0x1) << 1) | 190 (((pwrctrl->reg_spm_ddren_req | 191 !!(resource_usage & MT_SPM_DRAM_S1)) & 0x1) << 2) | 192 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 3) | 193 (((pwrctrl->reg_spm_emi_req | 194 !!(resource_usage & MT_SPM_EMI)) & 0x1) << 4) | 195 (((pwrctrl->reg_spm_f26m_req | 196 !!(resource_usage & (MT_SPM_26M | MT_SPM_XO_FPM))) & 0x1) << 5) | 197 (((pwrctrl->reg_spm_infra_req | 198 !!(resource_usage & MT_SPM_INFRA)) & 0x1) << 6) | 199 (((pwrctrl->reg_spm_pmic_req | 200 !!(resource_usage & MT_SPM_PMIC)) & 0x1) << 7) | 201 (((uint32_t)pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) | 202 (((uint32_t)pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) | 203 (((uint32_t)pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 10) | 204 ((((uint32_t)pwrctrl->reg_spm_vcore_req | 205 !!(resource_usage & MT_SPM_VCORE)) & 0x1) << 11) | 206 ((((uint32_t)pwrctrl->reg_spm_vrf18_req | 207 !!(resource_usage & MT_SPM_SYSPLL)) & 0x1) << 12) | 208 (((uint32_t)pwrctrl->adsp_mailbox_state & 0x1) << 16) | 209 (((uint32_t)pwrctrl->apsrc_state & 0x1) << 17) | 210 (((uint32_t)pwrctrl->ddren_state & 0x1) << 18) | 211 (((uint32_t)pwrctrl->dvfs_state & 0x1) << 19) | 212 (((uint32_t)pwrctrl->emi_state & 0x1) << 20) | 213 (((uint32_t)pwrctrl->f26m_state & 0x1) << 21) | 214 (((uint32_t)pwrctrl->infra_state & 0x1) << 22) | 215 (((uint32_t)pwrctrl->pmic_state & 0x1) << 23) | 216 (((uint32_t)pwrctrl->scp_mailbox_state & 0x1) << 24) | 217 (((uint32_t)pwrctrl->sspm_mailbox_state & 0x1) << 25) | 218 (((uint32_t)pwrctrl->sw_mailbox_state & 0x1) << 26) | 219 (((uint32_t)pwrctrl->vcore_state & 0x1) << 27) | 220 (((uint32_t)pwrctrl->vrf18_state & 0x1) << 28)); 221 222 /* SPM_SRC_MASK_0 */ 223 mmio_write_32(SPM_SRC_MASK_0, 224 (((uint32_t)pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 0) | 225 (((uint32_t)pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 1) | 226 (((uint32_t)pwrctrl->reg_apu_emi_req_mask_b & 0x1) << 2) | 227 (((uint32_t)pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 3) | 228 (((uint32_t)pwrctrl->reg_apu_pmic_req_mask_b & 0x1) << 4) | 229 (((uint32_t)pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 5) | 230 (((uint32_t)pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 6) | 231 (((uint32_t)pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | 232 (((uint32_t)pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 8) | 233 (((uint32_t)pwrctrl->reg_audio_dsp_emi_req_mask_b & 0x1) << 9) | 234 (((uint32_t)pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 10) | 235 (((uint32_t)pwrctrl->reg_audio_dsp_pmic_req_mask_b & 0x1) << 11) | 236 (((uint32_t)pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 12) | 237 (((uint32_t)pwrctrl->reg_audio_dsp_vcore_req_mask_b & 0x1) << 13) | 238 (((uint32_t)pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 14) | 239 (((uint32_t)pwrctrl->reg_cam_apsrc_req_mask_b & 0x1) << 15) | 240 (((uint32_t)pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 16) | 241 (((uint32_t)pwrctrl->reg_cam_emi_req_mask_b & 0x1) << 17) | 242 (((uint32_t)pwrctrl->reg_cam_infra_req_mask_b & 0x1) << 18) | 243 (((uint32_t)pwrctrl->reg_cam_pmic_req_mask_b & 0x1) << 19) | 244 (((uint32_t)pwrctrl->reg_cam_srcclkena_mask_b & 0x1) << 20) | 245 (((uint32_t)pwrctrl->reg_cam_vrf18_req_mask_b & 0x1) << 21) | 246 (((uint32_t)pwrctrl->reg_mdp_emi_req_mask_b & 0x1) << 22)); 247 248 /* SPM_SRC_MASK_1 */ 249 mmio_write_32(SPM_SRC_MASK_1, 250 (((uint32_t)pwrctrl->reg_ccif_apsrc_req_mask_b & 0xfff) << 0) | 251 (((uint32_t)pwrctrl->reg_ccif_emi_req_mask_b & 0xfff) << 12)); 252 253 /* SPM_SRC_MASK_2 */ 254 mmio_write_32(SPM_SRC_MASK_2, 255 (((uint32_t)pwrctrl->reg_ccif_infra_req_mask_b & 0xfff) << 0) | 256 (((uint32_t)pwrctrl->reg_ccif_pmic_req_mask_b & 0xfff) << 12)); 257 258 /* SPM_SRC_MASK_3 */ 259 mmio_write_32(SPM_SRC_MASK_3, 260 (((uint32_t)pwrctrl->reg_ccif_srcclkena_mask_b & 0xfff) << 0) | 261 (((uint32_t)pwrctrl->reg_ccif_vrf18_req_mask_b & 0xfff) << 12) | 262 (((uint32_t)pwrctrl->reg_ccu_apsrc_req_mask_b & 0x1) << 24) | 263 (((uint32_t)pwrctrl->reg_ccu_ddren_req_mask_b & 0x1) << 25) | 264 (((uint32_t)pwrctrl->reg_ccu_emi_req_mask_b & 0x1) << 26) | 265 (((uint32_t)pwrctrl->reg_ccu_infra_req_mask_b & 0x1) << 27) | 266 (((uint32_t)pwrctrl->reg_ccu_pmic_req_mask_b & 0x1) << 28) | 267 (((uint32_t)pwrctrl->reg_ccu_srcclkena_mask_b & 0x1) << 29) | 268 (((uint32_t)pwrctrl->reg_ccu_vrf18_req_mask_b & 0x1) << 30) | 269 (((uint32_t)pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 31)); 270 271 /* SPM_SRC_MASK_4 */ 272 mmio_write_32(SPM_SRC_MASK_4, 273 (((uint32_t)pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 0) | 274 (((uint32_t)pwrctrl->reg_cg_check_emi_req_mask_b & 0x1) << 1) | 275 (((uint32_t)pwrctrl->reg_cg_check_infra_req_mask_b & 0x1) << 2) | 276 (((uint32_t)pwrctrl->reg_cg_check_pmic_req_mask_b & 0x1) << 3) | 277 (((uint32_t)pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 4) | 278 (((uint32_t)pwrctrl->reg_cg_check_vcore_req_mask_b & 0x1) << 5) | 279 (((uint32_t)pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 6) | 280 (((uint32_t)pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 7) | 281 (((uint32_t)pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 8) | 282 (((uint32_t)pwrctrl->reg_conn_emi_req_mask_b & 0x1) << 9) | 283 (((uint32_t)pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 10) | 284 (((uint32_t)pwrctrl->reg_conn_pmic_req_mask_b & 0x1) << 11) | 285 (((uint32_t)pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | 286 (((uint32_t)pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | 287 (((uint32_t)pwrctrl->reg_conn_vcore_req_mask_b & 0x1) << 14) | 288 (((uint32_t)pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 15) | 289 (((uint32_t)pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 16) | 290 (((uint32_t)pwrctrl->reg_cpueb_ddren_req_mask_b & 0x1) << 17) | 291 (((uint32_t)pwrctrl->reg_cpueb_emi_req_mask_b & 0x1) << 18) | 292 (((uint32_t)pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 19) | 293 (((uint32_t)pwrctrl->reg_cpueb_pmic_req_mask_b & 0x1) << 20) | 294 (((uint32_t)pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 21) | 295 (((uint32_t)pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 22) | 296 (((uint32_t)pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 23) | 297 (((uint32_t)pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 24) | 298 (((uint32_t)pwrctrl->reg_disp0_emi_req_mask_b & 0x1) << 25) | 299 (((uint32_t)pwrctrl->reg_disp0_infra_req_mask_b & 0x1) << 26) | 300 (((uint32_t)pwrctrl->reg_disp0_pmic_req_mask_b & 0x1) << 27) | 301 (((uint32_t)pwrctrl->reg_disp0_srcclkena_mask_b & 0x1) << 28) | 302 (((uint32_t)pwrctrl->reg_disp0_vrf18_req_mask_b & 0x1) << 29) | 303 (((uint32_t)pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 30) | 304 (((uint32_t)pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 31)); 305 306 /* SPM_SRC_MASK_5 */ 307 mmio_write_32(SPM_SRC_MASK_5, 308 (((uint32_t)pwrctrl->reg_disp1_emi_req_mask_b & 0x1) << 0) | 309 (((uint32_t)pwrctrl->reg_disp1_infra_req_mask_b & 0x1) << 1) | 310 (((uint32_t)pwrctrl->reg_disp1_pmic_req_mask_b & 0x1) << 2) | 311 (((uint32_t)pwrctrl->reg_disp1_srcclkena_mask_b & 0x1) << 3) | 312 (((uint32_t)pwrctrl->reg_disp1_vrf18_req_mask_b & 0x1) << 4) | 313 (((uint32_t)pwrctrl->reg_dpm_apsrc_req_mask_b & 0xf) << 5) | 314 (((uint32_t)pwrctrl->reg_dpm_ddren_req_mask_b & 0xf) << 9) | 315 (((uint32_t)pwrctrl->reg_dpm_emi_req_mask_b & 0xf) << 13) | 316 (((uint32_t)pwrctrl->reg_dpm_infra_req_mask_b & 0xf) << 17) | 317 (((uint32_t)pwrctrl->reg_dpm_pmic_req_mask_b & 0xf) << 21) | 318 (((uint32_t)pwrctrl->reg_dpm_srcclkena_mask_b & 0xf) << 25)); 319 320 /* SPM_SRC_MASK_6 */ 321 mmio_write_32(SPM_SRC_MASK_6, 322 (((uint32_t)pwrctrl->reg_dpm_vcore_req_mask_b & 0xf) << 0) | 323 (((uint32_t)pwrctrl->reg_dpm_vrf18_req_mask_b & 0xf) << 4) | 324 (((uint32_t)pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 8) | 325 (((uint32_t)pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9) | 326 (((uint32_t)pwrctrl->reg_dpmaif_emi_req_mask_b & 0x1) << 10) | 327 (((uint32_t)pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 11) | 328 (((uint32_t)pwrctrl->reg_dpmaif_pmic_req_mask_b & 0x1) << 12) | 329 (((uint32_t)pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 13) | 330 (((uint32_t)pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 14) | 331 (((uint32_t)pwrctrl->reg_dvfsrc_level_req_mask_b & 0x1) << 15) | 332 (((uint32_t)pwrctrl->reg_emisys_apsrc_req_mask_b & 0x1) << 16) | 333 (((uint32_t)pwrctrl->reg_emisys_ddren_req_mask_b & 0x1) << 17) | 334 (((uint32_t)pwrctrl->reg_emisys_emi_req_mask_b & 0x1) << 18) | 335 (((uint32_t)pwrctrl->reg_gce_d_apsrc_req_mask_b & 0x1) << 19) | 336 (((uint32_t)pwrctrl->reg_gce_d_ddren_req_mask_b & 0x1) << 20) | 337 (((uint32_t)pwrctrl->reg_gce_d_emi_req_mask_b & 0x1) << 21) | 338 (((uint32_t)pwrctrl->reg_gce_d_infra_req_mask_b & 0x1) << 22) | 339 (((uint32_t)pwrctrl->reg_gce_d_pmic_req_mask_b & 0x1) << 23) | 340 (((uint32_t)pwrctrl->reg_gce_d_srcclkena_mask_b & 0x1) << 24) | 341 (((uint32_t)pwrctrl->reg_gce_d_vrf18_req_mask_b & 0x1) << 25) | 342 (((uint32_t)pwrctrl->reg_gce_m_apsrc_req_mask_b & 0x1) << 26) | 343 (((uint32_t)pwrctrl->reg_gce_m_ddren_req_mask_b & 0x1) << 27) | 344 (((uint32_t)pwrctrl->reg_gce_m_emi_req_mask_b & 0x1) << 28) | 345 (((uint32_t)pwrctrl->reg_gce_m_infra_req_mask_b & 0x1) << 29) | 346 (((uint32_t)pwrctrl->reg_gce_m_pmic_req_mask_b & 0x1) << 30) | 347 (((uint32_t)pwrctrl->reg_gce_m_srcclkena_mask_b & 0x1) << 31)); 348 349 /* SPM_SRC_MASK_7 */ 350 mmio_write_32(SPM_SRC_MASK_7, 351 (((uint32_t)pwrctrl->reg_gce_m_vrf18_req_mask_b & 0x1) << 0) | 352 (((uint32_t)pwrctrl->reg_gpueb_apsrc_req_mask_b & 0x1) << 1) | 353 (((uint32_t)pwrctrl->reg_gpueb_ddren_req_mask_b & 0x1) << 2) | 354 (((uint32_t)pwrctrl->reg_gpueb_emi_req_mask_b & 0x1) << 3) | 355 (((uint32_t)pwrctrl->reg_gpueb_infra_req_mask_b & 0x1) << 4) | 356 (((uint32_t)pwrctrl->reg_gpueb_pmic_req_mask_b & 0x1) << 5) | 357 (((uint32_t)pwrctrl->reg_gpueb_srcclkena_mask_b & 0x1) << 6) | 358 (((uint32_t)pwrctrl->reg_gpueb_vrf18_req_mask_b & 0x1) << 7) | 359 (((uint32_t)pwrctrl->reg_hwccf_apsrc_req_mask_b & 0x1) << 8) | 360 (((uint32_t)pwrctrl->reg_hwccf_ddren_req_mask_b & 0x1) << 9) | 361 (((uint32_t)pwrctrl->reg_hwccf_emi_req_mask_b & 0x1) << 10) | 362 (((uint32_t)pwrctrl->reg_hwccf_infra_req_mask_b & 0x1) << 11) | 363 (((uint32_t)pwrctrl->reg_hwccf_pmic_req_mask_b & 0x1) << 12) | 364 (((uint32_t)pwrctrl->reg_hwccf_srcclkena_mask_b & 0x1) << 13) | 365 (((uint32_t)pwrctrl->reg_hwccf_vcore_req_mask_b & 0x1) << 14) | 366 (((uint32_t)pwrctrl->reg_hwccf_vrf18_req_mask_b & 0x1) << 15) | 367 (((uint32_t)pwrctrl->reg_img_apsrc_req_mask_b & 0x1) << 16) | 368 (((uint32_t)pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 17) | 369 (((uint32_t)pwrctrl->reg_img_emi_req_mask_b & 0x1) << 18) | 370 (((uint32_t)pwrctrl->reg_img_infra_req_mask_b & 0x1) << 19) | 371 (((uint32_t)pwrctrl->reg_img_pmic_req_mask_b & 0x1) << 20) | 372 (((uint32_t)pwrctrl->reg_img_srcclkena_mask_b & 0x1) << 21) | 373 (((uint32_t)pwrctrl->reg_img_vrf18_req_mask_b & 0x1) << 22) | 374 (((uint32_t)pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 23) | 375 (((uint32_t)pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 24) | 376 (((uint32_t)pwrctrl->reg_infrasys_emi_req_mask_b & 0x1) << 25) | 377 (((uint32_t)pwrctrl->reg_ipic_infra_req_mask_b & 0x1) << 26) | 378 (((uint32_t)pwrctrl->reg_ipic_vrf18_req_mask_b & 0x1) << 27) | 379 (((uint32_t)pwrctrl->reg_mcu_apsrc_req_mask_b & 0x1) << 28) | 380 (((uint32_t)pwrctrl->reg_mcu_ddren_req_mask_b & 0x1) << 29) | 381 (((uint32_t)pwrctrl->reg_mcu_emi_req_mask_b & 0x1) << 30)); 382 383 /* SPM_SRC_MASK_8 */ 384 mmio_write_32(SPM_SRC_MASK_8, 385 (((uint32_t)pwrctrl->reg_mcusys_apsrc_req_mask_b & 0xff) << 0) | 386 (((uint32_t)pwrctrl->reg_mcusys_ddren_req_mask_b & 0xff) << 8) | 387 (((uint32_t)pwrctrl->reg_mcusys_emi_req_mask_b & 0xff) << 16) | 388 (((uint32_t)pwrctrl->reg_mcusys_infra_req_mask_b & 0xff) << 24)); 389 390 /* SPM_SRC_MASK_9 */ 391 mmio_write_32(SPM_SRC_MASK_9, 392 (((uint32_t)pwrctrl->reg_mcusys_pmic_req_mask_b & 0xff) << 0) | 393 (((uint32_t)pwrctrl->reg_mcusys_srcclkena_mask_b & 0xff) << 8) | 394 (((uint32_t)pwrctrl->reg_mcusys_vrf18_req_mask_b & 0xff) << 16) | 395 (((uint32_t)pwrctrl->reg_md_apsrc_req_mask_b & 0x1) << 24) | 396 (((uint32_t)pwrctrl->reg_md_ddren_req_mask_b & 0x1) << 25) | 397 (((uint32_t)pwrctrl->reg_md_emi_req_mask_b & 0x1) << 26) | 398 (((uint32_t)pwrctrl->reg_md_infra_req_mask_b & 0x1) << 27) | 399 (((uint32_t)pwrctrl->reg_md_pmic_req_mask_b & 0x1) << 28) | 400 (((uint32_t)pwrctrl->reg_md_srcclkena_mask_b & 0x1) << 29) | 401 (((uint32_t)pwrctrl->reg_md_srcclkena1_mask_b & 0x1) << 30) | 402 (((uint32_t)pwrctrl->reg_md_vcore_req_mask_b & 0x1) << 31)); 403 404 /* SPM_SRC_MASK_10 */ 405 mmio_write_32(SPM_SRC_MASK_10, 406 (((uint32_t)pwrctrl->reg_md_vrf18_req_mask_b & 0x1) << 0) | 407 (((uint32_t)pwrctrl->reg_mdp_apsrc_req_mask_b & 0x1) << 1) | 408 (((uint32_t)pwrctrl->reg_mdp_ddren_req_mask_b & 0x1) << 2) | 409 (((uint32_t)pwrctrl->reg_mm_proc_apsrc_req_mask_b & 0x1) << 3) | 410 (((uint32_t)pwrctrl->reg_mm_proc_ddren_req_mask_b & 0x1) << 4) | 411 (((uint32_t)pwrctrl->reg_mm_proc_emi_req_mask_b & 0x1) << 5) | 412 (((uint32_t)pwrctrl->reg_mm_proc_infra_req_mask_b & 0x1) << 6) | 413 (((uint32_t)pwrctrl->reg_mm_proc_pmic_req_mask_b & 0x1) << 7) | 414 (((uint32_t)pwrctrl->reg_mm_proc_srcclkena_mask_b & 0x1) << 8) | 415 (((uint32_t)pwrctrl->reg_mm_proc_vrf18_req_mask_b & 0x1) << 9) | 416 (((uint32_t)pwrctrl->reg_mmsys_apsrc_req_mask_b & 0x1) << 10) | 417 (((uint32_t)pwrctrl->reg_mmsys_ddren_req_mask_b & 0x1) << 11) | 418 (((uint32_t)pwrctrl->reg_mmsys_vrf18_req_mask_b & 0x1) << 12) | 419 (((uint32_t)pwrctrl->reg_pcie0_apsrc_req_mask_b & 0x1) << 13) | 420 (((uint32_t)pwrctrl->reg_pcie0_ddren_req_mask_b & 0x1) << 14) | 421 (((uint32_t)pwrctrl->reg_pcie0_infra_req_mask_b & 0x1) << 15) | 422 (((uint32_t)pwrctrl->reg_pcie0_srcclkena_mask_b & 0x1) << 16) | 423 (((uint32_t)pwrctrl->reg_pcie0_vrf18_req_mask_b & 0x1) << 17) | 424 (((uint32_t)pwrctrl->reg_pcie1_apsrc_req_mask_b & 0x1) << 18) | 425 (((uint32_t)pwrctrl->reg_pcie1_ddren_req_mask_b & 0x1) << 19) | 426 (((uint32_t)pwrctrl->reg_pcie1_infra_req_mask_b & 0x1) << 20) | 427 (((uint32_t)pwrctrl->reg_pcie1_srcclkena_mask_b & 0x1) << 21) | 428 (((uint32_t)pwrctrl->reg_pcie1_vrf18_req_mask_b & 0x1) << 22) | 429 (((uint32_t)pwrctrl->reg_perisys_apsrc_req_mask_b & 0x1) << 23) | 430 (((uint32_t)pwrctrl->reg_perisys_ddren_req_mask_b & 0x1) << 24) | 431 (((uint32_t)pwrctrl->reg_perisys_emi_req_mask_b & 0x1) << 25) | 432 (((uint32_t)pwrctrl->reg_perisys_infra_req_mask_b & 0x1) << 26) | 433 (((uint32_t)pwrctrl->reg_perisys_pmic_req_mask_b & 0x1) << 27) | 434 (((uint32_t)pwrctrl->reg_perisys_srcclkena_mask_b & 0x1) << 28) | 435 (((uint32_t)pwrctrl->reg_perisys_vcore_req_mask_b & 0x1) << 29) | 436 (((uint32_t)pwrctrl->reg_perisys_vrf18_req_mask_b & 0x1) << 30) | 437 (((uint32_t)pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 31)); 438 439 /* SPM_SRC_MASK_11 */ 440 mmio_write_32(SPM_SRC_MASK_11, 441 (((uint32_t)pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 0) | 442 (((uint32_t)pwrctrl->reg_scp_emi_req_mask_b & 0x1) << 1) | 443 (((uint32_t)pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 2) | 444 (((uint32_t)pwrctrl->reg_scp_pmic_req_mask_b & 0x1) << 3) | 445 (((uint32_t)pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 4) | 446 (((uint32_t)pwrctrl->reg_scp_vcore_req_mask_b & 0x1) << 5) | 447 (((uint32_t)pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 6) | 448 (((uint32_t)pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x3) << 7) | 449 (((uint32_t)pwrctrl->reg_srcclkeni_pmic_req_mask_b & 0x3) << 9) | 450 (((uint32_t)pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x3) << 11) | 451 (((uint32_t)pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 13) | 452 (((uint32_t)pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 14) | 453 (((uint32_t)pwrctrl->reg_sspm_emi_req_mask_b & 0x1) << 15) | 454 (((uint32_t)pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 16) | 455 (((uint32_t)pwrctrl->reg_sspm_pmic_req_mask_b & 0x1) << 17) | 456 (((uint32_t)pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 18) | 457 (((uint32_t)pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 19) | 458 (((uint32_t)pwrctrl->reg_ssr_apsrc_req_mask_b & 0x1) << 20) | 459 (((uint32_t)pwrctrl->reg_ssr_ddren_req_mask_b & 0x1) << 21) | 460 (((uint32_t)pwrctrl->reg_ssr_emi_req_mask_b & 0x1) << 22) | 461 (((uint32_t)pwrctrl->reg_ssr_infra_req_mask_b & 0x1) << 23) | 462 (((uint32_t)pwrctrl->reg_ssr_pmic_req_mask_b & 0x1) << 24) | 463 (((uint32_t)pwrctrl->reg_ssr_srcclkena_mask_b & 0x1) << 25) | 464 (((uint32_t)pwrctrl->reg_ssr_vrf18_req_mask_b & 0x1) << 26) | 465 (((uint32_t)pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 27) | 466 (((uint32_t)pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 28) | 467 (((uint32_t)pwrctrl->reg_ufs_emi_req_mask_b & 0x1) << 29) | 468 (((uint32_t)pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 30) | 469 (((uint32_t)pwrctrl->reg_ufs_pmic_req_mask_b & 0x1) << 31)); 470 471 /* SPM_SRC_MASK_12 */ 472 mmio_write_32(SPM_SRC_MASK_12, 473 (((uint32_t)pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 0) | 474 (((uint32_t)pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 1) | 475 (((uint32_t)pwrctrl->reg_vdec_apsrc_req_mask_b & 0x1) << 2) | 476 (((uint32_t)pwrctrl->reg_vdec_ddren_req_mask_b & 0x1) << 3) | 477 (((uint32_t)pwrctrl->reg_vdec_emi_req_mask_b & 0x1) << 4) | 478 (((uint32_t)pwrctrl->reg_vdec_infra_req_mask_b & 0x1) << 5) | 479 (((uint32_t)pwrctrl->reg_vdec_pmic_req_mask_b & 0x1) << 6) | 480 (((uint32_t)pwrctrl->reg_vdec_srcclkena_mask_b & 0x1) << 7) | 481 (((uint32_t)pwrctrl->reg_vdec_vrf18_req_mask_b & 0x1) << 8) | 482 (((uint32_t)pwrctrl->reg_venc_apsrc_req_mask_b & 0x1) << 9) | 483 (((uint32_t)pwrctrl->reg_venc_ddren_req_mask_b & 0x1) << 10) | 484 (((uint32_t)pwrctrl->reg_venc_emi_req_mask_b & 0x1) << 11) | 485 (((uint32_t)pwrctrl->reg_venc_infra_req_mask_b & 0x1) << 12) | 486 (((uint32_t)pwrctrl->reg_venc_pmic_req_mask_b & 0x1) << 13) | 487 (((uint32_t)pwrctrl->reg_venc_srcclkena_mask_b & 0x1) << 14) | 488 (((uint32_t)pwrctrl->reg_venc_vrf18_req_mask_b & 0x1) << 15) | 489 (((uint32_t)pwrctrl->reg_ipe_apsrc_req_mask_b & 0x1) << 16) | 490 (((uint32_t)pwrctrl->reg_ipe_ddren_req_mask_b & 0x1) << 17) | 491 (((uint32_t)pwrctrl->reg_ipe_emi_req_mask_b & 0x1) << 18) | 492 (((uint32_t)pwrctrl->reg_ipe_infra_req_mask_b & 0x1) << 19) | 493 (((uint32_t)pwrctrl->reg_ipe_pmic_req_mask_b & 0x1) << 20) | 494 (((uint32_t)pwrctrl->reg_ipe_srcclkena_mask_b & 0x1) << 21) | 495 (((uint32_t)pwrctrl->reg_ipe_vrf18_req_mask_b & 0x1) << 22) | 496 (((uint32_t)pwrctrl->reg_ufs_vcore_req_mask_b & 0x1) << 23)); 497 498 /* SPM_EVENT_CON_MISC */ 499 mmio_write_32(SPM_EVENT_CON_MISC, 500 (((uint32_t)pwrctrl->reg_srcclken_fast_resp & 0x1) << 0) | 501 (((uint32_t)pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 1)); 502 503 /* SPM_WAKEUP_EVENT_MASK */ 504 mmio_write_32(SPM_WAKEUP_EVENT_MASK, 505 (((uint32_t)pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); 506 507 /* SPM_WAKEUP_EVENT_EXT_MASK */ 508 mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, 509 (((uint32_t)pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); 510 /* Auto-gen End */ 511 } 512 513 #define CHECK_ONE (0xffffffff) 514 #define CHECK_ZERO (0x0) 515 static int32_t __spm_check_ack(uint32_t reg, uint32_t mask, uint32_t check_en) 516 { 517 uint32_t val; 518 519 val = mmio_read_32(reg); 520 if ((val & mask) == (mask & check_en)) 521 return 0; 522 return -1; 523 } 524 525 int32_t __spm_wait_spm_request_ack(uint32_t spm_resource_req, 526 uint32_t timeout_us) 527 { 528 uint32_t spm_ctrl0_mask, spm_ctrl1_mask; 529 int32_t ret, retry; 530 531 if (spm_resource_req == 0) 532 return 0; 533 534 spm_ctrl0_mask = 0; 535 spm_ctrl1_mask = 0; 536 537 if (spm_resource_req & (MT_SPM_XO_FPM | MT_SPM_26M)) 538 spm_ctrl0_mask |= CTRL0_SC_MD26M_CK_OFF; 539 540 if (spm_resource_req & MT_SPM_VCORE) 541 spm_ctrl1_mask |= CTRL1_SPM_VCORE_INTERNAL_ACK; 542 if (spm_resource_req & MT_SPM_PMIC) 543 spm_ctrl1_mask |= CTRL1_SPM_PMIC_INTERNAL_ACK; 544 if (spm_resource_req & MT_SPM_INFRA) 545 spm_ctrl1_mask |= CTRL1_SPM_INFRA_INTERNAL_ACK; 546 if (spm_resource_req & MT_SPM_SYSPLL) 547 spm_ctrl1_mask |= CTRL1_SPM_VRF18_INTERNAL_ACK; 548 if (spm_resource_req & MT_SPM_EMI) 549 spm_ctrl1_mask |= CTRL1_SPM_EMI_INTERNAL_ACK; 550 if (spm_resource_req & MT_SPM_DRAM_S0) 551 spm_ctrl1_mask |= CTRL1_SPM_APSRC_INTERNAL_ACK; 552 if (spm_resource_req & MT_SPM_DRAM_S1) 553 spm_ctrl1_mask |= CTRL1_SPM_DDREN_INTERNAL_ACK; 554 555 retry = -1; 556 ret = 0; 557 558 while (retry++ < timeout_us) { 559 udelay(1); 560 if (spm_ctrl0_mask != 0) { 561 ret = __spm_check_ack(MD32PCM_SCU_CTRL0, spm_ctrl0_mask, 562 CHECK_ZERO); 563 if (ret) 564 continue; 565 } 566 if (spm_ctrl1_mask != 0) { 567 ret = __spm_check_ack(MD32PCM_SCU_CTRL1, spm_ctrl1_mask, 568 CHECK_ONE); 569 if (ret) 570 continue; 571 } 572 break; 573 } 574 575 return ret; 576 } 577 578 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 579 { 580 uint32_t val, mask, isr; 581 582 /* toggle event counter clear */ 583 mmio_write_32(SPM_EVENT_COUNTER_CLEAR, REG_SPM_EVENT_COUNTER_CLR_LSB); 584 /* toggle for reset SYS TIMER start point */ 585 mmio_write_32(SYS_TIMER_CON, 586 mmio_read_32(SYS_TIMER_CON) | SYS_TIMER_START_EN_LSB); 587 588 if (pwrctrl->timer_val_cust == 0) 589 val = pwrctrl->timer_val ? pwrctrl->timer_val : 590 PCM_TIMER_SUSPEND; 591 else 592 val = pwrctrl->timer_val_cust; 593 594 mmio_write_32(PCM_TIMER_VAL, val); 595 mmio_write_32(PCM_CON1, mmio_read_32(PCM_CON1) | SPM_REGWR_CFG_KEY | 596 REG_PCM_TIMER_EN_LSB); 597 598 /* unmask AP wakeup source */ 599 if (pwrctrl->wake_src_cust == 0) 600 mask = pwrctrl->wake_src; 601 else 602 mask = pwrctrl->wake_src_cust; 603 604 if (pwrctrl->reg_csyspwrup_ack_mask) 605 mask &= ~R12_CSYSPWREQ_B; 606 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); 607 608 /* unmask SPM ISR (keep TWAM setting) */ 609 isr = mmio_read_32(SPM_IRQ_MASK); 610 mmio_write_32(SPM_IRQ_MASK, isr | ISRM_RET_IRQ_AUX); 611 612 /* toggle event counter clear */ 613 mmio_write_32(SPM_EVENT_COUNTER_CLEAR, 0); 614 /* toggle for reset SYS TIMER start point */ 615 mmio_write_32(SYS_TIMER_CON, 616 mmio_read_32(SYS_TIMER_CON) & ~SYS_TIMER_START_EN_LSB); 617 } 618 619 void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl) 620 { 621 #if SPM_FW_NO_RESUME 622 /* do Nothing */ 623 #else 624 pwrctrl->pcm_flags1 |= SPM_FLAG1_DISABLE_NO_RESUME; 625 #endif 626 } 627 628 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) 629 { 630 /* set PCM flags and data */ 631 uint32_t pcm_flags = 632 (pwrctrl->pcm_flags & ~pwrctrl->pcm_flags_cust_clr) | 633 pwrctrl->pcm_flags_cust_set; 634 uint32_t pcm_flags1 = 635 (pwrctrl->pcm_flags1 & ~pwrctrl->pcm_flags1_cust_clr) | 636 pwrctrl->pcm_flags1_cust_set; 637 638 mmio_write_32(SPM_SW_FLAG_0, pcm_flags); 639 640 mmio_write_32(SPM_SW_FLAG_1, pcm_flags1); 641 642 mmio_write_32(PCM_WDT_LATCH_SPARE_7, pcm_flags); 643 644 mmio_write_32(PCM_WDT_LATCH_SPARE_5, pcm_flags1); 645 } 646 647 void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) 648 { 649 uint32_t con0; 650 651 /* Waiting for loading SPMFW done*/ 652 while (mmio_read_32(MD32PCM_DMA0_RLCT) != 0x0) 653 ; 654 655 __spm_set_pcm_flags(pwrctrl); 656 657 /* kick PCM to run (only toggle PCM_KICK) */ 658 con0 = mmio_read_32(PCM_CON0); 659 mmio_write_32(PCM_CON0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); 660 /* reset md32pcm */ 661 con0 = mmio_read_32(MD32PCM_CFGREG_SW_RSTN); 662 mmio_write_32(MD32PCM_CFGREG_SW_RSTN, con0 | 0x1); 663 664 /* Waiting for SPM init done and entering WFI*/ 665 udelay(SPM_INIT_DONE_US); 666 } 667 668 void __spm_get_wakeup_status(struct wake_status *wakesta, 669 unsigned int ext_status) 670 { 671 /* get wakeup event */ 672 wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); /* backup of PCM_REG12_DATA */ 673 wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_EXT_STA); 674 wakesta->tr.comm.raw_sta = mmio_read_32(SPM_WAKEUP_STA); 675 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); 676 wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA); 677 wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA); 678 wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC); /* backup of SPM_WAKEUP_MISC */ 679 680 /* get sleep time */ 681 wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER); /* backup of PCM_TIMER_OUT */ 682 683 /* get other SYS and co-clock status */ 684 wakesta->tr.comm.r13 = mmio_read_32(MD32PCM_SCU_STA0); 685 wakesta->tr.comm.req_sta0 = mmio_read_32(SPM_REQ_STA_0); 686 wakesta->tr.comm.req_sta1 = mmio_read_32(SPM_REQ_STA_1); 687 wakesta->tr.comm.req_sta2 = mmio_read_32(SPM_REQ_STA_2); 688 wakesta->tr.comm.req_sta3 = mmio_read_32(SPM_REQ_STA_3); 689 wakesta->tr.comm.req_sta4 = mmio_read_32(SPM_REQ_STA_4); 690 wakesta->tr.comm.req_sta5 = mmio_read_32(SPM_REQ_STA_5); 691 wakesta->tr.comm.req_sta6 = mmio_read_32(SPM_REQ_STA_6); 692 wakesta->tr.comm.req_sta7 = mmio_read_32(SPM_REQ_STA_7); 693 wakesta->tr.comm.req_sta8 = mmio_read_32(SPM_REQ_STA_8); 694 wakesta->tr.comm.req_sta9 = mmio_read_32(SPM_REQ_STA_9); 695 wakesta->tr.comm.req_sta10 = mmio_read_32(SPM_REQ_STA_10); 696 wakesta->tr.comm.req_sta11 = mmio_read_32(SPM_REQ_STA_11); 697 wakesta->tr.comm.req_sta12 = mmio_read_32(SPM_REQ_STA_12); 698 699 /* get debug flag for PCM execution check */ 700 wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0); 701 wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1); 702 703 /* get backup SW flag status */ 704 wakesta->tr.comm.b_sw_flag0 = mmio_read_32(PCM_WDT_LATCH_SPARE_7); 705 wakesta->tr.comm.b_sw_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_5); 706 707 /* get ISR status */ 708 wakesta->isr = mmio_read_32(SPM_IRQ_STA); 709 710 /* get SW flag status */ 711 wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0); 712 wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1); 713 714 /* check abort */ 715 wakesta->is_abort = wakesta->tr.comm.debug_flag1 & DEBUG_ABORT_MASK_1; 716 } 717 718 void __spm_clean_after_wakeup(void) 719 { 720 /* 721 * Copy SPM_WAKEUP_STA to SPM_BK_WAKE_EVENT 722 * before clear SPM_WAKEUP_STA 723 * 724 * CPU dormant driver @kernel will copy edge-trig IRQ pending 725 * (recorded @SPM_BK_WAKE_EVENT) to GIC 726 */ 727 mmio_write_32(SPM_BK_WAKE_EVENT, mmio_read_32(SPM_WAKEUP_STA) | 728 mmio_read_32(SPM_BK_WAKE_EVENT)); 729 730 /* 731 * [Vcorefs] can not switch back to POWER_ON_VAL0 here, 732 * the FW stays in VCORE DVFS which use r0 to Ctrl MEM 733 */ 734 /* disable r0 and r7 to control power */ 735 /* mmio_write_32(PCM_PWR_IO_EN, 0); */ 736 737 /* clean CPU wakeup event */ 738 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); 739 740 /* 741 * [Vcorefs] not disable pcm timer here, due to the 742 * following vcore dvfs will use it for latency check 743 */ 744 /* clean PCM timer event */ 745 /* 746 * mmio_write_32(PCM_CON1, SPM_REGWR_CFG_KEY | 747 * (mmio_read_32(PCM_CON1) & ~PCM_TIMER_EN_LSB)); 748 */ 749 750 /* clean wakeup event raw status (for edge trigger event) */ 751 mmio_write_32(SPM_WAKEUP_EVENT_MASK, 752 0xefffffff); /* bit[28] for cpu wake up event */ 753 754 /* clean ISR status (except TWAM) */ 755 mmio_write_32(SPM_IRQ_MASK, 756 mmio_read_32(SPM_IRQ_MASK) | ISRM_ALL_EXC_TWAM); 757 mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); 758 mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); 759 } 760 761 void __spm_set_pcm_wdt(int en) 762 { 763 /* enable PCM WDT (normal mode) to start count if needed */ 764 if (en) { 765 uint32_t con1; 766 767 con1 = mmio_read_32(PCM_CON1) & ~(REG_PCM_WDT_WAKE_LSB); 768 mmio_write_32(PCM_CON1, SPM_REGWR_CFG_KEY | con1); 769 770 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) 771 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); 772 mmio_write_32(PCM_WDT_VAL, 773 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); 774 mmio_write_32(PCM_CON1, 775 con1 | SPM_REGWR_CFG_KEY | REG_PCM_WDT_EN_LSB); 776 } else { 777 mmio_write_32(PCM_CON1, 778 SPM_REGWR_CFG_KEY | (mmio_read_32(PCM_CON1) & 779 ~REG_PCM_WDT_EN_LSB)); 780 } 781 } 782 783 uint32_t __spm_get_pcm_timer_val(void) 784 { 785 /* PCM_TIMER_VAL / 32768 = PCM_TIMER_VAL >> 15 (unit : sec) */ 786 return mmio_read_32(PCM_TIMER_VAL) >> 15; 787 } 788 789 void __spm_send_cpu_wakeup_event(void) 790 { 791 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); 792 /* SPM will clear SPM_CPU_WAKEUP_EVENT */ 793 } 794 795 void __spm_ext_int_wakeup_req_clr(void) 796 { 797 uint32_t cpu = plat_my_core_pos(); 798 unsigned int reg; 799 800 mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, (1U << cpu)); 801 802 /* Clear spm2mcupm wakeup interrupt status */ 803 reg = mmio_read_32(SPM2MCUPM_CON); 804 reg &= ~SPM2MCUPM_SW_INT_LSB; 805 mmio_write_32(SPM2MCUPM_CON, reg); 806 } 807 808 void __spm_clean_before_wfi(void) 809 { 810 } 811 812 void __spm_hw_s1_state_monitor(int en, unsigned int *status) 813 { 814 unsigned int reg; 815 816 if (en) { 817 reg = mmio_read_32(SPM_ACK_CHK_CON_3); 818 reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL; 819 mmio_write_32(SPM_ACK_CHK_CON_3, reg); 820 reg |= SPM_ACK_CHK_3_CON_EN; 821 mmio_write_32(SPM_ACK_CHK_CON_3, reg); 822 } else { 823 reg = mmio_read_32(SPM_ACK_CHK_CON_3); 824 825 if (reg & SPM_ACK_CHK_3_CON_RESULT) { 826 if (status) 827 *status |= SPM_INTERNAL_STATUS_HW_S1; 828 } 829 830 reg |= (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | 831 SPM_ACK_CHK_3_CON_CLR_ALL); 832 reg &= ~(SPM_ACK_CHK_3_CON_EN); 833 mmio_write_32(SPM_ACK_CHK_CON_3, reg); 834 } 835 } 836