1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <lib/mmio.h> 9 10 #include <mt_spm_hwreq.h> 11 #include <mt_spm_reg.h> 12 #include <platform_def.h> 13 14 static uint32_t spm_hwcg_index2res(uint32_t idx) 15 { 16 uint32_t res; 17 18 if (idx >= HWCG_MAX) 19 return 0; 20 21 switch (idx) { 22 case HWCG_DDREN: 23 res = (MT_SPM_DRAM_S0 | MT_SPM_DRAM_S1 | MT_SPM_EMI); 24 break; 25 case HWCG_VRF18: 26 res = MT_SPM_SYSPLL; 27 break; 28 case HWCG_INFRA: 29 res = MT_SPM_INFRA; 30 break; 31 case HWCG_PMIC: 32 res = MT_SPM_PMIC; 33 break; 34 case HWCG_F26M: 35 res = MT_SPM_26M; 36 break; 37 case HWCG_VCORE: 38 res = MT_SPM_VCORE; 39 break; 40 default: 41 res = 0; 42 } 43 return res; 44 } 45 46 static uint32_t spm_hwcg_ctrl_get(struct spm_hwcg_info *info, 47 enum spm_hwcg_setting type) 48 { 49 uint32_t reg = 0; 50 51 if (!info) 52 return 0; 53 54 switch (type) { 55 case HWCG_PWR: 56 reg = info->pwr; 57 break; 58 case HWCG_PWR_MSB: 59 reg = info->pwr_msb; 60 break; 61 default: 62 reg = info->module_busy; 63 break; 64 } 65 return reg; 66 } 67 68 static void __spm_hwcg_ctrl(struct spm_hwcg_info *info, 69 enum spm_hwcg_setting type, uint32_t is_set, 70 uint32_t val) 71 { 72 uint32_t reg; 73 74 reg = spm_hwcg_ctrl_get(info, type); 75 76 if (!reg) 77 return; 78 79 if (is_set) 80 mmio_setbits_32(reg, val); 81 else 82 mmio_clrbits_32(reg, val); 83 } 84 85 void spm_hwcg_ctrl(uint32_t res, enum spm_hwcg_setting type, uint32_t is_set, 86 uint32_t val) 87 { 88 struct spm_hwcg_info info; 89 90 if (res & (MT_SPM_DRAM_S0 | MT_SPM_DRAM_S1 | MT_SPM_EMI)) 91 DECLARE_HWCG_REG(DDREN, info); 92 else if (res & MT_SPM_SYSPLL) 93 DECLARE_HWCG_REG(VRF18, info); 94 else if (res & MT_SPM_INFRA) 95 DECLARE_HWCG_REG(INFRA, info); 96 else if (res & MT_SPM_PMIC) 97 DECLARE_HWCG_REG(PMIC, info); 98 else if (res & MT_SPM_26M) 99 DECLARE_HWCG_REG(F26M, info); 100 else if (res & MT_SPM_VCORE) 101 DECLARE_HWCG_REG(VCORE, info); 102 else 103 HWCG_INFO_INIT(info); 104 105 if (info.pwr) 106 __spm_hwcg_ctrl(&info, type, is_set, val); 107 } 108 109 void spm_hwcg_ctrl_by_index(uint32_t idx, enum spm_hwcg_setting type, 110 uint32_t is_set, uint32_t val) 111 { 112 uint32_t res = spm_hwcg_index2res(idx); 113 114 if (res) 115 spm_hwcg_ctrl(res, type, is_set, val); 116 } 117 118 static uint32_t spm_hwcg_mask_get(uint32_t res, enum spm_hwcg_setting type) 119 { 120 struct spm_hwcg_info info; 121 uint32_t raw_val = 0, reg = 0; 122 123 if (res & (MT_SPM_DRAM_S0 | MT_SPM_DRAM_S1 | MT_SPM_EMI)) 124 DECLARE_HWCG_REG(DDREN, info); 125 else if (res & MT_SPM_SYSPLL) 126 DECLARE_HWCG_REG(VRF18, info); 127 else if (res & MT_SPM_INFRA) 128 DECLARE_HWCG_REG(INFRA, info); 129 else if (res & MT_SPM_PMIC) 130 DECLARE_HWCG_REG(PMIC, info); 131 else if (res & MT_SPM_26M) 132 DECLARE_HWCG_REG(F26M, info); 133 else if (res & MT_SPM_VCORE) 134 DECLARE_HWCG_REG(VCORE, info); 135 else 136 HWCG_INFO_INIT(info); 137 138 if (!info.pwr) 139 return 0; 140 141 reg = spm_hwcg_ctrl_get(&info, type); 142 143 if (!reg) 144 return 0; 145 146 raw_val = ~mmio_read_32(reg); 147 148 return raw_val; 149 } 150 151 static uint32_t spm_hwcg_get_default(uint32_t res, enum spm_hwcg_setting type) 152 { 153 struct spm_hwcg_info info; 154 155 if (res & (MT_SPM_DRAM_S0 | MT_SPM_DRAM_S1 | MT_SPM_EMI)) 156 DECLARE_HWCG_DEFAULT(DDREN, info); 157 else if (res & MT_SPM_SYSPLL) 158 DECLARE_HWCG_DEFAULT(VRF18, info); 159 else if (res & MT_SPM_INFRA) 160 DECLARE_HWCG_DEFAULT(INFRA, info); 161 else if (res & MT_SPM_PMIC) 162 DECLARE_HWCG_DEFAULT(PMIC, info); 163 else if (res & MT_SPM_26M) 164 DECLARE_HWCG_DEFAULT(F26M, info); 165 else if (res & MT_SPM_VCORE) 166 DECLARE_HWCG_DEFAULT(VCORE, info); 167 else 168 HWCG_INFO_INIT(info); 169 170 if (!info.pwr) 171 return 0; 172 173 return spm_hwcg_ctrl_get(&info, type); 174 } 175 176 #define _APMIXEDSYS(ofs) (APMIXEDSYS + ofs) 177 #define PLL_UNIV _APMIXEDSYS(0x314) 178 #define PLL_MM _APMIXEDSYS(0x324) 179 #define PLL_MSDC _APMIXEDSYS(0x35C) 180 #define PLL_UFS _APMIXEDSYS(0x36C) 181 #define PLLEN_ALL _APMIXEDSYS(0x070) 182 #define PLL_UNIV_MERG BIT(5) 183 #define PLL_MM_MERG BIT(3) 184 #define PLL_MSDC_MERG BIT(4) 185 #define PLL_UFS_MERG BIT(2) 186 187 uint32_t spm_hwcg_get_status(uint32_t idx, enum spm_hwcg_setting type) 188 { 189 uint32_t val = 0; 190 uint32_t pllen_all = 0; 191 192 switch (type) { 193 case HWCG_PWR: 194 val = mmio_read_32(PWR_STATUS); 195 break; 196 case HWCG_PWR_MSB: 197 val = mmio_read_32(PWR_STATUS_MSB); 198 break; 199 default: 200 pllen_all = mmio_read_32(PLLEN_ALL); 201 202 if ((mmio_read_32(PLL_UNIV) & 0x1) || 203 (pllen_all & PLL_UNIV_MERG)) 204 val |= BIT(HWCG_MODULE_UNIVPLL); 205 if ((mmio_read_32(PLL_MSDC) & 0x1) || 206 (pllen_all & PLL_MSDC_MERG)) 207 val |= BIT(HWCG_MODULE_MSDCPLL); 208 if ((mmio_read_32(PLL_UFS) & 0x1) || (pllen_all & PLL_UFS_MERG)) 209 val |= BIT(HWCG_MODULE_UFSPLL); 210 if ((mmio_read_32(PLL_MM) & 0x1) || (pllen_all & PLL_MM_MERG)) 211 val |= BIT(HWCG_MODULE_MMPLL); 212 break; 213 } 214 return val; 215 } 216 217 int spm_hwcg_get_setting(uint32_t res, enum spm_hwcg_sta_type sta_type, 218 enum spm_hwcg_setting type, struct spm_hwcg_sta *sta) 219 { 220 int ret = 0; 221 222 if (!sta) 223 return -1; 224 225 switch (sta_type) { 226 case HWCG_STA_DEFAULT_MASK: 227 sta->sta = spm_hwcg_get_default(res, type); 228 break; 229 case HWCG_STA_MASK: 230 sta->sta = spm_hwcg_mask_get(res, type); 231 break; 232 default: 233 ret = -1; 234 MT_SPM_HW_CG_STA_INIT(sta); 235 break; 236 } 237 return ret; 238 } 239 240 int spm_hwcg_get_setting_by_index(uint32_t idx, enum spm_hwcg_sta_type sta_type, 241 enum spm_hwcg_setting type, 242 struct spm_hwcg_sta *sta) 243 { 244 uint32_t res = spm_hwcg_index2res(idx); 245 246 return spm_hwcg_get_setting(res, sta_type, type, sta); 247 } 248 249 static void spm_infra_swcg_init(void) 250 { 251 mmio_write_32(INFRA_SW_CG_0_MASK, ~INFRA_SW_CG_MB); 252 mmio_write_32(INFRA_SW_CG_1_MASK, ~INFRA_SW_CG_MB); 253 mmio_write_32(INFRA_SW_CG_2_MASK, ~INFRA_SW_CG_MB); 254 mmio_write_32(INFRA_SW_CG_3_MASK, ~INFRA_SW_CG_MB); 255 mmio_write_32(INFRA_SW_CG_4_MASK, ~INFRA_SW_CG_MB); 256 } 257 258 static void spm_hwcg_init(void) 259 { 260 /* HW CG for ddren, apsrc, emi resource req */ 261 mmio_write_32(REG_PWR_STATUS_DDREN_REQ_MASK, 262 ~SPM_HWCG_DDREN_PWR_MB); 263 mmio_write_32(REG_PWR_STATUS_MSB_DDREN_REQ_MASK, 264 ~SPM_HWCG_DDREN_PWR_MSB_MB); 265 mmio_write_32(REG_MODULE_BUSY_DDREN_REQ_MASK, 266 ~SPM_HWCG_DDREN_MODULE_BUSY_MB); 267 268 /* HW CG for vrf18 resource req */ 269 mmio_write_32(REG_PWR_STATUS_VRF18_REQ_MASK, 270 (uint32_t)(~SPM_HWCG_VRF18_PWR_MB)); 271 mmio_write_32(REG_PWR_STATUS_MSB_VRF18_REQ_MASK, 272 (uint32_t)(~SPM_HWCG_VRF18_PWR_MSB_MB)); 273 mmio_write_32(REG_MODULE_BUSY_VRF18_REQ_MASK, 274 (uint32_t)(~SPM_HWCG_VRF18_MODULE_BUSY_MB)); 275 276 /* HW CG for infra resource req */ 277 mmio_write_32(REG_PWR_STATUS_INFRA_REQ_MASK, 278 (uint32_t)(~SPM_HWCG_INFRA_PWR_MB)); 279 mmio_write_32(REG_PWR_STATUS_MSB_INFRA_REQ_MASK, 280 (uint32_t)(~SPM_HWCG_INFRA_PWR_MSB_MB)); 281 mmio_write_32(REG_MODULE_BUSY_INFRA_REQ_MASK, 282 (uint32_t)(~SPM_HWCG_INFRA_MODULE_BUSY_MB)); 283 284 /* HW CG for pmic resource req */ 285 mmio_write_32(REG_PWR_STATUS_PMIC_REQ_MASK, 286 (uint32_t)(~SPM_HWCG_PMIC_PWR_MB)); 287 mmio_write_32(REG_PWR_STATUS_MSB_PMIC_REQ_MASK, 288 (uint32_t)(~SPM_HWCG_PMIC_PWR_MSB_MB)); 289 mmio_write_32(REG_MODULE_BUSY_PMIC_REQ_MASK, 290 (uint32_t)(~SPM_HWCG_PMIC_MODULE_BUSY_MB)); 291 292 /* HW CG for f26m resource req */ 293 mmio_write_32(REG_PWR_STATUS_F26M_REQ_MASK, 294 (uint32_t)(~SPM_HWCG_F26M_PWR_MB)); 295 mmio_write_32(REG_PWR_STATUS_MSB_F26M_REQ_MASK, 296 (uint32_t)(~SPM_HWCG_F26M_PWR_MSB_MB)); 297 mmio_write_32(REG_MODULE_BUSY_F26M_REQ_MASK, 298 (uint32_t)(~SPM_HWCG_F26M_MODULE_BUSY_MB)); 299 300 /* HW CG for vcore resource req */ 301 mmio_write_32(REG_PWR_STATUS_VCORE_REQ_MASK, 302 (uint32_t)(~SPM_HWCG_VCORE_PWR_MB)); 303 mmio_write_32(REG_PWR_STATUS_MSB_VCORE_REQ_MASK, 304 (uint32_t)(~SPM_HWCG_VCORE_PWR_MSB_MB)); 305 mmio_write_32(REG_MODULE_BUSY_VCORE_REQ_MASK, 306 (uint32_t)(~SPM_HWCG_VCORE_MODULE_BUSY_MB)); 307 } 308 309 #define PERI_CG(ofs) (PERICFG_AO_BASE + 0x10 + (0x4 * ofs)) 310 #define PERI_REQ_DDREN_MB (BIT(PERI_REQ_EN_DMA) |\ 311 BIT(PERI_REQ_EN_UART1) |\ 312 BIT(PERI_REQ_EN_UART2) |\ 313 BIT(PERI_REQ_EN_UART3) |\ 314 BIT(PERI_REQ_EN_PWM) |\ 315 BIT(PERI_REQ_EN_SPI0) |\ 316 BIT(PERI_REQ_EN_SPI1) |\ 317 BIT(PERI_REQ_EN_SPI2) |\ 318 BIT(PERI_REQ_EN_SPI3) |\ 319 BIT(PERI_REQ_EN_SPI4) |\ 320 BIT(PERI_REQ_EN_SPI5) |\ 321 BIT(PERI_REQ_EN_I2C) |\ 322 BIT(PERI_REQ_EN_MSDC0) |\ 323 BIT(PERI_REQ_EN_MSDC1) |\ 324 BIT(PERI_REQ_EN_MSDC2) |\ 325 BIT(PERI_REQ_EN_SSUSB0) |\ 326 BIT(PERI_REQ_EN_SSUSB1) |\ 327 BIT(PERI_REQ_EN_SSUSB2) |\ 328 BIT(PERI_REQ_EN_SSUSB3) |\ 329 BIT(PERI_REQ_EN_SSUSB4) |\ 330 BIT(PERI_REQ_EN_PEXTP) |\ 331 BIT(PERI_REQ_EN_AFE)) 332 333 #define PERI_REQ_APSRC_MB (PERI_REQ_DDREN_MB) 334 #define PERI_REQ_EMI_MB (PERI_REQ_DDREN_MB) 335 #define PERI_REQ_INFRA_MB (PERI_REQ_DDREN_MB) 336 #define PERI_REQ_SYSPLL_MB (PERI_REQ_DDREN_MB) 337 #define PERI_REQ_PMIC_MB (PERI_REQ_DDREN_MB) 338 #define PERI_REQ_F26M_MB (PERI_REQ_DDREN_MB) 339 340 uint32_t spm_peri_req_get_status(uint32_t idx, enum spm_peri_req_status type) 341 { 342 uint32_t val = 0, reg = 0; 343 struct spm_peri_req_info info; 344 345 switch (type) { 346 case PERI_RES_REQ_EN: 347 348 switch (idx) { 349 case PERI_REQ_DDREN: 350 DECLARE_PERI_REQ_STA_REG(PERI_REQ_DDREN, info); 351 352 break; 353 case PERI_REQ_APSRC: 354 DECLARE_PERI_REQ_STA_REG(PERI_REQ_APSRC, info); 355 356 break; 357 case PERI_REQ_EMI: 358 DECLARE_PERI_REQ_STA_REG(PERI_REQ_EMI, info); 359 360 break; 361 case PERI_REQ_SYSPLL: 362 DECLARE_PERI_REQ_STA_REG(PERI_REQ_SYSPLL, info); 363 364 break; 365 case PERI_REQ_INFRA: 366 DECLARE_PERI_REQ_STA_REG(PERI_REQ_INFRA, info); 367 368 break; 369 case PERI_REQ_PMIC: 370 DECLARE_PERI_REQ_STA_REG(PERI_REQ_PMIC, info); 371 372 break; 373 case PERI_REQ_F26M: 374 DECLARE_PERI_REQ_STA_REG(PERI_REQ_F26M, info); 375 376 break; 377 default: 378 PERI_REQ_STA_INFO_INIT(info); 379 break; 380 } 381 382 if (!info.req_sta) 383 return 0; 384 385 reg = info.req_sta; 386 val = (mmio_read_32(reg) & PERI_REQ_EN_MASK); 387 388 break; 389 default: 390 break; 391 } 392 return val; 393 } 394 395 int spm_peri_req_name(uint32_t idex, char *name, size_t sz) 396 { 397 int ret = 0; 398 399 if (!name) 400 return -1; 401 402 switch (idex) { 403 case PERI_REQ_DDREN: 404 ret = snprintf(name, sz - 1, "ddren"); 405 break; 406 case PERI_REQ_APSRC: 407 ret = snprintf(name, sz - 1, "apsrc"); 408 break; 409 case PERI_REQ_EMI: 410 ret = snprintf(name, sz - 1, "emi"); 411 break; 412 case PERI_REQ_SYSPLL: 413 ret = snprintf(name, sz - 1, "syspll"); 414 break; 415 case PERI_REQ_INFRA: 416 ret = snprintf(name, sz - 1, "infra"); 417 break; 418 case PERI_REQ_PMIC: 419 ret = snprintf(name, sz - 1, "pmic"); 420 break; 421 case PERI_REQ_F26M: 422 ret = snprintf(name, sz - 1, "26m_vcore"); 423 break; 424 default: 425 ret = -1; 426 break; 427 } 428 429 name[sz - 1] = '\0'; 430 431 return ret; 432 } 433 434 uint32_t spm_peri_req_get_status_raw(enum spm_peri_req_status_raw type, 435 uint32_t idx, char *name, size_t sz) 436 { 437 return 0; 438 } 439 440 static uint32_t spm_peri_req_get_default(uint32_t res) 441 { 442 struct spm_peri_req_info info; 443 444 if (res & MT_SPM_DRAM_S1) 445 DECLARE_PERI_REQ_DEFAULT(DDREN, info); 446 else if (res & MT_SPM_DRAM_S0) 447 DECLARE_PERI_REQ_DEFAULT(APSRC, info); 448 else if (res & MT_SPM_EMI) 449 DECLARE_PERI_REQ_DEFAULT(EMI, info); 450 else if (res & MT_SPM_SYSPLL) 451 DECLARE_PERI_REQ_DEFAULT(SYSPLL, info); 452 else if (res & MT_SPM_INFRA) 453 DECLARE_PERI_REQ_DEFAULT(INFRA, info); 454 else if (res & MT_SPM_PMIC) 455 DECLARE_PERI_REQ_DEFAULT(PMIC, info); 456 else if (res & (MT_SPM_26M | MT_SPM_VCORE)) 457 DECLARE_PERI_REQ_DEFAULT(F26M, info); 458 else 459 PERI_REQ_EN_INFO_INIT(info); 460 461 return info.req_en; 462 } 463 464 static uint32_t spm_peri_req_mask_get(uint32_t res) 465 { 466 struct spm_peri_req_info info; 467 uint32_t raw_val = 0, reg = 0; 468 469 if (res & MT_SPM_DRAM_S1) 470 DECLARE_PERI_REQ_EN_REG(PERI_REQ_DDREN, info); 471 else if (res & MT_SPM_DRAM_S0) 472 DECLARE_PERI_REQ_EN_REG(PERI_REQ_APSRC, info); 473 else if (res & MT_SPM_EMI) 474 DECLARE_PERI_REQ_EN_REG(PERI_REQ_EMI, info); 475 else if (res & MT_SPM_SYSPLL) 476 DECLARE_PERI_REQ_EN_REG(PERI_REQ_SYSPLL, info); 477 else if (res & MT_SPM_INFRA) 478 DECLARE_PERI_REQ_EN_REG(PERI_REQ_INFRA, info); 479 else if (res & MT_SPM_PMIC) 480 DECLARE_PERI_REQ_EN_REG(PERI_REQ_PMIC, info); 481 else if (res & (MT_SPM_26M | MT_SPM_VCORE)) 482 DECLARE_PERI_REQ_EN_REG(PERI_REQ_F26M, info); 483 else 484 PERI_REQ_EN_INFO_INIT(info); 485 486 if (!info.req_en) 487 return 0; 488 489 reg = info.req_en; 490 491 raw_val = (mmio_read_32(reg) & PERI_REQ_EN_MASK); 492 493 return raw_val; 494 } 495 496 int spm_peri_req_get_setting(uint32_t res, enum spm_peri_req_sta_type sta_type, 497 struct spm_peri_req_sta *sta) 498 { 499 int ret = 0; 500 501 if (!sta) 502 return -1; 503 504 switch (sta_type) { 505 case PERI_REQ_STA_DEFAULT_MASK: 506 sta->sta = spm_peri_req_get_default(res); 507 break; 508 case PERI_REQ_STA_MASK: 509 sta->sta = spm_peri_req_mask_get(res); 510 break; 511 default: 512 ret = -1; 513 MT_SPM_HW_CG_STA_INIT(sta); 514 break; 515 } 516 return ret; 517 } 518 519 static uint32_t spm_peri_req_index2res(uint32_t idx) 520 { 521 uint32_t res; 522 523 if (idx >= PERI_REQ_MAX) 524 return 0; 525 526 switch (idx) { 527 case PERI_REQ_DDREN: 528 res = MT_SPM_DRAM_S1; 529 break; 530 case PERI_REQ_APSRC: 531 res = MT_SPM_DRAM_S0; 532 break; 533 case PERI_REQ_EMI: 534 res = MT_SPM_EMI; 535 break; 536 case PERI_REQ_SYSPLL: 537 res = MT_SPM_SYSPLL; 538 break; 539 case PERI_REQ_INFRA: 540 res = MT_SPM_INFRA; 541 break; 542 case PERI_REQ_PMIC: 543 res = (MT_SPM_PMIC); 544 break; 545 case PERI_REQ_F26M: 546 res = (MT_SPM_26M | MT_SPM_VCORE); 547 break; 548 default: 549 res = 0; 550 } 551 return res; 552 } 553 554 int spm_peri_req_get_setting_by_index(uint32_t idx, 555 enum spm_peri_req_sta_type sta_type, 556 struct spm_peri_req_sta *sta) 557 { 558 uint32_t res = spm_peri_req_index2res(idx); 559 560 return spm_peri_req_get_setting(res, sta_type, sta); 561 } 562 563 static void __spm_peri_req_ctrl(struct spm_peri_req_info *info, uint32_t is_set, 564 uint32_t val) 565 { 566 uint32_t reg; 567 568 if (!info) 569 return; 570 571 reg = info->req_en; 572 573 if (!reg) 574 return; 575 576 if (is_set) 577 mmio_setbits_32(reg, val); 578 else 579 mmio_clrbits_32(reg, val); 580 } 581 582 void spm_peri_req_ctrl(uint32_t res, uint32_t is_set, uint32_t val) 583 { 584 struct spm_peri_req_info info; 585 586 if (res & MT_SPM_DRAM_S1) 587 DECLARE_PERI_REQ_EN_REG(PERI_REQ_DDREN, info); 588 else if (res & MT_SPM_DRAM_S0) 589 DECLARE_PERI_REQ_EN_REG(PERI_REQ_APSRC, info); 590 else if (res & MT_SPM_EMI) 591 DECLARE_PERI_REQ_EN_REG(PERI_REQ_EMI, info); 592 else if (res & MT_SPM_SYSPLL) 593 DECLARE_PERI_REQ_EN_REG(PERI_REQ_SYSPLL, info); 594 else if (res & MT_SPM_INFRA) 595 DECLARE_PERI_REQ_EN_REG(PERI_REQ_INFRA, info); 596 else if (res & MT_SPM_PMIC) 597 DECLARE_PERI_REQ_EN_REG(MT_SPM_PMIC, info); 598 else if (res & (MT_SPM_26M | MT_SPM_VCORE)) 599 DECLARE_PERI_REQ_EN_REG(PERI_REQ_F26M, info); 600 else 601 PERI_REQ_EN_INFO_INIT(info); 602 603 if (info.req_en) 604 __spm_peri_req_ctrl(&info, is_set, val); 605 } 606 607 void spm_peri_req_ctrl_by_index(uint32_t idx, uint32_t is_set, uint32_t val) 608 { 609 uint32_t res = spm_peri_req_index2res(idx); 610 611 if (res) 612 spm_peri_req_ctrl(res, is_set, val); 613 } 614 615 static void spm_peri_req_init(void) 616 { 617 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_DDREN), PERI_REQ_DDREN_MB); 618 619 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_EMI), PERI_REQ_EMI_MB); 620 621 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_APSRC), PERI_REQ_APSRC_MB); 622 623 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_INFRA), PERI_REQ_INFRA_MB); 624 625 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_SYSPLL), PERI_REQ_SYSPLL_MB); 626 627 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_PMIC), PERI_REQ_PMIC_MB); 628 629 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_F26M), PERI_REQ_F26M_MB); 630 } 631 632 void spm_hwreq_init(void) 633 { 634 spm_infra_swcg_init(); 635 spm_hwcg_init(); 636 spm_peri_req_init(); 637 } 638