1 /* 2 * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stddef.h> 8 #include <stdio.h> 9 #include <string.h> 10 11 #include <common/debug.h> 12 #include <lib/mmio.h> 13 #include <plat/common/platform.h> 14 15 #include <lib/pm/mtk_pm.h> 16 #include "mt_spm.h" 17 #include "mt_spm_internal.h" 18 #include "mt_spm_pmic_wrap.h" 19 #include "mt_spm_reg.h" 20 #include <platform_def.h> 21 22 /* BIT operation */ 23 #define _BITS_(h, l, v) ((GENMASK(h, l) & ((v) << (l)))) 24 25 /* PMIC_WRAP */ 26 #define VCORE_BASE_UV (40000) /* PMIC MT6359 */ 27 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) 28 29 #define NR_PMIC_WRAP_CMD (NR_IDX_ALL) 30 #define SPM_DATA_SHIFT (16) 31 32 #define BUCK_VGPU11_ELR0 (0x15B4) 33 #define TOP_SPI_CON0 (0x0456) 34 #define BUCK_TOP_CON1 (0x1443) /* PMIC MT6315 */ 35 #define TOP_CON (0x0013) /* PMIC MT6315 */ 36 #define TOP_DIG_WPK (0x03a9) 37 #define TOP_CON_LOCK (0x03a8) 38 #define TOP_CLK_CON0 (0x0134) /* PMIC MT6359*/ 39 40 struct pmic_wrap_cmd { 41 uint32_t cmd_addr; 42 uint32_t cmd_wdata; 43 }; 44 45 struct pmic_wrap_setting { 46 enum pmic_wrap_phase_id phase; 47 struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD]; 48 struct { 49 struct { 50 uint32_t cmd_addr; 51 uint32_t cmd_wdata; 52 } _[NR_PMIC_WRAP_CMD]; 53 const int nr_idx; 54 } set[NR_PMIC_WRAP_PHASE]; 55 }; 56 57 static struct pmic_wrap_setting pw = { 58 .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */ 59 .addr = {{0, 0} }, 60 .set[PMIC_WRAP_PHASE_ALLINONE] = { 61 ._[CMD_0] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(75000)),}, 62 ._[CMD_1] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(65000)),}, 63 ._[CMD_2] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(60000)),}, 64 ._[CMD_3] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(55000)),}, 65 ._[CMD_4] = {TOP_SPI_CON0, _BITS_(0, 0, 1),}, 66 ._[CMD_5] = {TOP_SPI_CON0, _BITS_(0, 0, 0),}, 67 ._[CMD_6] = {BUCK_TOP_CON1, 0x0,}, /* MT6315-3: VMD NO LP */ 68 ._[CMD_7] = {BUCK_TOP_CON1, 0xF,}, /* MT6315-3: VMD LP */ 69 ._[CMD_8] = {TOP_CON, 0x3,}, /* MT6315-3: PMIC NO LP */ 70 ._[CMD_9] = {TOP_CON, 0x0,}, /* MT6315-3: PMIC LP */ 71 ._[CMD_10] = {TOP_DIG_WPK, 0x63,}, /* MT6315-2: PMIC_CON_DIG_WPK */ 72 ._[CMD_11] = {TOP_CON_LOCK, 0x15,}, /* MT6315-2: PMIC_CON_UNLOCK */ 73 ._[CMD_12] = {TOP_DIG_WPK, 0x0,}, /* MT6315-2: PMIC_CON_DIG_WPK */ 74 ._[CMD_13] = {TOP_CON_LOCK, 0x0,}, /* MT6315-2: PMIC_CON_LOCK */ 75 ._[CMD_14] = {TOP_CLK_CON0, 0x0040,}, /* MT6359: 6359_LDO_SW_SEL_H */ 76 ._[CMD_15] = {TOP_CLK_CON0, 0x0000,}, /* MT6359: 6359_LDO_SW_SEL_L */ 77 .nr_idx = NR_IDX_ALL, 78 }, 79 }; 80 81 void _mt_spm_pmic_table_init(void) 82 { 83 struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = { 84 { (uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0, }, 85 { (uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1, }, 86 { (uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2, }, 87 { (uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3, }, 88 { (uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4, }, 89 { (uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5, }, 90 { (uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6, }, 91 { (uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7, }, 92 { (uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8, }, 93 { (uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9, }, 94 { (uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10, }, 95 { (uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11, }, 96 { (uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12, }, 97 { (uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13, }, 98 { (uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14, }, 99 { (uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15, }, 100 }; 101 102 memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); 103 } 104 105 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) 106 { 107 int idx; 108 109 if ((phase >= NR_PMIC_WRAP_PHASE) || (pw.phase == phase)) { 110 return; 111 } 112 113 if (pw.addr[0].cmd_addr == 0) { 114 _mt_spm_pmic_table_init(); 115 } 116 117 pw.phase = phase; 118 119 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); 120 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { 121 mmio_write_32(pw.addr[idx].cmd_addr, 122 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | 123 (pw.set[phase]._[idx].cmd_wdata)); 124 } 125 } 126 127 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx, 128 unsigned int cmd_wdata) 129 { 130 /* just set wdata value */ 131 if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) { 132 return; 133 } 134 135 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; 136 137 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); 138 if (pw.phase == phase) { 139 mmio_write_32(pw.addr[idx].cmd_addr, 140 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | cmd_wdata); 141 } 142 } 143 144 uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx) 145 { 146 /* just get wdata value */ 147 if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) { 148 return 0; 149 } 150 151 return pw.set[phase]._[idx].cmd_wdata; 152 } 153