1 /* 2 * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 #include <stdio.h> 10 #include <string.h> 11 12 #include <common/debug.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 16 #include <drivers/spm/mt_spm_resource_req.h> 17 #include "mt_spm.h" 18 #include "mt_spm_internal.h" 19 #include "mt_spm_pmic_wrap.h" 20 #include "mt_spm_reg.h" 21 #include <platform_def.h> 22 23 #define SPM_INIT_DONE_US (20) /* Simulation result */ 24 25 wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta) 26 { 27 uint32_t bk_vtcxo_dur, spm_26m_off_pct; 28 wake_reason_t wr = WR_UNKNOWN; 29 30 if (wakesta == NULL) { 31 return wr; 32 } 33 34 if (wakesta->is_abort != 0U) { 35 VERBOSE("SPM EARLY WAKE r12 = 0x%x, debug_flag = 0x%x 0x%x\n", 36 wakesta->tr.comm.r12, 37 wakesta->tr.comm.debug_flag, wakesta->tr.comm.debug_flag1); 38 VERBOSE("SPM EARLY WAKE sw_flag = 0x%x 0x%x b_sw_flag = 0x%x 0x%x\n", 39 wakesta->sw_flag0, wakesta->sw_flag1, 40 wakesta->tr.comm.b_sw_flag0, wakesta->tr.comm.b_sw_flag1); 41 } 42 43 if ((wakesta->tr.comm.r12 & R12_PCM_TIMER) != 0U) { 44 45 if ((wakesta->wake_misc & WAKE_MISC_PCM_TIMER_EVENT) != 0U) { 46 wr = WR_PCM_TIMER; 47 } 48 } 49 50 INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n", 51 wakesta->tr.comm.r12, wakesta->r12_ext, wakesta->tr.comm.r13, wakesta->tr.comm.debug_flag, 52 wakesta->tr.comm.debug_flag1); 53 INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n", 54 wakesta->tr.comm.raw_sta, wakesta->md32pcm_wakeup_sta, 55 wakesta->md32pcm_event_sta, wakesta->idle_sta, 56 wakesta->cg_check_sta); 57 INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n", 58 wakesta->tr.comm.req_sta0, wakesta->tr.comm.req_sta1, wakesta->tr.comm.req_sta2, 59 wakesta->tr.comm.req_sta3, wakesta->tr.comm.req_sta4, wakesta->isr); 60 INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n", 61 wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2); 62 INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n", 63 wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta); 64 INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n", 65 wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1, 66 wakesta->tr.comm.b_sw_flag0, wakesta->tr.comm.b_sw_flag1, wakesta->src_req); 67 INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n", 68 wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L), 69 mmio_read_32(SYS_TIMER_VALUE_H)); 70 71 if (wakesta->tr.comm.timer_out != 0U) { 72 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); 73 spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->tr.comm.timer_out; 74 INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct); 75 } 76 77 return wr; 78 } 79 80 void __spm_set_cpu_status(unsigned int cpu) 81 { 82 if (cpu >= 8) { 83 ERROR("%s: error cpu number %d\n", __func__, cpu); 84 return; 85 } 86 mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu)); 87 mmio_write_32(ROOT_CORE_ADDR, SPM_CPU0_PWR_CON + (cpu * 0x4) + 0x20000000); 88 /* Notify MCUPM to wake the target CPU up */ 89 mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu); 90 } 91 92 void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, unsigned int resource_usage) 93 { 94 95 uint8_t reg_spm_apsrc_req = (resource_usage & MT_SPM_DRAM_S0) ? 96 1 : pwrctrl->reg_spm_apsrc_req; 97 uint8_t reg_spm_ddr_en_req = (resource_usage & MT_SPM_DRAM_S1) ? 98 1 : pwrctrl->reg_spm_ddr_en_req; 99 uint8_t reg_spm_vrf18_req = (resource_usage & MT_SPM_SYSPLL) ? 100 1 : pwrctrl->reg_spm_vrf18_req; 101 uint8_t reg_spm_infra_req = (resource_usage & MT_SPM_INFRA) ? 102 1 : pwrctrl->reg_spm_infra_req; 103 uint8_t reg_spm_f26m_req = (resource_usage & (MT_SPM_26M | MT_SPM_XO_FPM)) ? 104 1 : pwrctrl->reg_spm_f26m_req; 105 106 /* SPM_SRC_REQ */ 107 mmio_write_32(SPM_SRC_REQ, 108 ((reg_spm_apsrc_req & 0x1) << 0) | 109 ((reg_spm_f26m_req & 0x1) << 1) | 110 ((reg_spm_infra_req & 0x1) << 3) | 111 ((reg_spm_vrf18_req & 0x1) << 4) | 112 ((reg_spm_ddr_en_req & 0x1) << 7) | 113 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | 114 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | 115 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | 116 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | 117 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); 118 } 119 120 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl) 121 { 122 /* SPM_AP_STANDBY_CON */ 123 mmio_write_32(SPM_AP_STANDBY_CON, 124 ((pwrctrl->reg_wfi_op & 0x1) << 0) | 125 ((pwrctrl->reg_wfi_type & 0x1) << 1) | 126 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | 127 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | 128 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | 129 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | 130 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | 131 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); 132 133 /* SPM_SRC_REQ */ 134 mmio_write_32(SPM_SRC_REQ, 135 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | 136 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | 137 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | 138 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | 139 ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) | 140 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | 141 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | 142 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | 143 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | 144 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); 145 146 /* SPM_SRC_MASK */ 147 mmio_write_32(SPM_SRC_MASK, 148 ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) | 149 ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) | 150 ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) | 151 ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) | 152 ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) | 153 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) | 154 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) | 155 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) | 156 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) | 157 ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) | 158 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) | 159 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) | 160 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) | 161 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) | 162 ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) | 163 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) | 164 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) | 165 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) | 166 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) | 167 ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) | 168 ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) | 169 ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) | 170 ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) | 171 ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) | 172 ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) | 173 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) | 174 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) | 175 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) | 176 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) | 177 ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29) | 178 ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 30) | 179 ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 31)); 180 181 /* SPM_SRC2_MASK */ 182 mmio_write_32(SPM_SRC2_MASK, 183 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) | 184 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) | 185 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) | 186 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) | 187 ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) | 188 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) | 189 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) | 190 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) | 191 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) | 192 ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) | 193 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) | 194 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) | 195 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) | 196 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) | 197 ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) | 198 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) | 199 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) | 200 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) | 201 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) | 202 ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) | 203 ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) | 204 ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) | 205 ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) | 206 ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) | 207 ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) | 208 ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) | 209 ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) | 210 ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) | 211 ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) | 212 ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29)); 213 214 /* SPM_SRC3_MASK */ 215 mmio_write_32(SPM_SRC3_MASK, 216 ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) | 217 ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) | 218 ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) | 219 ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) | 220 ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) | 221 ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) | 222 ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) | 223 ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) | 224 ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) | 225 ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) | 226 ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) | 227 ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) | 228 ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) | 229 ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) | 230 ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) | 231 ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) | 232 ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) | 233 ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) | 234 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) | 235 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) | 236 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) | 237 ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) | 238 ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) | 239 ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) | 240 ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) | 241 ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) | 242 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) | 243 ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27)); 244 245 /* SPM_SRC4_MASK */ 246 mmio_write_32(SPM_SRC4_MASK, 247 ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) | 248 ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) | 249 ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 18) | 250 ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 20) | 251 ((pwrctrl->reg_dramc_md32_ddr_en_mask_b & 0x3) << 22) | 252 ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 24)); 253 254 /* SPM_WAKEUP_EVENT_MASK */ 255 mmio_write_32(SPM_WAKEUP_EVENT_MASK, 256 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); 257 258 /* SPM_WAKEUP_EVENT_EXT_MASK */ 259 mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, 260 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); 261 } 262 263 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 264 { 265 unsigned int val, mask; 266 267 /* toggle event counter clear */ 268 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); 269 /* toggle for reset SYS TIMER start point */ 270 mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); 271 272 if (pwrctrl->timer_val_cust == 0U) { 273 val = (pwrctrl->timer_val != 0U) ? pwrctrl->timer_val : PCM_TIMER_MAX; 274 } else { 275 val = pwrctrl->timer_val_cust; 276 } 277 278 mmio_write_32(PCM_TIMER_VAL, val); 279 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); 280 281 /* unmask AP wakeup source */ 282 if (pwrctrl->wake_src_cust == 0U) { 283 mask = pwrctrl->wake_src; 284 } else { 285 mask = pwrctrl->wake_src_cust; 286 } 287 288 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); 289 290 /* unmask SPM ISR (keep TWAM setting) */ 291 mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX); 292 293 /* toggle event counter clear */ 294 mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY); 295 /* toggle for reset SYS TIMER start point */ 296 mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); 297 } 298 299 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) 300 { 301 /* set PCM flags and data */ 302 if (pwrctrl->pcm_flags_cust_clr != 0U) { 303 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; 304 } 305 if (pwrctrl->pcm_flags_cust_set != 0U) { 306 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set; 307 } 308 if (pwrctrl->pcm_flags1_cust_clr != 0U) { 309 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; 310 } 311 if (pwrctrl->pcm_flags1_cust_set != 0U) { 312 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; 313 } 314 315 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags); 316 317 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1); 318 319 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags); 320 321 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1); 322 } 323 324 void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_status) 325 { 326 /* get wakeup event */ 327 wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); /* backup of PCM_REG12_DATA */ 328 wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_EXT_STA); 329 wakesta->tr.comm.raw_sta = mmio_read_32(SPM_WAKEUP_STA); 330 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); 331 wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA); 332 wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA); 333 wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC); /* backup of SPM_WAKEUP_MISC */ 334 335 /* get sleep time */ 336 wakesta->tr.comm.timer_out = 337 mmio_read_32(SPM_BK_PCM_TIMER); /* backup of PCM_TIMER_OUT */ 338 339 /* get other SYS and co-clock status */ 340 wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA); 341 wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA); 342 wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0); 343 wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1); 344 wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2); 345 wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3); 346 wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4); 347 348 /* get debug flag for PCM execution check */ 349 wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0); 350 wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1); 351 352 if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) { 353 wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE | 354 SPM_DBG_DEBUG_IDX_DDREN_SLEEP); 355 mmio_write_32(PCM_WDT_LATCH_SPARE_0, wakesta->tr.comm.debug_flag); 356 } 357 358 /* get backup SW flag status */ 359 wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); /* SPM_SW_RSV_7 */ 360 wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); /* SPM_SW_RSV_8 */ 361 362 /* record below spm info for debug */ 363 wakesta->src_req = mmio_read_32(SPM_SRC_REQ); 364 365 /* get HW CG check status */ 366 wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA); 367 368 wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2); 369 wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3); 370 wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4); 371 wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5); 372 wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6); 373 374 /* get ISR status */ 375 wakesta->isr = mmio_read_32(SPM_IRQ_STA); 376 377 /* get SW flag status */ 378 wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0); 379 wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1); 380 381 /* get CLK SETTLE */ 382 wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE); 383 384 /* check abort */ 385 wakesta->is_abort = wakesta->tr.comm.debug_flag & DEBUG_ABORT_MASK; 386 wakesta->is_abort |= wakesta->tr.comm.debug_flag1 & DEBUG_ABORT_MASK_1; 387 } 388 389 void __spm_clean_after_wakeup(void) 390 { 391 /* 392 * Copy SPM_WAKEUP_STA to SPM_BK_WAKE_EVENT before clear SPM_WAKEUP_STA 393 * 394 * CPU dormant driver @kernel will copy edge-trig IRQ pending 395 * (recorded @SPM_BK_WAKE_EVENT) to GIC 396 */ 397 mmio_write_32(SPM_BK_WAKE_EVENT, mmio_read_32(SPM_WAKEUP_STA) | 398 mmio_read_32(SPM_BK_WAKE_EVENT)); 399 400 /* clean CPU wakeup event */ 401 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0U); 402 403 /* clean wakeup event raw status (for edge trigger event) */ 404 mmio_write_32(SPM_WAKEUP_EVENT_MASK, 0xefffffff); /* bit[28] for cpu wake up event */ 405 406 /* clean ISR status (except TWAM) */ 407 mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); 408 mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); 409 mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); 410 } 411 412 void __spm_set_pcm_wdt(int en) 413 { 414 /* enable PCM WDT (normal mode) to start count if needed */ 415 if (en != 0) { 416 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, SPM_REGWR_CFG_KEY); 417 418 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) { 419 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); 420 } 421 mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); 422 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); 423 } else { 424 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, SPM_REGWR_CFG_KEY); 425 } 426 } 427 428 void __spm_send_cpu_wakeup_event(void) 429 { 430 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); 431 /* SPM will clear SPM_CPU_WAKEUP_EVENT */ 432 } 433 434 void __spm_ext_int_wakeup_req_clr(void) 435 { 436 mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR)); 437 438 /* clear spm2mcupm wakeup interrupt status */ 439 mmio_write_32(SPM2CPUEB_CON, 0); 440 } 441 442 void __spm_clean_before_wfi(void) 443 { 444 } 445 446 void __spm_hw_s1_state_monitor(int en, unsigned int *status) 447 { 448 unsigned int reg; 449 450 if (en != 0) { 451 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_CLR_ALL, 452 SPM_ACK_CHK_3_CON_EN); 453 } else { 454 reg = mmio_read_32(SPM_ACK_CHK_CON_3); 455 456 if ((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) { 457 if (status != NULL) { 458 *status |= SPM_INTERNAL_STATUS_HW_S1; 459 } 460 } 461 462 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, 463 (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL)); 464 } 465 } 466