xref: /rk3399_ARM-atf/plat/mediatek/drivers/spm/common/mt_spm_constraint.h (revision b47dddd061e92054c3b2096fc8aa9688bfef68d6)
1 /*
2  * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MT_SPM_CONSTRAINT_H
8 #define MT_SPM_CONSTRAINT_H
9 
10 #include <lpm_v2/mt_lp_rm.h>
11 
12 #define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF	BIT(0)
13 #define MT_RM_CONSTRAINT_ALLOW_DRAM_S0		BIT(1)
14 #define MT_RM_CONSTRAINT_ALLOW_DRAM_S1		BIT(2)
15 #define MT_RM_CONSTRAINT_ALLOW_VCORE_LP		BIT(3)
16 #define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN	BIT(4)
17 #define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF	BIT(5)
18 #define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND	BIT(6) /* System suspend */
19 #define MT_RM_CONSTRAINT_ALLOW_BBLPM		BIT(7)
20 #define MT_RM_CONSTRAINT_ALLOW_XO_UFS		BIT(8)
21 #define MT_RM_CONSTRAINT_ALLOW_GPS_STATE	BIT(9)
22 #define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE	BIT(10)
23 #define MT_RM_CONSTRAINT_ALLOW_AP_PLAT_SUSPEND	BIT(11) /* Kernel suspend */
24 #define MT_RM_CONSTRAINT_ALLOW_VCORE_OFF	BIT(12)
25 
26 #define MT_SPM_RC_INVALID		0x0
27 #define MT_SPM_RC_VALID_SW		BIT(0)
28 #define MT_SPM_RC_VALID_FW		BIT(1)
29 #define MT_SPM_RC_VALID_RESIDNECY	BIT(2)
30 #define MT_SPM_RC_VALID_COND_CHECK	BIT(3)
31 #define MT_SPM_RC_VALID_COND_LATCH	BIT(4)
32 #define MT_SPM_RC_VALID_UFS_H8		BIT(5)
33 #define MT_SPM_RC_VALID_FLIGHTMODE	BIT(6)
34 #define MT_SPM_RC_VALID_XSOC_BBLPM	BIT(7)
35 #define MT_SPM_RC_VALID_TRACE_EVENT	BIT(8)
36 #define MT_SPM_RC_VALID_TRACE_TIME	BIT(9)
37 #define MT_SPM_RC_VALID_NOTIFY		BIT(10)
38 
39 #define MT_SPM_RC_VALID		(MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_FW)
40 
41 #define IS_MT_RM_RC_READY(status) \
42 	((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
43 
44 struct constraint_status {
45 	uint16_t id;
46 	uint16_t is_valid;
47 	uint64_t is_cond_block;
48 	uint32_t enter_cnt;
49 	uint64_t all_pll_dump;
50 	unsigned long long residency;
51 	struct mt_spm_cond_tables *cond_res;
52 };
53 
54 enum constraint_status_update_type {
55 	CONSTRAINT_UPDATE_VALID,
56 	CONSTRAINT_UPDATE_COND_CHECK,
57 	CONSTRAINT_RESIDNECY,
58 };
59 
60 enum constraint_status_get_type {
61 	CONSTRAINT_GET_VALID = 0xD0000000,
62 	CONSTRAINT_GET_ENTER_CNT,
63 	CONSTRAINT_GET_RESIDENCY,
64 	CONSTRAINT_GET_COND_EN,
65 	CONSTRAINT_COND_BLOCK,
66 	CONSTRAINT_GET_COND_BLOCK_LATCH,
67 	CONSTRAINT_GET_COND_BLOCK_DETAIL,
68 	CONSTRAINT_GET_RESIDNECY,
69 };
70 
71 struct rc_common_state {
72 	unsigned int id;
73 	unsigned int act;
74 	unsigned int type;
75 	void *value;
76 };
77 
78 #define MT_SPM_RC_BBLPM_MODE	(MT_SPM_RC_VALID_UFS_H8 | \
79 				 MT_SPM_RC_VALID_FLIGHTMODE | \
80 				 MT_SPM_RC_VALID_XSOC_BBLPM)
81 
82 #define IS_MT_SPM_RC_BBLPM_MODE(st) \
83 	((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
84 
85 #define IS_MT_SPM_RC_NOTIFY_ENABLE(st) \
86 	((st & (MT_SPM_RC_VALID_NOTIFY)))
87 
88 #define MT_SPM_RC_EXTERN_STATUS_SET(v, st)	({v |= (st & 0xffff); })
89 #define MT_SPM_RC_EXTERN_STATUS_CLR(v, st)	({v &= ~(st & 0xffff); })
90 
91 #endif /* MT_SPM_CONSTRAINT_H */
92