xref: /rk3399_ARM-atf/plat/mediatek/drivers/rng/mt8186/rng_plat.h (revision d684e7fbb34b53bdccbafa6d78211e7c77688bb9)
1*8c1740e2SSuyuan Su /*
2*8c1740e2SSuyuan Su  * Copyright (c) 2024, MediaTek Inc. All rights reserved.
3*8c1740e2SSuyuan Su  *
4*8c1740e2SSuyuan Su  * SPDX-License-Identifier: BSD-3-Clause
5*8c1740e2SSuyuan Su  */
6*8c1740e2SSuyuan Su 
7*8c1740e2SSuyuan Su #ifndef RNG_PLAT_H
8*8c1740e2SSuyuan Su #define RNG_PLAT_H
9*8c1740e2SSuyuan Su 
10*8c1740e2SSuyuan Su #define TRNG_TIME_OUT		1000
11*8c1740e2SSuyuan Su #define MTK_TRNG_MAX_ROUND	4
12*8c1740e2SSuyuan Su 
13*8c1740e2SSuyuan Su /*******************************************************************************
14*8c1740e2SSuyuan Su  * TRNG related constants
15*8c1740e2SSuyuan Su  ******************************************************************************/
16*8c1740e2SSuyuan Su #define TRNG_BASE_SIZE		0x1000
17*8c1740e2SSuyuan Su #define TRNG_CTRL		(TRNG_BASE + 0x0000)
18*8c1740e2SSuyuan Su #define TRNG_TIME		(TRNG_BASE + 0x0004)
19*8c1740e2SSuyuan Su #define TRNG_DATA		(TRNG_BASE + 0x0008)
20*8c1740e2SSuyuan Su #define TRNG_CONF		(TRNG_BASE + 0x000C)
21*8c1740e2SSuyuan Su #define TRNG_CTRL_RDY		0x80000000
22*8c1740e2SSuyuan Su #define TRNG_CTRL_START		0x00000001
23*8c1740e2SSuyuan Su #define TRNG_CONF_VON_EN	0x00000020
24*8c1740e2SSuyuan Su #define TRNG_PDN_BASE_SIZE	0x1000
25*8c1740e2SSuyuan Su #define TRNG_PDN_SET		(INFRACFG_AO_BASE + 0x0088)
26*8c1740e2SSuyuan Su #define TRNG_PDN_CLR		(INFRACFG_AO_BASE + 0x008C)
27*8c1740e2SSuyuan Su #define TRNG_PDN_STATUS		(INFRACFG_AO_BASE + 0x0094)
28*8c1740e2SSuyuan Su #define TRNG_PDN_VALUE		0x200
29*8c1740e2SSuyuan Su 
30*8c1740e2SSuyuan Su #endif /* RNG_PLAT_H */
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