1*c8a74b45SHope Wang /* 2*c8a74b45SHope Wang * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3*c8a74b45SHope Wang * 4*c8a74b45SHope Wang * SPDX-License-Identifier: BSD-3-Clause 5*c8a74b45SHope Wang */ 6*c8a74b45SHope Wang 7*c8a74b45SHope Wang #ifndef PTP3_PLAT_COMMON_H 8*c8a74b45SHope Wang #define PTP3_PLAT_COMMON_H 9*c8a74b45SHope Wang 10*c8a74b45SHope Wang #include <lib/mmio.h> 11*c8a74b45SHope Wang #include <lib/utils_def.h> 12*c8a74b45SHope Wang #include <ptp3_common.h> 13*c8a74b45SHope Wang 14*c8a74b45SHope Wang /* CPU Info */ 15*c8a74b45SHope Wang #define NR_PTP3_CFG_CPU U(8) 16*c8a74b45SHope Wang #define PTP3_CFG_CPU_START_ID_L U(0) 17*c8a74b45SHope Wang #define PTP3_CFG_CPU_END_ID U(7) 18*c8a74b45SHope Wang 19*c8a74b45SHope Wang #define NR_PTP3_CFG1_DATA U(2) 20*c8a74b45SHope Wang #define PTP3_CFG1_MASK 0x3000 21*c8a74b45SHope Wang 22*c8a74b45SHope Wang #define NR_PTP3_CFG2_DATA U(5) 23*c8a74b45SHope Wang 24*c8a74b45SHope Wang #define PTP3_CFG3_MASK1 0x1180 25*c8a74b45SHope Wang #define PTP3_CFG3_MASK2 0x35C0 26*c8a74b45SHope Wang #define PTP3_CFG3_MASK3 0x3DC0 27*c8a74b45SHope Wang 28*c8a74b45SHope Wang /* Central control */ 29*c8a74b45SHope Wang static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = { 30*c8a74b45SHope Wang {0x0C53A2A0, 0x1000}, 31*c8a74b45SHope Wang {0x0C53A2A4, 0x1000} 32*c8a74b45SHope Wang }; 33*c8a74b45SHope Wang 34*c8a74b45SHope Wang static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = { 35*c8a74b45SHope Wang {0x0C530404, 0x3A1000}, 36*c8a74b45SHope Wang {0x0C530428, 0x13E0408}, 37*c8a74b45SHope Wang {0x0C530434, 0xB22800}, 38*c8a74b45SHope Wang {0x0C53043C, 0x750}, 39*c8a74b45SHope Wang {0x0C530440, 0x0222c4cc} 40*c8a74b45SHope Wang }; 41*c8a74b45SHope Wang 42*c8a74b45SHope Wang static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00}; 43*c8a74b45SHope Wang 44*c8a74b45SHope Wang #endif /* PTP3_PLAT_COMMON_H */ 45