xref: /rk3399_ARM-atf/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h (revision 05d22c3045e2e972c2262b9ccd6c82cb7545bf83)
1 /*
2  * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PMIC_WRAP_INIT_COMMON_H
8 #define PMIC_WRAP_INIT_COMMON_H
9 
10 #include <stdint.h>
11 
12 #include "platform_def.h"
13 
14 /* external API */
15 int32_t pmic_wrap_test(void);
16 int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
17 int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
18 int32_t pwrap_write(uint32_t adr, uint32_t wdata);
19 int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
20 
21 #define GET_SWINF_INIT_DONE(x)	((x>>15) & 0x00000001)
22 #define GET_WACS_FSM(x)		((x >> 1) & 0x7)
23 
24 /* macro for SWINF_FSM */
25 #define SWINF_FSM_IDLE		(0x00)
26 #define SWINF_FSM_REQ		(0x02)
27 #define SWINF_FSM_WFDLE		(0x04)
28 #define SWINF_FSM_WFVLDCLR	(0x06)
29 #define SWINF_INIT_DONE		(0x01)
30 
31 /* timeout setting */
32 #define PWRAP_READ_US		(1000)
33 #define PWRAP_WAIT_IDLE_US	(1000)
34 
35 /* error information flag */
36 enum pwrap_errno {
37 	E_PWR_INVALID_ARG		= 1,
38 	E_PWR_INVALID_RW		= 2,
39 	E_PWR_INVALID_ADDR		= 3,
40 	E_PWR_INVALID_WDAT		= 4,
41 	E_PWR_INVALID_OP_MANUAL		= 5,
42 	E_PWR_NOT_IDLE_STATE		= 6,
43 	E_PWR_NOT_INIT_DONE		= 7,
44 	E_PWR_NOT_INIT_DONE_READ	= 8,
45 	E_PWR_WAIT_IDLE_TIMEOUT		= 9,
46 	E_PWR_WAIT_IDLE_TIMEOUT_READ	= 10,
47 	E_PWR_INIT_SIDLY_FAIL		= 11,
48 	E_PWR_RESET_TIMEOUT		= 12,
49 	E_PWR_TIMEOUT			= 13,
50 	E_PWR_INVALID_SWINF		= 14,
51 	E_PWR_INVALID_CMD		= 15,
52 	E_PWR_INVALID_PMIFID		= 16,
53 	E_PWR_INVALID_SLVID		= 17,
54 	E_PWR_INVALID_BYTECNT		= 18,
55 	E_PWR_INIT_RESET_SPI		= 20,
56 	E_PWR_INIT_SIDLY		= 21,
57 	E_PWR_INIT_REG_CLOCK		= 22,
58 	E_PWR_INIT_ENABLE_PMIC		= 23,
59 	E_PWR_INIT_DIO			= 24,
60 	E_PWR_INIT_CIPHER		= 25,
61 	E_PWR_INIT_WRITE_TEST		= 26,
62 	E_PWR_INIT_ENABLE_CRC		= 27,
63 	E_PWR_INIT_ENABLE_DEWRAP	= 28,
64 	E_PWR_INIT_ENABLE_EVENT		= 29,
65 	E_PWR_READ_TEST_FAIL		= 30,
66 	E_PWR_WRITE_TEST_FAIL		= 31,
67 	E_PWR_SWITCH_DIO		= 32,
68 };
69 
70 #endif /* PMIC_WRAP_INIT_COMMON_H */
71