1*868b2d60SZhigang Qin /*
2*868b2d60SZhigang Qin * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3*868b2d60SZhigang Qin * SPDX-License-Identifier: BSD-3-Clause
4*868b2d60SZhigang Qin */
5*868b2d60SZhigang Qin
6*868b2d60SZhigang Qin #include <errno.h>
7*868b2d60SZhigang Qin
8*868b2d60SZhigang Qin #include <common/debug.h>
9*868b2d60SZhigang Qin #include <lib/mmio.h>
10*868b2d60SZhigang Qin
11*868b2d60SZhigang Qin #include "../mt6359p/registers.h"
12*868b2d60SZhigang Qin #include <drivers/pmic/pmic_shutdown_cfg.h>
13*868b2d60SZhigang Qin #include <drivers/spmi/spmi_common.h>
14*868b2d60SZhigang Qin #include <drivers/spmi_api.h>
15*868b2d60SZhigang Qin #include <lib/mtk_init/mtk_init.h>
16*868b2d60SZhigang Qin #include <pmic_wrap_init_common.h>
17*868b2d60SZhigang Qin
18*868b2d60SZhigang Qin #define MT6319_RG_SEQ_OFF 0x2d
19*868b2d60SZhigang Qin #define MT6319_TOP_RST_MISC_CLR 0x128
20*868b2d60SZhigang Qin #define MT6319_TOP_DIG_WPK_H 0x3a9
21*868b2d60SZhigang Qin #define MT6319_TOP_DIG_WPK_H_MASK 0xFF
22*868b2d60SZhigang Qin #define MT6319_TOP_DIG_WPK_H_SHIFT 0
23*868b2d60SZhigang Qin #define MT6319_TOP_DIG_WPK 0x3a8
24*868b2d60SZhigang Qin #define MT6319_TOP_DIG_WPK_MASK 0xFF
25*868b2d60SZhigang Qin #define MT6319_TOP_DIG_WPK_SHIFT 0
26*868b2d60SZhigang Qin
27*868b2d60SZhigang Qin
pmic_shutdown_cfg(void)28*868b2d60SZhigang Qin int pmic_shutdown_cfg(void)
29*868b2d60SZhigang Qin {
30*868b2d60SZhigang Qin /*
31*868b2d60SZhigang Qin * In mt8189, the pmic_shutdown_cfg() api does not need to read and write the
32*868b2d60SZhigang Qin * pmic register to determine the return value and in order not to modify the
33*868b2d60SZhigang Qin * common code to affect other ICs, the pmic_shutdown_cfg() will directly
34*868b2d60SZhigang Qin * return 1.
35*868b2d60SZhigang Qin */
36*868b2d60SZhigang Qin return 1;
37*868b2d60SZhigang Qin }
38*868b2d60SZhigang Qin
shutdown_slave_dev(struct spmi_device * dev)39*868b2d60SZhigang Qin static void shutdown_slave_dev(struct spmi_device *dev)
40*868b2d60SZhigang Qin {
41*868b2d60SZhigang Qin spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0x63,
42*868b2d60SZhigang Qin MT6319_TOP_DIG_WPK_H_MASK,
43*868b2d60SZhigang Qin MT6319_TOP_DIG_WPK_H_SHIFT);
44*868b2d60SZhigang Qin spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0x15,
45*868b2d60SZhigang Qin MT6319_TOP_DIG_WPK_MASK,
46*868b2d60SZhigang Qin MT6319_TOP_DIG_WPK_SHIFT);
47*868b2d60SZhigang Qin
48*868b2d60SZhigang Qin /* Disable WDTRSTB_EN */
49*868b2d60SZhigang Qin spmi_ext_register_writel_field(dev, MT6319_TOP_RST_MISC_CLR, 1, 0x1, 0);
50*868b2d60SZhigang Qin /* Normal sequence power off when PAD_EN falling */
51*868b2d60SZhigang Qin spmi_ext_register_writel_field(dev, MT6319_RG_SEQ_OFF, 1, 0x1, 0);
52*868b2d60SZhigang Qin
53*868b2d60SZhigang Qin spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0,
54*868b2d60SZhigang Qin MT6319_TOP_DIG_WPK_H_MASK,
55*868b2d60SZhigang Qin MT6319_TOP_DIG_WPK_H_SHIFT);
56*868b2d60SZhigang Qin spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0,
57*868b2d60SZhigang Qin MT6319_TOP_DIG_WPK_MASK,
58*868b2d60SZhigang Qin MT6319_TOP_DIG_WPK_SHIFT);
59*868b2d60SZhigang Qin
60*868b2d60SZhigang Qin }
61*868b2d60SZhigang Qin
spmi_shutdown(void)62*868b2d60SZhigang Qin int spmi_shutdown(void)
63*868b2d60SZhigang Qin {
64*868b2d60SZhigang Qin struct spmi_device *mt6319_sdev;
65*868b2d60SZhigang Qin
66*868b2d60SZhigang Qin mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_7);
67*868b2d60SZhigang Qin if (!mt6319_sdev)
68*868b2d60SZhigang Qin return -ENODEV;
69*868b2d60SZhigang Qin shutdown_slave_dev(mt6319_sdev);
70*868b2d60SZhigang Qin
71*868b2d60SZhigang Qin if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
72*868b2d60SZhigang Qin mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189H) {
73*868b2d60SZhigang Qin mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_8);
74*868b2d60SZhigang Qin if (!mt6319_sdev)
75*868b2d60SZhigang Qin return -ENODEV;
76*868b2d60SZhigang Qin shutdown_slave_dev(mt6319_sdev);
77*868b2d60SZhigang Qin }
78*868b2d60SZhigang Qin
79*868b2d60SZhigang Qin /* clear main pmic power hold */
80*868b2d60SZhigang Qin pwrap_write_field(MT6359P_PPCCTL0, 0, 0x1, 0);
81*868b2d60SZhigang Qin
82*868b2d60SZhigang Qin return 0;
83*868b2d60SZhigang Qin }
84