1*41004253Sirving-ch-lin /* 2*41004253Sirving-ch-lin * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3*41004253Sirving-ch-lin * 4*41004253Sirving-ch-lin * SPDX-License-Identifier: BSD-3-Clause 5*41004253Sirving-ch-lin */ 6*41004253Sirving-ch-lin 7*41004253Sirving-ch-lin #ifndef MTCMOS_H 8*41004253Sirving-ch-lin #define MTCMOS_H 9*41004253Sirving-ch-lin 10*41004253Sirving-ch-lin enum mtcmos_state { 11*41004253Sirving-ch-lin STA_POWER_DOWN, 12*41004253Sirving-ch-lin STA_POWER_ON, 13*41004253Sirving-ch-lin }; 14*41004253Sirving-ch-lin 15*41004253Sirving-ch-lin struct bus_protect { 16*41004253Sirving-ch-lin uint32_t en_addr; 17*41004253Sirving-ch-lin uint32_t rdy_addr; 18*41004253Sirving-ch-lin uint32_t mask; 19*41004253Sirving-ch-lin }; 20*41004253Sirving-ch-lin 21*41004253Sirving-ch-lin int spm_mtcmos_ctrl_ufs0(enum mtcmos_state state); 22*41004253Sirving-ch-lin int spm_mtcmos_ctrl_ufs0_phy(enum mtcmos_state state); 23*41004253Sirving-ch-lin 24*41004253Sirving-ch-lin #endif /* MTCMOS_H */ 25