xref: /rk3399_ARM-atf/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.h (revision 3ba36ea07ca22c748b5adcf5d9bff00e752681d7)
1 /*
2  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_
8 #define PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_
9 
10 #include <mtcmos_common.h>
11 #include <platform_def.h>
12 
13 #define RTFF_SAVE	BIT(24)
14 #define RTFF_NRESTORE	BIT(25)
15 #define RTFF_CLK_DIS	BIT(26)
16 #define RTFF_SAVE_FLAG	BIT(27)
17 
18 #define POWERON_CONFIG_EN	(SPM_BASE + 0x0)
19 #define UFS0_PWR_CON		(SPM_BASE + 0xE2C)
20 #define UFS0_PHY_PWR_CON	(SPM_BASE + 0xE30)
21 
22 #define SPM_BUS_PROTECT_EN_SET		(SPM_BASE + 0x90DC)
23 #define SPM_BUS_PROTECT_EN_CLR		(SPM_BASE + 0x90E0)
24 #define SPM_BUS_PROTECT_CG_EN_SET	(SPM_BASE + 0x90F4)
25 #define SPM_BUS_PROTECT_CG_EN_CLR	(SPM_BASE + 0x90F8)
26 #define SPM_BUS_PROTECT_RDY_STA		(SPM_BASE + 0x9208)
27 
28 #define UFS0_PROT_STEP1_MASK		BIT(11)
29 #define UFS0_PHY_PROT_STEP1_MASK	BIT(12)
30 
31 static const struct bus_protect ufs0_bus_prot_set_table[] = {
32 	{SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PROT_STEP1_MASK},
33 	{SPM_BUS_PROTECT_EN_SET, SPM_BUS_PROTECT_RDY_STA, UFS0_PROT_STEP1_MASK},
34 	{SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK},
35 };
36 
37 static const struct bus_protect ufs0_bus_prot_clr_table[] = {
38 	{SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PROT_STEP1_MASK},
39 	{SPM_BUS_PROTECT_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK},
40 	{SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK},
41 };
42 
43 static const struct bus_protect ufs0_phy_bus_prot_set_table[] = {
44 	{SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PHY_PROT_STEP1_MASK},
45 	{SPM_BUS_PROTECT_EN_SET, SPM_BUS_PROTECT_RDY_STA, UFS0_PHY_PROT_STEP1_MASK},
46 	{SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK},
47 };
48 
49 static const struct bus_protect ufs0_phy_bus_prot_clr_table[] = {
50 	{SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PHY_PROT_STEP1_MASK},
51 	{SPM_BUS_PROTECT_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK},
52 	{SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK},
53 };
54 
55 #endif /* PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ */
56