1*41004253Sirving-ch-lin /* 2*41004253Sirving-ch-lin * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3*41004253Sirving-ch-lin * 4*41004253Sirving-ch-lin * SPDX-License-Identifier: BSD-3-Clause 5*41004253Sirving-ch-lin */ 6*41004253Sirving-ch-lin 7*41004253Sirving-ch-lin #ifndef PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ 8*41004253Sirving-ch-lin #define PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ 9*41004253Sirving-ch-lin 10*41004253Sirving-ch-lin #include <mtcmos_common.h> 11*41004253Sirving-ch-lin #include <platform_def.h> 12*41004253Sirving-ch-lin 13*41004253Sirving-ch-lin #define RTFF_SAVE BIT(24) 14*41004253Sirving-ch-lin #define RTFF_NRESTORE BIT(25) 15*41004253Sirving-ch-lin #define RTFF_CLK_DIS BIT(26) 16*41004253Sirving-ch-lin #define RTFF_SAVE_FLAG BIT(27) 17*41004253Sirving-ch-lin 18*41004253Sirving-ch-lin #define POWERON_CONFIG_EN (SPM_BASE + 0x0) 19*41004253Sirving-ch-lin #define UFS0_PWR_CON (SPM_BASE + 0xE2C) 20*41004253Sirving-ch-lin #define UFS0_PHY_PWR_CON (SPM_BASE + 0xE30) 21*41004253Sirving-ch-lin 22*41004253Sirving-ch-lin #define SPM_BUS_PROTECT_EN_SET (SPM_BASE + 0x90DC) 23*41004253Sirving-ch-lin #define SPM_BUS_PROTECT_EN_CLR (SPM_BASE + 0x90E0) 24*41004253Sirving-ch-lin #define SPM_BUS_PROTECT_CG_EN_SET (SPM_BASE + 0x90F4) 25*41004253Sirving-ch-lin #define SPM_BUS_PROTECT_CG_EN_CLR (SPM_BASE + 0x90F8) 26*41004253Sirving-ch-lin #define SPM_BUS_PROTECT_RDY_STA (SPM_BASE + 0x9208) 27*41004253Sirving-ch-lin 28*41004253Sirving-ch-lin #define UFS0_PROT_STEP1_MASK BIT(11) 29*41004253Sirving-ch-lin #define UFS0_PHY_PROT_STEP1_MASK BIT(12) 30*41004253Sirving-ch-lin 31*41004253Sirving-ch-lin static const struct bus_protect ufs0_bus_prot_set_table[] = { 32*41004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PROT_STEP1_MASK}, 33*41004253Sirving-ch-lin {SPM_BUS_PROTECT_EN_SET, SPM_BUS_PROTECT_RDY_STA, UFS0_PROT_STEP1_MASK}, 34*41004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK}, 35*41004253Sirving-ch-lin }; 36*41004253Sirving-ch-lin 37*41004253Sirving-ch-lin static const struct bus_protect ufs0_bus_prot_clr_table[] = { 38*41004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PROT_STEP1_MASK}, 39*41004253Sirving-ch-lin {SPM_BUS_PROTECT_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK}, 40*41004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PROT_STEP1_MASK}, 41*41004253Sirving-ch-lin }; 42*41004253Sirving-ch-lin 43*41004253Sirving-ch-lin static const struct bus_protect ufs0_phy_bus_prot_set_table[] = { 44*41004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 45*41004253Sirving-ch-lin {SPM_BUS_PROTECT_EN_SET, SPM_BUS_PROTECT_RDY_STA, UFS0_PHY_PROT_STEP1_MASK}, 46*41004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 47*41004253Sirving-ch-lin }; 48*41004253Sirving-ch-lin 49*41004253Sirving-ch-lin static const struct bus_protect ufs0_phy_bus_prot_clr_table[] = { 50*41004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_SET, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 51*41004253Sirving-ch-lin {SPM_BUS_PROTECT_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 52*41004253Sirving-ch-lin {SPM_BUS_PROTECT_CG_EN_CLR, 0x0, UFS0_PHY_PROT_STEP1_MASK}, 53*41004253Sirving-ch-lin }; 54*41004253Sirving-ch-lin 55*41004253Sirving-ch-lin #endif /* PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ */ 56