1*d8c718c5Sirving-ch-lin /* 2*d8c718c5Sirving-ch-lin * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3*d8c718c5Sirving-ch-lin * 4*d8c718c5Sirving-ch-lin * SPDX-License-Identifier: BSD-3-Clause 5*d8c718c5Sirving-ch-lin */ 6*d8c718c5Sirving-ch-lin 7*d8c718c5Sirving-ch-lin #ifndef PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8189_MTCMOS_H_ 8*d8c718c5Sirving-ch-lin #define PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8189_MTCMOS_H_ 9*d8c718c5Sirving-ch-lin 10*d8c718c5Sirving-ch-lin #include <mtcmos_common.h> 11*d8c718c5Sirving-ch-lin #include <platform_def.h> 12*d8c718c5Sirving-ch-lin 13*d8c718c5Sirving-ch-lin #define RTFF_SAVE BIT(24) 14*d8c718c5Sirving-ch-lin #define RTFF_NRESTORE BIT(25) 15*d8c718c5Sirving-ch-lin #define RTFF_CLK_DIS BIT(28) 16*d8c718c5Sirving-ch-lin 17*d8c718c5Sirving-ch-lin #define VLPCFG_REG_BASE (0x1C00C000) 18*d8c718c5Sirving-ch-lin #define POWERON_CONFIG_EN (SPM_BASE + 0x0) 19*d8c718c5Sirving-ch-lin #define UFS0_PWR_CON (SPM_BASE + 0x0E10) 20*d8c718c5Sirving-ch-lin #define UFS0_PHY_PWR_CON (SPM_BASE + 0x0E14) 21*d8c718c5Sirving-ch-lin 22*d8c718c5Sirving-ch-lin #define PERISYS_PROTECT_EN_STA_0 (INFRACFG_AO_BASE + 0x0C80) 23*d8c718c5Sirving-ch-lin #define PERISYS_PROTECT_EN_STA_0_SET (INFRACFG_AO_BASE + 0x0C84) 24*d8c718c5Sirving-ch-lin #define PERISYS_PROTECT_EN_STA_0_CLR (INFRACFG_AO_BASE + 0x0C88) 25*d8c718c5Sirving-ch-lin #define PERISYS_PROTECT_RDY_STA_0 (INFRACFG_AO_BASE + 0x0C8C) 26*d8c718c5Sirving-ch-lin #define VLP_TOPAXI_PROTECTEN (VLPCFG_REG_BASE + 0x0210) 27*d8c718c5Sirving-ch-lin #define VLP_TOPAXI_PROTECTEN_SET (VLPCFG_REG_BASE + 0x0214) 28*d8c718c5Sirving-ch-lin #define VLP_TOPAXI_PROTECTEN_CLR (VLPCFG_REG_BASE + 0x0218) 29*d8c718c5Sirving-ch-lin #define VLP_TOPAXI_PROTECTEN_STA1 (VLPCFG_REG_BASE + 0x0220) 30*d8c718c5Sirving-ch-lin 31*d8c718c5Sirving-ch-lin #define UFS0_PROT_STEP1_0_MASK BIT(5) 32*d8c718c5Sirving-ch-lin #define UFS0_PROT_STEP2_0_MASK BIT(4) 33*d8c718c5Sirving-ch-lin #define UFS0_PROT_STEP3_0_MASK BIT(6) 34*d8c718c5Sirving-ch-lin 35*d8c718c5Sirving-ch-lin static const struct bus_protect ufs0_bus_prot_set_table[] = { 36*d8c718c5Sirving-ch-lin {VLP_TOPAXI_PROTECTEN_SET, VLP_TOPAXI_PROTECTEN_STA1, UFS0_PROT_STEP1_0_MASK}, 37*d8c718c5Sirving-ch-lin {PERISYS_PROTECT_EN_STA_0_SET, PERISYS_PROTECT_RDY_STA_0, UFS0_PROT_STEP2_0_MASK}, 38*d8c718c5Sirving-ch-lin {VLP_TOPAXI_PROTECTEN_SET, VLP_TOPAXI_PROTECTEN_STA1, UFS0_PROT_STEP3_0_MASK}, 39*d8c718c5Sirving-ch-lin }; 40*d8c718c5Sirving-ch-lin 41*d8c718c5Sirving-ch-lin static const struct bus_protect ufs0_bus_prot_clr_table[] = { 42*d8c718c5Sirving-ch-lin {VLP_TOPAXI_PROTECTEN_CLR, 0x0, UFS0_PROT_STEP3_0_MASK}, 43*d8c718c5Sirving-ch-lin {PERISYS_PROTECT_EN_STA_0_CLR, 0x0, UFS0_PROT_STEP2_0_MASK}, 44*d8c718c5Sirving-ch-lin {VLP_TOPAXI_PROTECTEN_CLR, 0x0, UFS0_PROT_STEP1_0_MASK}, 45*d8c718c5Sirving-ch-lin }; 46*d8c718c5Sirving-ch-lin 47*d8c718c5Sirving-ch-lin static const struct bus_protect ufs0_phy_bus_prot_set_table[] = {}; 48*d8c718c5Sirving-ch-lin static const struct bus_protect ufs0_phy_bus_prot_clr_table[] = {}; 49*d8c718c5Sirving-ch-lin 50*d8c718c5Sirving-ch-lin #endif /* PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8189_MTCMOS_H_ */ 51