1be457248SChengci Xu /* 2be457248SChengci Xu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3be457248SChengci Xu * 4be457248SChengci Xu * SPDX-License-Identifier: BSD-3-Clause 5be457248SChengci Xu */ 6be457248SChengci Xu 7be457248SChengci Xu #ifndef IOMMU_PRIV_H 8be457248SChengci Xu #define IOMMU_PRIV_H 9be457248SChengci Xu 10be457248SChengci Xu #include <common/debug.h> 11be457248SChengci Xu #include <lib/mmio.h> 12*5fb5ff56Skiwi liu #include <mtk_iommu_plat.h> 13be457248SChengci Xu #include <mtk_sip_svc.h> 14be457248SChengci Xu 15be457248SChengci Xu #define LARB_CFG_ENTRY(bs, p_nr, dom) \ 16be457248SChengci Xu { .base = (bs), .port_nr = (p_nr), \ 17be457248SChengci Xu .dom_id = (dom), .to_sram = 0, } 18be457248SChengci Xu 19be457248SChengci Xu #define LARB_CFG_ENTRY_WITH_PATH(bs, p_nr, dom, sram) \ 20be457248SChengci Xu { .base = (bs), .port_nr = (p_nr), \ 21be457248SChengci Xu .dom_id = (dom), .to_sram = (sram), } 22be457248SChengci Xu 23be457248SChengci Xu #define IFR_MST_CFG_ENTRY(idx, bit) \ 24be457248SChengci Xu { .cfg_addr_idx = (idx), .r_mmu_en_bit = (bit), } 25be457248SChengci Xu 26*5fb5ff56Skiwi liu #define SEC_IOMMU_CFG_ENTRY(s_bs) \ 27*5fb5ff56Skiwi liu { .base = (s_bs), } 28*5fb5ff56Skiwi liu 29be457248SChengci Xu enum IOMMU_ATF_CMD { 30be457248SChengci Xu IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to enable iommu */ 31be457248SChengci Xu IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */ 32*5fb5ff56Skiwi liu IOMMU_ATF_CMD_GET_SECURE_IOMMU_STATUS, /* For secure iommu translation fault report */ 33be457248SChengci Xu IOMMU_ATF_CMD_COUNT, 34be457248SChengci Xu }; 35be457248SChengci Xu 36be457248SChengci Xu struct mtk_smi_larb_config { 37be457248SChengci Xu uint32_t base; 38be457248SChengci Xu uint32_t port_nr; 39be457248SChengci Xu uint32_t dom_id; 40be457248SChengci Xu uint32_t to_sram; 41be457248SChengci Xu uint32_t sec_en_msk; 42be457248SChengci Xu }; 43be457248SChengci Xu 44be457248SChengci Xu struct mtk_ifr_mst_config { 45be457248SChengci Xu uint8_t cfg_addr_idx; 46be457248SChengci Xu uint8_t r_mmu_en_bit; 47be457248SChengci Xu }; 48be457248SChengci Xu 49*5fb5ff56Skiwi liu struct mtk_secure_iommu_config { 50*5fb5ff56Skiwi liu uint32_t base; 51*5fb5ff56Skiwi liu }; 52*5fb5ff56Skiwi liu 53*5fb5ff56Skiwi liu 54*5fb5ff56Skiwi liu #ifdef ATF_MTK_SMI_LARB_CFG_SUPPORT 55*5fb5ff56Skiwi liu /* mm smi larb security feature is used */ 56*5fb5ff56Skiwi liu extern struct mtk_smi_larb_config *g_larb_cfg; 57*5fb5ff56Skiwi liu extern const unsigned int g_larb_num; 58*5fb5ff56Skiwi liu #endif 59*5fb5ff56Skiwi liu 60*5fb5ff56Skiwi liu #ifdef ATF_MTK_INFRA_MASTER_CFG_SUPPORT 61*5fb5ff56Skiwi liu /* infra iommu is used */ 62*5fb5ff56Skiwi liu extern struct mtk_ifr_mst_config *g_ifr_mst_cfg; 63*5fb5ff56Skiwi liu extern const unsigned int g_ifr_mst_num; 64*5fb5ff56Skiwi liu extern uint32_t *g_ifr_mst_cfg_base; 65*5fb5ff56Skiwi liu extern uint32_t *g_ifr_mst_cfg_offs; 66*5fb5ff56Skiwi liu extern void mtk_infra_iommu_enable_protect(void); 67*5fb5ff56Skiwi liu #endif 68*5fb5ff56Skiwi liu 69*5fb5ff56Skiwi liu #ifdef ATF_MTK_IOMMU_CFG_SUPPORT 70*5fb5ff56Skiwi liu /* secure iommu is used */ 71*5fb5ff56Skiwi liu extern struct mtk_secure_iommu_config *g_sec_iommu_cfg; 72*5fb5ff56Skiwi liu extern const unsigned int g_sec_iommu_num; 73*5fb5ff56Skiwi liu #endif 74*5fb5ff56Skiwi liu 75be457248SChengci Xu #endif /* IOMMU_PRIV_H */ 76