1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <mtk_iommu_priv.h> 8 #include <mtk_mmap_pool.h> 9 #include <platform_def.h> 10 11 /* mm iommu */ 12 #define SMI_L0_ID (0) 13 #define SMI_L1_ID (1) 14 #define SMI_L2_ID (2) 15 #define SMI_L4_ID (3) 16 #define SMI_L7_ID (4) 17 #define SMI_L9_ID (5) 18 #define SMI_L11_ID (6) 19 #define SMI_L13_ID (7) 20 #define SMI_L14_ID (8) 21 #define SMI_L16_ID (9) 22 #define SMI_L17_ID (10) 23 #define SMI_L19_ID (11) 24 #define SMI_L20_ID (12) 25 26 /* infra iommu */ 27 #define PERICFG_AO_IOMMU_0 (0x90) 28 #define PERICFG_AO_IOMMU_1 (0x94) 29 #define MMU_DEV_PCIE_0 (0) 30 #define IFR_CFG_GROUP_NUM (1) 31 32 static struct mtk_smi_larb_config mt8189_larb_cfg[] = { 33 [SMI_L0_ID] = LARB_CFG_ENTRY(SMI_LARB_0_BASE, 8, 0), 34 [SMI_L1_ID] = LARB_CFG_ENTRY(SMI_LARB_1_BASE, 8, 0), 35 [SMI_L2_ID] = LARB_CFG_ENTRY(SMI_LARB_2_BASE, 11, 0), 36 [SMI_L4_ID] = LARB_CFG_ENTRY(SMI_LARB_4_BASE, 12, 0), 37 [SMI_L7_ID] = LARB_CFG_ENTRY(SMI_LARB_7_BASE, 18, 0), 38 [SMI_L9_ID] = LARB_CFG_ENTRY(SMI_LARB_9_BASE, 29, 0), 39 [SMI_L11_ID] = LARB_CFG_ENTRY(SMI_LARB_11_BASE, 29, 0), 40 [SMI_L13_ID] = LARB_CFG_ENTRY(SMI_LARB_13_BASE, 15, 0), 41 [SMI_L14_ID] = LARB_CFG_ENTRY(SMI_LARB_14_BASE, 10, 0), 42 [SMI_L16_ID] = LARB_CFG_ENTRY(SMI_LARB_16_BASE, 17, 0), 43 [SMI_L17_ID] = LARB_CFG_ENTRY(SMI_LARB_17_BASE, 17, 0), 44 [SMI_L19_ID] = LARB_CFG_ENTRY(SMI_LARB_19_BASE, 4, 0), 45 [SMI_L20_ID] = LARB_CFG_ENTRY(SMI_LARB_20_BASE, 6, 0), 46 }; 47 48 static uint32_t mt8189_ifr_mst_cfg_base[IFR_CFG_GROUP_NUM] = { 49 PERICFG_AO_BASE, 50 }; 51 static uint32_t mt8189_ifr_mst_cfg_offs[IFR_CFG_GROUP_NUM] = { 52 PERICFG_AO_IOMMU_1, 53 }; 54 static struct mtk_ifr_mst_config mt8189_ifr_mst_cfg[] = { 55 [MMU_DEV_PCIE_0] = IFR_MST_CFG_ENTRY(0, 0), 56 }; 57 58 struct mtk_smi_larb_config *g_larb_cfg = &mt8189_larb_cfg[0]; 59 const unsigned int g_larb_num = ARRAY_SIZE(mt8189_larb_cfg); 60 61 static struct mtk_secure_iommu_config mt8189_secure_iommu_config[] = { 62 SEC_IOMMU_CFG_ENTRY(MM_IOMMU_BASE), 63 }; 64 65 struct mtk_secure_iommu_config *g_sec_iommu_cfg = &mt8189_secure_iommu_config[0]; 66 const unsigned int g_sec_iommu_num = ARRAY_SIZE(mt8189_secure_iommu_config); 67 68 struct mtk_ifr_mst_config *g_ifr_mst_cfg = &mt8189_ifr_mst_cfg[0]; 69 const unsigned int g_ifr_mst_num = ARRAY_SIZE(mt8189_ifr_mst_cfg); 70 71 uint32_t *g_ifr_mst_cfg_base = &mt8189_ifr_mst_cfg_base[0]; 72 uint32_t *g_ifr_mst_cfg_offs = &mt8189_ifr_mst_cfg_offs[0]; 73 74 /** 75 * Protect infra iommu enable setting registers as secure access. 76 * This is removed in MT8189, just return here. 77 */ 78 void mtk_infra_iommu_enable_protect(void) 79 { 80 } 81