1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <mtk_iommu_priv.h> 8 #include <mtk_mmap_pool.h> 9 #include <platform_def.h> 10 11 /* mm iommu */ 12 #define SMI_L0_ID (0) 13 #define SMI_L1_ID (1) 14 #define SMI_L2_ID (2) 15 #define SMI_L3_ID (3) 16 #define SMI_L4_ID (4) 17 #define SMI_L5_ID (5) 18 #define SMI_L6_ID (6) 19 #define SMI_L7_ID (7) 20 #define SMI_L9_ID (8) 21 #define SMI_L10_ID (9) 22 #define SMI_L11A_ID (10) 23 #define SMI_L11B_ID (11) 24 #define SMI_L11C_ID (12) 25 #define SMI_L12_ID (13) 26 #define SMI_L13_ID (14) 27 #define SMI_L14_ID (15) 28 #define SMI_L15_ID (16) 29 #define SMI_L16A_ID (17) 30 #define SMI_L16B_ID (18) 31 #define SMI_L17A_ID (19) 32 #define SMI_L17B_ID (20) 33 #define SMI_L19_ID (21) 34 #define SMI_L21_ID (22) 35 #define SMI_L23_ID (23) 36 #define SMI_L27_ID (24) 37 #define SMI_L28_ID (25) 38 39 /* infra iommu */ 40 #define PERI_MST_PROT (0x710) 41 #define PERICFG_AO_IOMMU_1 (0x714) 42 #define MMU_DEV_PCIE_0 (0) 43 #define IFR_CFG_GROUP_NUM (1) 44 45 static struct mtk_smi_larb_config mt8188_larb_cfg[] = { 46 [SMI_L0_ID] = LARB_CFG_ENTRY(SMI_LARB_0_BASE, 7, 0), 47 [SMI_L1_ID] = LARB_CFG_ENTRY(SMI_LARB_1_BASE, 7, 0), 48 [SMI_L2_ID] = LARB_CFG_ENTRY(SMI_LARB_2_BASE, 5, 0), 49 [SMI_L3_ID] = LARB_CFG_ENTRY(SMI_LARB_3_BASE, 7, 0), 50 [SMI_L4_ID] = LARB_CFG_ENTRY(SMI_LARB_4_BASE, 7, 0), 51 [SMI_L5_ID] = LARB_CFG_ENTRY(SMI_LARB_5_BASE, 8, 0), 52 [SMI_L6_ID] = LARB_CFG_ENTRY(SMI_LARB_6_BASE, 4, 0), 53 [SMI_L7_ID] = LARB_CFG_ENTRY(SMI_LARB_7_BASE, 3, 0), 54 [SMI_L9_ID] = LARB_CFG_ENTRY(SMI_LARB_9_BASE, 25, 0), 55 [SMI_L10_ID] = LARB_CFG_ENTRY(SMI_LARB_10_BASE, 20, 0), 56 [SMI_L11A_ID] = LARB_CFG_ENTRY(SMI_LARB_11A_BASE, 30, 0), 57 [SMI_L11B_ID] = LARB_CFG_ENTRY(SMI_LARB_11B_BASE, 30, 0), 58 [SMI_L11C_ID] = LARB_CFG_ENTRY(SMI_LARB_11C_BASE, 30, 0), 59 [SMI_L12_ID] = LARB_CFG_ENTRY(SMI_LARB_12_BASE, 16, 0), 60 [SMI_L13_ID] = LARB_CFG_ENTRY(SMI_LARB_13_BASE, 24, 0), 61 [SMI_L14_ID] = LARB_CFG_ENTRY(SMI_LARB_14_BASE, 23, 0), 62 [SMI_L15_ID] = LARB_CFG_ENTRY(SMI_LARB_15_BASE, 19, 0), 63 [SMI_L16A_ID] = LARB_CFG_ENTRY(SMI_LARB_16A_BASE, 17, 0), 64 [SMI_L16B_ID] = LARB_CFG_ENTRY(SMI_LARB_16B_BASE, 17, 0), 65 [SMI_L17A_ID] = LARB_CFG_ENTRY(SMI_LARB_17A_BASE, 7, 0), 66 [SMI_L17B_ID] = LARB_CFG_ENTRY(SMI_LARB_17B_BASE, 7, 0), 67 /* venc nbm ports (5/6/11/15/16/17) to sram */ 68 [SMI_L19_ID] = LARB_CFG_ENTRY_WITH_PATH(SMI_LARB_19_BASE, 27, 0, 0x38860), 69 [SMI_L21_ID] = LARB_CFG_ENTRY(SMI_LARB_21_BASE, 11, 0), 70 [SMI_L23_ID] = LARB_CFG_ENTRY(SMI_LARB_23_BASE, 9, 0), 71 [SMI_L27_ID] = LARB_CFG_ENTRY(SMI_LARB_27_BASE, 4, 0), 72 [SMI_L28_ID] = LARB_CFG_ENTRY(SMI_LARB_28_BASE, 0, 0), 73 }; 74 75 static bool is_protected; 76 77 static uint32_t mt8188_ifr_mst_cfg_base[IFR_CFG_GROUP_NUM] = { 78 PERICFG_AO_BASE, 79 }; 80 static uint32_t mt8188_ifr_mst_cfg_offs[IFR_CFG_GROUP_NUM] = { 81 PERICFG_AO_IOMMU_1, 82 }; 83 static struct mtk_ifr_mst_config mt8188_ifr_mst_cfg[] = { 84 [MMU_DEV_PCIE_0] = IFR_MST_CFG_ENTRY(0, 18), 85 }; 86 87 struct mtk_smi_larb_config *g_larb_cfg = &mt8188_larb_cfg[0]; 88 const unsigned int g_larb_num = ARRAY_SIZE(mt8188_larb_cfg); 89 90 static struct mtk_secure_iommu_config mt8188_secure_iommu_config[] = { 91 SEC_IOMMU_CFG_ENTRY(VDO_SECURE_IOMMU_BASE), 92 SEC_IOMMU_CFG_ENTRY(VPP_SECURE_IOMMU_BASE), 93 }; 94 95 struct mtk_secure_iommu_config *g_sec_iommu_cfg = &mt8188_secure_iommu_config[0]; 96 const unsigned int g_sec_iommu_num = ARRAY_SIZE(mt8188_secure_iommu_config); 97 98 struct mtk_ifr_mst_config *g_ifr_mst_cfg = &mt8188_ifr_mst_cfg[0]; 99 const unsigned int g_ifr_mst_num = ARRAY_SIZE(mt8188_ifr_mst_cfg); 100 101 uint32_t *g_ifr_mst_cfg_base = &mt8188_ifr_mst_cfg_base[0]; 102 uint32_t *g_ifr_mst_cfg_offs = &mt8188_ifr_mst_cfg_offs[0]; 103 104 /* Protect infra iommu enable setting registers as secure access. */ 105 void mtk_infra_iommu_enable_protect(void) 106 { 107 if (!is_protected) { 108 mmio_write_32(PERICFG_AO_BASE + PERI_MST_PROT, 0xffffffff); 109 is_protected = true; 110 } 111 } 112