1*ec4cfb91SJianguo Zhang /* 2*ec4cfb91SJianguo Zhang * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*ec4cfb91SJianguo Zhang * 4*ec4cfb91SJianguo Zhang * SPDX-License-Identifier: BSD-3-Clause 5*ec4cfb91SJianguo Zhang */ 6*ec4cfb91SJianguo Zhang 7*ec4cfb91SJianguo Zhang #include <assert.h> 8*ec4cfb91SJianguo Zhang #include <mtgpio.h> 9*ec4cfb91SJianguo Zhang #include <platform_def.h> 10*ec4cfb91SJianguo Zhang mt_gpio_find_reg_addr(uint32_t pin)11*ec4cfb91SJianguo Zhanguintptr_t mt_gpio_find_reg_addr(uint32_t pin) 12*ec4cfb91SJianguo Zhang { 13*ec4cfb91SJianguo Zhang uintptr_t reg_addr = 0U; 14*ec4cfb91SJianguo Zhang struct mt_pin_info gpio_info; 15*ec4cfb91SJianguo Zhang 16*ec4cfb91SJianguo Zhang assert(pin < MAX_GPIO_PIN); 17*ec4cfb91SJianguo Zhang 18*ec4cfb91SJianguo Zhang gpio_info = mt_pin_infos[pin]; 19*ec4cfb91SJianguo Zhang 20*ec4cfb91SJianguo Zhang switch (gpio_info.base & 0x0f) { 21*ec4cfb91SJianguo Zhang case 0: 22*ec4cfb91SJianguo Zhang reg_addr = IOCFG_RM_BASE; 23*ec4cfb91SJianguo Zhang break; 24*ec4cfb91SJianguo Zhang case 1: 25*ec4cfb91SJianguo Zhang reg_addr = IOCFG_LT_BASE; 26*ec4cfb91SJianguo Zhang break; 27*ec4cfb91SJianguo Zhang case 2: 28*ec4cfb91SJianguo Zhang reg_addr = IOCFG_LM_BASE; 29*ec4cfb91SJianguo Zhang break; 30*ec4cfb91SJianguo Zhang case 3: 31*ec4cfb91SJianguo Zhang reg_addr = IOCFG_RT_BASE; 32*ec4cfb91SJianguo Zhang break; 33*ec4cfb91SJianguo Zhang default: 34*ec4cfb91SJianguo Zhang break; 35*ec4cfb91SJianguo Zhang } 36*ec4cfb91SJianguo Zhang 37*ec4cfb91SJianguo Zhang return reg_addr; 38*ec4cfb91SJianguo Zhang } 39