1*7079a942SFengquan Chen /* 2*7079a942SFengquan Chen * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*7079a942SFengquan Chen * 4*7079a942SFengquan Chen * SPDX-License-Identifier: BSD-3-Clause 5*7079a942SFengquan Chen */ 6*7079a942SFengquan Chen #include <arch_helpers.h> 7*7079a942SFengquan Chen #include <common/debug.h> 8*7079a942SFengquan Chen #include <lib/mmio.h> 9*7079a942SFengquan Chen #include <dfd.h> 10*7079a942SFengquan Chen #include <plat_dfd.h> 11*7079a942SFengquan Chen 12*7079a942SFengquan Chen static uint64_t dfd_cache_dump; 13*7079a942SFengquan Chen static bool dfd_enabled; 14*7079a942SFengquan Chen static uint64_t dfd_base_addr; 15*7079a942SFengquan Chen static uint64_t dfd_chain_length; 16*7079a942SFengquan Chen 17*7079a942SFengquan Chen void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump) 18*7079a942SFengquan Chen { 19*7079a942SFengquan Chen mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL); 20*7079a942SFengquan Chen mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL); 21*7079a942SFengquan Chen mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL); 22*7079a942SFengquan Chen 23*7079a942SFengquan Chen mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, BIT(2)); 24*7079a942SFengquan Chen mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); 25*7079a942SFengquan Chen sync_writel(DFD_INTERNAL_CTL, 0x5); 26*7079a942SFengquan Chen mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); 27*7079a942SFengquan Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); 28*7079a942SFengquan Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); 29*7079a942SFengquan Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); 30*7079a942SFengquan Chen 31*7079a942SFengquan Chen mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); 32*7079a942SFengquan Chen mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); 33*7079a942SFengquan Chen mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); 34*7079a942SFengquan Chen mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); 35*7079a942SFengquan Chen 36*7079a942SFengquan Chen mmio_write_32(DFD_TEST_SI_0, 0x0); 37*7079a942SFengquan Chen mmio_write_32(DFD_TEST_SI_1, 0x0); 38*7079a942SFengquan Chen mmio_write_32(DFD_TEST_SI_2, 0x0); 39*7079a942SFengquan Chen mmio_write_32(DFD_TEST_SI_3, 0x0); 40*7079a942SFengquan Chen 41*7079a942SFengquan Chen sync_writel(DFD_POWER_CTL, 0xF9); 42*7079a942SFengquan Chen sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL); 43*7079a942SFengquan Chen sync_writel(DFD_V30_CTL, 0xD); 44*7079a942SFengquan Chen 45*7079a942SFengquan Chen mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); 46*7079a942SFengquan Chen mmio_write_32(DFD_O_REG_0, 0); 47*7079a942SFengquan Chen 48*7079a942SFengquan Chen /* setup global variables for suspend and resume */ 49*7079a942SFengquan Chen dfd_enabled = true; 50*7079a942SFengquan Chen dfd_base_addr = base_addr; 51*7079a942SFengquan Chen dfd_chain_length = chain_length; 52*7079a942SFengquan Chen dfd_cache_dump = cache_dump; 53*7079a942SFengquan Chen 54*7079a942SFengquan Chen if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { 55*7079a942SFengquan Chen mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL); 56*7079a942SFengquan Chen sync_writel(DFD_V35_ENABLE, 0x1); 57*7079a942SFengquan Chen sync_writel(DFD_V35_TAP_NUMBER, 0xB); 58*7079a942SFengquan Chen sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); 59*7079a942SFengquan Chen sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); 60*7079a942SFengquan Chen 61*7079a942SFengquan Chen /* Cache dump only mode */ 62*7079a942SFengquan Chen sync_writel(DFD_V35_CTL, 0x1); 63*7079a942SFengquan Chen mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF); 64*7079a942SFengquan Chen mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL); 65*7079a942SFengquan Chen mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL); 66*7079a942SFengquan Chen mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL); 67*7079a942SFengquan Chen mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL); 68*7079a942SFengquan Chen 69*7079a942SFengquan Chen if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) { 70*7079a942SFengquan Chen sync_writel(DFD_HW_TRIGGER_MASK, 0xC); 71*7079a942SFengquan Chen mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); 72*7079a942SFengquan Chen } 73*7079a942SFengquan Chen } 74*7079a942SFengquan Chen dsbsy(); 75*7079a942SFengquan Chen } 76*7079a942SFengquan Chen 77*7079a942SFengquan Chen void dfd_resume(void) 78*7079a942SFengquan Chen { 79*7079a942SFengquan Chen if (dfd_enabled == true) { 80*7079a942SFengquan Chen dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); 81*7079a942SFengquan Chen } 82*7079a942SFengquan Chen } 83